Lecturer 2 vhdl

Authored by Dr. Tri Caohuu& Vivek Verma 1

EE 179 – Lecture 2

VHDL Data TypesVHDL OperatorsVHDL AttributesVHDL Control StatementsOther Constructs in VHDL

Authored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy Davis

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VHDL Data Types

Type is a named set of values with common characteristics.Subtype is a subset of the values of a typeScalar is one-dimensional while composite is multidimensionalPhysical type is used for physical variables, i.e. variables that have unitsAccess type and File type facilitate access to external informationthrough disk files


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VHDL Data Types : Scalar

Enumeration

Numeric

Physical


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VHDL Data Types : Scalar

Access

Access type is really a pointer to the location of a string or location of an element of a file.Only used for behavioral simulation, since there is no hardware equivalentFileThe file variable my_file describes a text file in read mode. For write and read/write use ‘out’ and ‘inout’ keywords respectively.

read and readline are procedures definedin TEXTIO package of STD library.


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VHDL Data Types : Composite

Array

The array std_ulogic_1d is indexed by the 9 values of the enumeration type std_ulogic

Record

month_name must be defined as an enumeration


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VHDL Data Types

Pre-defined data types provided in VHDL libraries are

o Booleano bito bit_vectoro std_logic (std_ulogic)o std_logic_vector (std_ulogic_vector)o integero positiveo naturalo realo charactero stringo timeo fileo line


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VHDL Operators

Lower Precedence (Applied left to right)----------------------------------------------------------------------------Logical not , and, or, nand, nor, xorRelational =, /=, <, <=, >, >=Shift sll, srl, sla, sra, rol, rorAdding +, -, &Signing +, -Multiplying/Dividing *, /, mod, remMiscellaneous **, abs-----------------------------------------------------------------------------Higher Precedence (Applied left to right)

Relational operators are provided for scalar types and returnboolean . If type is composite, the test is carried on each andevery elementAdding operators are pre-defined for types integer and realFor user defined types, user must provide the operatorfunctionality (next slide)


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VHDL Operators : Overloading

VHDL provides for overloading operatorsFunctionality for the operator and possible operand types thatcan be used is provided using functions, for example

The overloaded operator ‘+’ can now be used with the right/left operands of typemy_data_type

Simulator implicitly calls a function when it encounters theoperator, as opposed to an explicit user-defined function call,for example


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VHDL Objects

There are three classes of objects in VHDLConstant – An object whose value cannot be changed

Variable – An object whose value can be changed but has no timedimension associated with it, and thus no hardware correspondence. Operations on variables are instantaneous.

Signal – An object whose value can be changed and has a timedimension associated with it. Each signal is driven by one or moredrivers. Incase of multiple drivers, a resolution function must bespecified


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VHDL Attributes

Attributes are characteristics of VHDL types orobjects separated by a tick mark (single quote), forinstance, S’EVENT (pronounced as “S tick EVENT”)The five categories of pre-defined attributes are

1. Value2. Function3. Signal4. Enumerated Type5. Array

VHDL also provides for implementation of userdefinedattributes


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VHDL Attributes : Signal

ExampleSignal attributes that return a value

Signal attributes that create and return a signal


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VHDL Attributes : Enumeration

Example

For enumerated types, pred and succ are equivalent to leftof and rightof respectivelyFor enumerated types, low and high are equivalent to left and right respectivelyThese equivalence do not hold for other data types and sub types


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VHDL Attributes : Array

Example


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VHDL Attributes

Function – Any attribute in the other categories that is associated with a pre-defined function for looking up values, for instance

Value – Any attribute in the other categories thatreturns a value, for instance


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VHDL Control Statements

Control statements in VHDL are very similar to thatof many other procedural languages such as C orPascalThey are all sequential, thus can only be used insideprocessesSome examples1. if…end if2. case3. loop4. wait5. exit6. next7. return


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VHDL Control Statements : If…End If

Conditions are evaluated from top to bottom

Example


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VHDL Control Statements : Case

The sets of choices must be mutually exclusiveThe keyword others is used to cover all remaining possiblevalues

Example


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VHDL Control Statements : Loop

Three forms of loop statementsFor loops

Example

Notice that the loop-index is implicitly/automatically declaredThe loop-index cannot be modified


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While loop

Example


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Simple loop

Requires a wait or exit statement to prevent infinite loopExample


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VHDL Control Statements : Wait

Commonly used to induce delay

Three different formsExample


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VHDL Control Statements

Next

Facilitates skipping certain iterations in a loop

Exit

Facilitates exiting a loop on a certain condition

Example


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Other VHDL Constructs : Block

Block is a bounded region of statements that has adeclarative part and an executable part. For instance,architecture is a block statementThe visibility of a local signal is limited to the blockor any nested blocks

In a guarded block, statements containing the word guarded will not be executed unlessthe guard_expression holds true


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Other VHDL Constructs : Block

Example

In this case, ((clk='1' and not clk‘stable) or clr='1') is the guard_expression. Signal s willchange to ‘0’ or d only if the guard_expression is true


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Other VHDL Constructs : Process

Processes execute concurrently to each other. They are sensitiveto a list of signals, on which any event causes the processes toexecute. There are two types of processes, implicit and explicit1. Implicit processes are represented by Concurrent Signal

Assignment (CSA) statements. Signals on the right hand side of aCSA act as its sensitivity list

2. Example


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Other VHDL Constructs : Process

Explicit processes are block statements inside which all statementsare executed sequentially

It can optionally have an explicitly defined sensitivity list, otherwise, a waitstatement must be used

Example


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Other VHDL Constructs : Procedure

Procedures are sub-programs that hold sequential statementsand only exist inside packagesProcedures do not return a value but are allowed to modify oneor more of its parameters.Procedures can have parameters of mode in, out or inout

Example


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Other VHDL Constructs : Function

As in procedural programming languages, functions are used to compute a value based on inputsFunctions only exist inside packagesInvocation of a function returns a single valueFunctions cannot modify the outside world, thus all parameters are assumed to be of mode inFunctions are executed instantaneously, in zero simulation time.It follows that procedures called from within functions cannothave wait statements


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Other VHDL Constructs : Function

Example


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Other VHDL Constructs : Component

A VHDL hardware module must be cast as a component beforeit can be instantiated for use

Specification is similar to the entity declarationThe actual inter-connects are defined by port map throughcomponent instantiation

Labels are used to differentiate between multiple instantiationsof a componentDefault mode of a port is in, it can be out, inout or buffer


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Other VHDL Constructs : Component

Example

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Lecturer 2 vhdl