Lecture3 Inverter Metrics 2up

8/3/2019 Lecture3 Inverter Metrics 2up

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EECS141 1Lecture #3

EE141EE141- - Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits

Lecture 3Lecture 3Switches, Inverters,Switches, Inverters,

and Design Metricsand Design Metrics

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EECS141 2Lecture #3

Administrative Stuff Administrative Stuff Discussions start tomorrow (Fri.)

(Next Mon. is Labor Day – may shift Mon.discussion to Fri. afternoon)

Labs start next weekEveryone should have an EECSinstructional account

Homework #1 is due todayHomework #2 due next Thursday



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EECS141 3Lecture #3

Class Material Class Material

Last lectureBasics of IC manufacturing, cost

Today’s lectureTransistor as switchesBuilding an inverter Design metrics

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EECS141 4Lecture #3

What is a Transistor? What is a Transistor?

|V GS |

An MOS Transistor

|V GS | ≥ |VT |

S DR on

A Switch!

S D

G



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EECS141 5Lecture #3

Switch Model of MOS Transistor Switch Model of MOS Transistor

|VGS |

S D

G

|V GS | < | V T| |V GS | > | V T |

R on

S D S D

GG

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EECS141 6Lecture #3

NMOS and PMOS NMOS and PMOS

V GS > 0

S D

G

V GS < 0

S D

G

NMOS Transistor PMOS Transistor



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EECS141 7Lecture #3

Building a CMOS inverter Building a CMOS inverter

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EECS141 8Lecture #3

Design Metrics Design Metrics

How to evaluate performance of adigital circuit (gate, block, …)?

CostReliabilitySpeed/Performance (delay, frequency)Power



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EECS141 9Lecture #3

Reliability Reliability The real world is analog

All physical quantities you deal with as a circuitdesigner are actually continuous

Thus, even a “digital” signal can be noisy:

i (t )

Inductive coupling Capacitive coupling Power and groundnoise

v(t ) V DD

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EECS141 10Lecture #3

Noise and Digital Systems Noise and Digital Systems Circuit needs to works despite “analog” noise

Digital gates can reject noiseThis is actually how digital systems are defined

Digital system is one where:Discrete values mapped to analog levels and backAll the elements (gates) can reject noise – For “small” amounts of noise, output noise is less than

input noiseThus, for sufficiently “small” noise, the system actsas if it was noiseless



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Noise Rejection Noise Rejection

Gain = ∞

V in

V out

V DD /2 V DD

V DD

Gain = 0

Gain = 0

To see if a gate rejects noiseLook at its DC voltage transfer characteristic (VTC)See what happens when input is not exactly 1 or 0

Ideal digital gate:Noise needs to belarger than V DD/2to have any effecton gate output

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More Realistic VTC More Realistic VTC

V(in)

V(out)

VOH

VOL

VM

VOHVOL

f V(out)=V(in)

Switching Threshold

Nominal Voltage Levels

VOH = f (VOL)VOL = f (VOH)VM = f (VM)



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Voltage Mapping Voltage Mapping

V IL V IH V in

Slope = -1

Slope = -1

V OL

V OH

V out

“ 0” V OL

V IL

V IH

V OH

UndefinedRegion

“ 1”

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Definition of Noise Margins Definition of Noise Margins

UndefinedRegion

Noise margin high:NMH = VOH – V IH

Noise margin low:NML = V IL – V OL

GateOutput

GateInput

NML

NMH

“0”

“1”

V OL

V OH

V IL

V IH

(Stage M) (Stage M+1)



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Digital Gate Noise Reduction: Digital Gate Noise Reduction: Regenerative Property Regenerative Property

A chain of inverters

v0 v1 v2 v3 v4 v5 v6

2

V ( V o

l t )

4

v0

v1v2

t (nsec)0

2 1

1

3

5

6 8 10Simulated response

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Regenerative Property (Another View)Regenerative Property (Another View)

v0

v1

v3

fin v(v)

f (v)

v3

out

v 2 in

Regenerative Non-Regenerativev2

v1

f (v)

fin v(v)

v3

out

v0 in



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Fan Fan - - in and Fan in and Fan - - out out

N

Fan-out N Fan-in M

M

There is a modified definition of fan-out for CMOS logic

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Key Reliability Properties Key Reliability Properties Absolute noise margin values are not the only thingsthat matter

e.g., floating (high impedance) nodes are moreeasily disturbed than low impedance nodes (interms of voltage)

Noise immunity (i.e., how well the gate suppressesnoise sources) needs to be considered too

Summary of some key reliability metrics:Noise transfer functions & margin (ideal: gain = ∞ , margin =Vdd /2)Output impedance (ideal: R o = 0)Input impedance (ideal: R i = ∞ )



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Example: An Old Example: An Old - - time Inverter time Inverter

NM H

V in (V)

V

o u t

( V )

NM L

V M

0.0

1.0

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0

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Example: An Old Example: An Old - - time Inverter time Inverter

V OH = 3.6VV OL = 0.4VV IL = 0.6VV IH = 2.3VNM H = V OH – V IH = 1.3VNM L = V IL – V OL = 0.2V



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Performance: Delay Definitions Performance: Delay Definitions

V out

t f

t pHL t pLH

t r

t

V in

t

90%

10%

50%

50%

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Fanout Fanout of Four (FO4) Delay of Four (FO4) Delay

tFO4

Want a way to characterize the delay of a circuit(roughly) independent of technology

Most common metric:Delay of an inverter driving four copies of itself (t FO4 )



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A First A First - - Order RC Network Order RC Network

v out

v in C

R

tp = ln (2) τ = 0.69 RC

Important model – matches delay of an inverter

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Power Dissipation Power Dissipation

Instantaneous power:p(t) = v(t)i(t) = Vsupplyi(t)

Peak power:Ppeak = Vsupplyipeak

Average power:

( )∫ ∫ + +

==T t

t

T t

t supplysupply

ave dt t iT

V dt t p

T P )(

1



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“ “ Power Power - - Delay Delay ” ” and Energy and Energy - - Delay Delay Want low power and low delay, so how aboutoptimizing the product of the two?

So-called “Power-Delay Product”

Power·Delay is by definition EnergyOptimizing this pushes you to go as slow aspossible

Alternative gate metric: Energy-Delay ProductEDP = (P av ·tp)·tp = E·t p

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Energy in CMOS Energy in CMOS v out

v in C L

R

The voltage on C L eventually settles to V DD

Thus, charge stored on the capacitor is C LVDDThis charge has to flow out of the power supply

So, energy is just Q·V DD = (C LVDD)·VDD



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Energy (the harder way)Energy (the harder way)

v out

v in C L

R

( ) ( ) ∫ ∫ ∫ ====→

DD V

DD Lout LDD

T T

DD DD DD V C dv C V dt t i V dt t P E 0

2

0 010

( ) ( ) ∫ ∫ ∫ ====

DD V

DD Lout out L

T T

Lout C C V C dv v C dt t i v dt t P E 0

2

0 021

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Summary Summary Understanding the design metrics thatgovern digital design is crucial

CostRobustnessPerformance/speedPower and energy dissipation



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Next Lecture Next Lecture

Detailed CMOS switch modelBuilding gates with switchesDesign rules

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Lecture3 Inverter Metrics 2up