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Lecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1

Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

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Page 1: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Lecture 6: Universal Gates

CSE 140: Components and Design Techniques for Digital Systems

Spring 2014

CK Cheng, Diba Mirza

Dept. of Computer Science and Engineering University of California, San Diego

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Page 2: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Combinational Logic: Other Types of Gates

§  Universal Set of Gates §  Other Types of Gates

1)  XOR 2)  NAND / NOR

3)  Block Diagram Transfers: Converting a circuit to an equivalent circuit

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Page 3: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Universal Set Universal Set: A set of gates such that every switching function can be implemented with gates in this set.

Ex:

{AND, OR, NOT}

{AND, NOT}

{OR, NOT}

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Page 4: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Universal Set Universal Set: A set of gates such that every Boolean function can be implemented with gates in this set.

Ex:

{AND, OR, NOT}

{AND, NOT} OR can be implemented with AND & NOT gates a+b = (a’b’)’

{OR, NOT} AND can be implemented with OR & NOT gates ab = (a’+b’)’

{XOR} is not universal

{XOR, AND} is universal 4

Page 5: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

iClicker

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Is the set {AND, OR} (but no NOT gate) universal? A. Yes B. No

Page 6: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Universal Set {AND, NOT} combined into a single gate:

{OR, NOT} combined into into a single gate:

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Page 7: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

1.  Implementing NOT using NAND 2. Implementing AND using NAND 3. Implementing OR using NAND

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Implementing NOT, AND and OR using NAND gates

Page 8: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

1.  Implementing NOT using NOR 2. Implementing OR using NOR 3. Implementing AND using NOR

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Implementing NOT, AND and OR using NOR gates

Page 9: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

1.  Implementing NOT using XOR X 1 = X.1’ + X’.1 = X’ if constant “1” is available. 2. Implementing OR using XOR and AND

Same as implementing OR using AND and NOT except NOT is implemented using XOR as shown above

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Universal gates {XOR, AND}

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Page 10: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Universal Set

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Remark: Universal set is a powerful concept to identify the coverage of a set of gates afforded by a given technology.

Page 11: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Other Types of Gates

(a)  Commutative X Y = Y X (b) Associative (X Y) Z = X (Y Z) (c)  1 X = X’ 0 X = 0X’ + 0’X = X (d) X X = 0, X X’ = 1

1) XOR X Y = XY’ + X’Y

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X Y

XY’ X’Y

Page 12: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

e) if ab = 0 then a b = a + b

Proof: If ab = 0 then a = a (b+b’) = ab+ab’ = ab’ b = b (a + a’) = ba + ba’ = a’b a+b = ab’ + a’b = a b

f) X XY’ X’Y (X + Y) X = ??

To answer, we apply Shannon’s Expansion.

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Page 13: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Shannon’s Expansion (for switching functions)

Formula: f (x,Y) = x * f (1, Y) + x’ * f (0, Y) Proof by enumeration: If x = 1, f (x,Y) = f (1, Y) : 1*f (1, Y) + 1’*f(0,Y) = f (1, Y) If x = 0, f(x,Y) = f (0, Y) : 0*f (1, Y) + 0’*f(0,Y) = f(0, Y)

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Page 14: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Back to our problem…

X XY’ X’Y (X + Y) X = ? Þ  X (XY’) (X’Y) (X + Y) X = f (X, Y)

If X = 1, f (1, Y) = 1 Y’ 0 1 1 = Y If X = 0, f (0, Y) = 0 0 Y Y 0 = 0

Thus, f (X, Y) = XY

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Page 15: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

XOR gates

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iClicker: a+(b c) = (a+b) (a+c) ? A. Yes B. No

Page 16: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

2) NAND, NOR gates

NAND, NOR gates are not associative

Let a | b = (ab)’

(a | b) | c ≠ a | (b | c)

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Page 17: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

3) Block Diagram Transformation

a) Reduce # of inputs.

ó

ó

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Page 18: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

b. DeMorgan’s Law

ó

(a+b)’ = a’b’

ó

(ab)’ = a’+b’ 18

Page 19: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

c. Sum of Products (Using only NAND gates)

ó ó

Sum of Products (Using only NOR gates)

ó ó

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Page 20: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

d. Product of Sums (NOR gates only)

ó ó

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Page 21: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

NAND, NOR gates

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Remark: Two level NAND gates: Sum of Products Two level NOR gates: Product of Sums

Page 22: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Part II. Sequential Networks

Memory / Timesteps

Clock

Flip flops Specification Implementation

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Page 23: Lecture 6: Universal Gatescseweb.ucsd.edu/classes/sp14/cse140-b/slides/140-sp14-lec6.pdfLecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Spring

Reading

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[Harris] Chapter 3, 3.1, 3.2