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EE241
1
UC Berkeley EE241 J. Rabaey, B. Nikolić
EE241 - Spring 2003Advanced Digital Integrated Circuits
Lecture 6MOS Logic Styles
UC Berkeley EE241 J. Rabaey, B. Nikolić
Reading� Chapter 7 in the text by K. Bernstein
� Background material from Rabaey
� References» [Rabaey 03] J.M. Rabaey “Digital Integrated
Circuits: A Design Perspective,” Prentice Hall2003.
» [Bernstein 98] K. Bernstein et al, “High-SpeedCMOS Design Styles,” Kluwer 1998.
» [Oklobdzija99] V.G. Oklobdzija, “High-Performance Systems: Circuits and Logic,” IEEEPress 1999.
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
CMOS Logic Styles
� CMOS tradeoffs:» Speed» Power (energy)» Area
� Design tradeoffs» Robustness, scalability
» Design time
� Many styles: don’t try to remember thenames – remember the principles
UC Berkeley EE241 J. Rabaey, B. Nikolić
CMOS Logic Styles
PUN
PDN
ABC
OUT
VDD
GND
ABC
Complementary
robustscales
large and slow
LOGICNETWORK
ABC
OUT
Pass Transistor Logic
simple and fastnot always very efficientversatile
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
CMOS Logic Styles
LOAD
ABC PDN
OUT
GND
GND
VDD
Ratioed Logic
small & faststatic power
RPDN <<RLOAD
VDD
PDN
φ
In1In2In3
Out
φ
CL
Dynamic Logic
Small & fastest!Noise issuesScales?
UC Berkeley EE241 J. Rabaey, B. Nikolić
Static CMOS
VDD
VSS
PUN
PDN
In1
In2
In3
F = G
In1
In2
In3
PMOS Only
NMOS Only
Complementary CMOS
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Complementary CMOS� Very robust, full swing, high noise margins
» But … high noise generation
� Fast to design, can synthesize� Implements all logic functions� No static power� Among other properties:
» Different pull-up and pull-down delays» Delay dependence on history» Crowbar current» Input capacitance consists of both P and N» Fast NAND, NOR, slow MUX, XOR
UC Berkeley EE241 J. Rabaey, B. Nikolić
Complementary CMOS
Courtesy of IEEE Press, New York. 2000
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Transfer Function and NoiseMargin
Courtesy of IEEE Press, New York. 2000
UC Berkeley EE241 J. Rabaey, B. Nikolić
VTC of Complementary CMOS Gates
0.0 1.0
Vin, V
V
o ut
, V
2.0 3.00.0
1.0
2.0
3.0
A � 1, B �
A � B � 0→1
B � 1, A �
int
B
VDD
A
M3 M4A
B
F
M2
M1
0→1
0→1
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Body Effect
UC Berkeley EE241 J. Rabaey, B. Nikolić
Delay Dependence on Input Patterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=1→0
A=1, B=1→0
A=1 →0, B=1
time [ps]
Vol
tage
[V]
81A= 1→0, B=1
80A=1, B=1→0
45A=B=1→0
61A= 0→1, B=1
64A=1, B=0→1
67A=B=0→1
Delay(psec)
Input DataPattern
NMOS = 0.5µm/0.25 µmPMOS = 0.75µm/0.25 µmCL = 100 fF
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Propagation Delays
tpHL
tpLH
tp
UC Berkeley EE241 J. Rabaey, B. Nikolić
Pulsed Static CMOSRH – Reset highRL – Reset low
Fast pull-up Fast pull-down
Chen, Ditlow, US Pat. 5,495,188 Feb. 1996.
Bring circuit in known state before transition
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
PS-CMOS� Advantages:
» No dynamic nodes – good noise immunity» High static performance (monotonic)» No data dependent delay (worst case gets better)» No false transitions (monotonic)» Smaller clock load than dynamic
� Disadvantages» Width of reset wave limits logic depth and clock
speed» Restricted connectivity» Complex clocking
UC Berkeley EE241 J. Rabaey, B. Nikolić
PS-CMOS
Evaluation and reset waves: reset is 1.5x slower
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Skewing Gates� Different rising and falling delays
2W
2W
4W
W
Good for H-to-L transition Good for L-to-H transition
UC Berkeley EE241 J. Rabaey, B. Nikolić
Ratioed Logic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Pseudo-NMOS
0.0 0.5 1.0 1.5 2.0 2.50.0
0.5
1.0
1.5
2.0
2.5
3.0
Vin, V
Vo
ut,
V
W/Lp = 4
W/Lp = 2
W/Lp = 1
W/Lp = .25
W/Lp = 0.5
VDD
In1In2In3
F
PMOSload
PDN
Trade-off between performance and power + noise margins
UC Berkeley EE241 J. Rabaey, B. Nikolić
Differential Logic
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Differential Logic� Differential Cascode Voltage Switch (DCVS)
� Differential Split-Level (DSL)
� Cascode Non-Threshold Logic (CNTL)
� Regenerative Push-Pull Cascode Logic(PPCL)
� Pass transistor logic families
� Dynamic logic families
UC Berkeley EE241 J. Rabaey, B. Nikolić
Differential Logic+ implicit invert, higher logic density
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Cascode Voltage Switch LogicVDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
AABB
M1 M2
Cascode Voltage Switch Logic (CVSL)
Sometimes called Differential Cascode Voltage Switch Logic (DCVSL)
UC Berkeley EE241 J. Rabaey, B. Nikolić
CVSL
A
B
M1
M2
A B
0 0.2 0.4 0.6 0.8 1.0-0.5
0.5
1.5
2.5
Time, ns
Vol
tage
,V
Out
Out
A,BA,BM3 M4
OutOut
VDD - Vth
Fast (but hysteresis due to latch function)No static power dissipationBUT: large cross-over current!
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
CVSL
Full adder design
How to design for reduced transistor count?
UC Berkeley EE241 J. Rabaey, B. Nikolić
Karnaugh Map Technique
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Karnaugh Map Technique
0
1
00 01 11 10x1
x2x3
0
0
0 01
1 1 1
Build sharedcubes first!
Add othercubes next
LOAD
x1
x3
x1
x3
x2 x2
Q Q
LOAD
x1
x3
x1
x3
x2 x2
Q Q
x1x2
UC Berkeley EE241 J. Rabaey, B. Nikolić
Example
Q = x1x2x3x4 + x1(x2+x3+x4)
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Using Ordered BDDs
BDD = Binary Decision Diagrams
UC Berkeley EE241 J. Rabaey, B. Nikolić
Push-Pull Cascode Logic
Gieseke et al, U.S. Patent 5,023,480 June 1991.
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
DSL Differential Split-Level Logic
UC Berkeley EE241 J. Rabaey, B. Nikolić
But … Consumes Static Power
EE241
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Simulation Results for Different Adders
UC Berkeley EE241 J. Rabaey, B. Nikolić
Cascode Non-Threshold Logic
Use negative feedbackto limit LOHCapacitors used fordecoupling
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Optimizing the Intrinsic RC-Delay
UC Berkeley EE241 J. Rabaey, B. Nikolić
Progressive Sizing
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Uniform versus Progressive Sizing
Uniform
kn-1
kn-1
N
Non-uniform
1
k
k2
kn-1
UC Berkeley EE241 J. Rabaey, B. Nikolić
Sizing Models
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UC Berkeley EE241 J. Rabaey, B. Nikolić
Case Study
UC Berkeley EE241 J. Rabaey, B. Nikolić
Example: Progressive Scaling ofNMOS Devices in DOMINO CMOS