Lecture 5: Decision and Control

CS 2011

Fall 2014, Dr. Rozier

LOGISTICS

Logistics

9/16 – Today9/18 – Continued Instructions

9/23 – Continued Instructions9/25 – Exam Review

9/30 – Midterm I

LADIES AND TIGERS

The Lady and the Tiger

• Two doors containing either Ladies or Tigers

The Lady and the Tiger

• Once again, you’ll have to tell Ladies from Tigers

• A new twist is being added.– In Room I, if a lady is in the room, the sign will be

true. If a tiger is in the room, the sign will be false.– In Room II, the situation is the opposite!

The Lady and the TigerQ1

Room I

Both rooms contain ladies.

Room II

Both rooms contain ladies.

The Lady and the TigerQ1

Room I Room II

The Lady and the TigerQ2

Room I

At least one room contains a lady

Room II

The other room contains a lady

The Lady and the TigerQ2

Room I Room II

The Lady and the TigerQ3

Room I

It makes no difference which room you pick.

Room II

The other room contains a lady.

The Lady and the TigerQ3

Room I Room II

CURRENT PROGRAM STATUS REGISTER

CPSR

• The Current Program Status Register– Special register that holds information on the side

effects of instructions.

– Condition code flags• N – Negative result from the ALU• Z – Zero result from the ALU• C – ALU operation Carried out• V – ALU operation oVerflowed

CPSR

Operand 1 – 32 bits

Operand 2 – 32 bits

Result – 32 bits

CPSR

Flag Logical Inst Arith Inst

N = 1 No meaning Bit 31 of the result has been set. Indicates a negative number for signed operations

Z = 1 Result bits are all zero

Result of the operation was zero

C = 1 After shift operation a ‘1’ was left in the carry

Result was greater than 32 bits

V = 1 No meaning Result was greater than 31 bits, possible corruption of sign bit

CPSR

• The CPSR bits are set by:

• Compare/Test instructions:– The only effect of a comparison is to

UPDATE THE CONDITIONS FLAGS.CMP : op1 – op2CMN: op1 + op2TST: op1 AND op2TEQ: op1 EOR op2

CPSR

• The CPSR bits are set by:

• Data processing operations do not normally effect CPSR!– Can be caused to effect them by

adding the S bit of the instruction.

CPSR

• The CPSR bits are set by:

• Data processing operations and CPSR– Add the “S” suffix to set the “S” bit.– ADDS– SUBS– ANDS

Conditional Execution

• The NZCV flags form the basis for conditional execution in the ARM, one of its most powerful features.– Most architectures must use “branch” or “jump”

instructions.– The ARM can enable or disable individual

instructions based on the CPSR.

Conditional Execution

Conditional Execution

• EQ – enable this instruction if the results of the last CMP or “S” instruction indicate equality:

Example:CMP r0, r1ADDEQ r0, r0, r1

Conditional Execution

• To understand conditional execution, let’s think in terms of CMP.– CMP r0, r1

• What does this mean to the processor?

Conditional Execution

• To understand conditional execution, let’s think in terms of CMP.– CMP r0, r1

• r0 - r1, and set NZCV flags

– EQ is the conditional execution suffix for r0 == r1. – NE is the conditional execution suffix for r0 != r1. – HI is the unsigned conditional execution suffix for r0 > r1– LO is the unsigned conditional execution suffix for r0 < r1

In groups, what are the values of NZCV that enable these conditionals?

Conditional Execution

• To understand conditional execution, let’s think in terms of CMP.– CMP r0, r1

• r0 - r1, and set NZCV flags

– HS is the conditional execution suffix for r0 >= r1. – LS is the conditional execution suffix for r0 <= r1.

In groups, what are the values of NZCV that enable these conditionals?

Conditional Execution

• How would you build GT, GE and LT, LE (the signed equivalents)?

Conditional ExecutionCode Suffix Meaning Code Suffix Meaning

0000 EQ Z = 1 1001 LS C = 0 || Z = 1

0001 NE Z = 0 1010 GE (N=1 && V=1) || (N=0 && V=0)

0010 HS/CS C = 1 1011 LT (N=1 && V=0) || (N=0 && V=1)

0011 LO/CC C = 0 1100 GT Z=0 && ((N=1 && V=1) || (N=0 && V=0))

0100 MI N = 1 1101 LE Z=1 || ((N=1 && V=0) || (N=0 && V=1))

0101 PL N = 0 1110 AL Always

0110 VS V = 1 1111 NV Reserved/deprecated

0111 VC V = 0

1000 HI C = 1 && Z = 0

BRANCHING

Branching

• Conditional execution isn’t the only tool in our belt.

Branching

• Branches allow us to transfer control of the program to a new address.– b (<suffix>) <label>– bl (<suffix>) <label>

b startbl start

Branching

• Basic branches do not operate on registers.

• Typically we branch to an indicated LABEL, example:

MAIN:b END

END:b MAIN

Branching

• Branches are calculated by the assembler relative to the current address.– Allows branching +/- 32 Mbytes

• Branch stores the target address in the Program Counter

• Branch and link also stores the next address in the link register.

Branch (b)

• Branch, possibly conditionally, to a new address.

beq subroutine @ If Z=1, branch

• Good practice to use bal instead of b.

Branch with link (bl)

• Branch, possibly conditionally, to a new address.– Before the branch is complete, store the PC in the

LR.– Allows easy return from the branch.

bleq subroutine @ If Z=1, branch, saving the PC

Branch with link (bl)

• How do we get back once we’ve saved the PC?

mov pc, lr

• Moves the contents of the link register to the program counter.

Implementing If Statements

• C code:if (i == j) f = g+h;else f = g - h;

• ARM code cmp r0, r1 @ Set flags via r0-r1 and discard

beq Elseadd r2, r3, r4 @ r2 = r3 + r4bal Exit

Else:sub r2, r3, r4 @ r2 = r3 + r4

Exit:

Implementing Loop Statements

• C code:while (i < j) i += 1;

• ARM code Loop:

cmp r0, r1bge Exitadd r0, r0, #1bal Loop

Exit:

i < j?i < j?

i=i+1i=i+1

i<j

ExitExit

i>=j

Basic Blocks• A basic block is a sequence of instructions with

– No embedded branches (except at end)– No branch targets (except at beginning)

A compiler identifies basic blocks for optimization

An advanced processor can accelerate execution of basic blocks

For next time

Continue discussion of Chapter 2 on Thursday.