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ECE 274 - Digital LogicLecture 5

Lecture 5Introduction - Sequential Logic DesignStoring One Bit

SR LatchD flip-flop

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Digital DesignSequential Logic Design – Controllers: Bit Storage

BitStorage

Call

Cancelbutton

button

Bluelight

Flight-attendant call-button system. Pressing Call turns on the light, which stays on after Call is released. Pressing Cancel turns off the light.

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

QS

First (failed) attempt at using feedback to store a bit.

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

QS

t

00 0

S

Q 10

t10

QS

t

10 0 QS

t

10

1 QS

t

11

1

10

QS

t

01

1(a) (b) (c) (d) (e)

Q stays 1 forever

Tracing the behavior of our first attempt at bit storage.

QS

t

00 0

S

Q 10

t10

QS

t

10 0 QS

t

10

1 QS

t

11

1

10

QS

t

01

1(a) (b) (c) (d) (e)

Q stays 1 forever

QS

t

00 0

S

Q 10

t10

QS

t

10 0 QS

t

10

1 QS

t

11

1

10

QS

t

01

1(a) (b) (c) (d) (e)

Q stays 1 forever

QS

t

00 0

S

Q 10

t10

QS

t

10 0 QS

t

10

1 QS

t

11

1

10

QS

t

01

1(a) (b) (c) (d) (e)

Q stays 1 forever

QS

t

00 0

S

Q 10

t10

QS

t

10 0 QS

t

10

1 QS

t

11

1

10

QS

t

01

1(a) (b) (c) (d) (e)

Q stays 1 forever

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

Q

S (set)

R (reset)

SR latchBasic SR latch2 cross-coupled NOR gates2 inputs: Set & Reset2 outputs: Q’ and QFeedback loop

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

Q

S=0

R =1

0

0 1

1

t SR

t

Q

10101010

SR latch when S=0 and R=1.Q(next) = 0

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

Q

S=0

R =0

0

0 1

1

t SR

t

Q

10101010

SR latch when S=0 and R=0.Q(next) = Q

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

Q

S=1

R =0

1

1 0

0

t SR

t

Q

10101010

SR latch when S=1 and R=0.Q(next) = 1

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

Figure 3.9

Flight attendant call-button system using a basic SR latch.

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

What happens when you Set (S=1) & Reset (R=1) at the same time?

S=1 and R=1 causes problems –Q oscillates when SR return to 00.

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

Q eventually settles to either 0 or 1, due to race condition.

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

Possible Solution:Introduce circuitry to prevent S=R=1

0.2 ns

0.8 ns

Will it Work?

Reality: NOT ALWAYS… due to the delay of the inverter and AND gate.

Conceptually: YES … S and R can’t both be 1 in this sample circuit.

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

1 ns

Glitches: Temporary values on signals caused by gate delays.

Gate Delays: can cause S=R=1.

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Digital DesignSequential Logic Design -- Controllers : Bit Storage

Level-sensitive SR latch = SR latch + enable input C.

S1 = 0 S1 = 0

S1 = S S1 = S

C1

0

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Digital DesignSequential Logic Design -- Controllers

Level-sensitive SR latch -- an SR latch with enable input C.

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Digital DesignSequential Design – Controllers: Synchronous Circuits

MHz, GHz -> speeds of a processorTime is measured by clocksA clock is used to co-ordinate & synchronize events;

Clock cycle time

Related to datapath cycle time

1 cycle

Rising edge Falling edge

Clock = 1

Clock = 0

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Digital DesignSequential Design – Controllers: Synchronous Circuits

Figure 3.17

Timing Input Changes:Circuit inputs (i.e. S & R) should only change while Clk=0, such that latch inputs will be stable when Clk=1.

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Digital DesignSequential Logic Design – Controllers: Bit Storage

But How Do We Prevent S=R=1 once & for all?!?!?(caveat: assumes you are using C responsibly)

Make a D (data)-Latch

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Digital DesignSequential Logic Design – Controllers: Bit Storage

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Digital DesignSequential Logic Design – Controllers: D-Latch

D latch symbol

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Digital DesignSequential Logic Design – Controllers: Registers

A problem with latches – through how many latches will Y propagate for each pulse of Clk_A? For Clk_B?

What the heck?!?!?

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Digital DesignSequential Design – Controllers: Latch: Signal Propagation

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Digital DesignSequential Design – Controllers: Bit Storage: Flip-Flop

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Digital DesignSequential Logic Design – Controllers: Bit Storage

D Q

Clk !Q

D Q

Clk !Q

Latch Flip-Flop

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Digital DesignSequential Logic Design – Controllers: Bit Storage

Through how many flip-flops will Y propagate for each pulse of Clk_A? For Clk_B?

Not AGAIN?!?!?

One flip-flop exactly per pulse, for either clock signal.

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Digital DesignSequential Logic Design -- Controllers

Positive (shown on the left) and negative (right) edge-triggered D flip-flops. The sideways triangle input represents an edge-triggered clock

input.

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Digital DesignSequential Logic Design – Controllers: Bit Storage

Latch versus Flip-Flop Timing

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Digital DesignSequential Logic Design – Controllers: Flight Call System

D Truth Table for call-button system

/Q(next)

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Digital DesignSequential Logic Design -- Controllers: Flight Call System

Flight attendant call-button system:

(a) block diagram

(b) implemented using a D flip-flop.

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Digital DesignSequential Logic Design – Controllers: Bit Storage

Increasingly-better bit storage blocks, leading to the D flip-flop