Lecture 35: Chapter 6

• Today’s topic– I/O Overview

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Introduction

• I/O devices can be characterized by– Behaviour: input, output, storage– Partner: human or machine– Data rate: bytes/sec, transfers/sec

• I/O bus connections

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Dependability

• Fault: failure of a component– May or may not lead

to system failure

Service accomplishmentService delivered

as specified

Service interruptionDeviation from

specified service

FailureRestoration

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Dependability Measures

• Reliability: mean time to failure (MTTF)• Service interruption: mean time to repair

(MTTR)• Mean time between failures

– MTBF = MTTF + MTTR

• Availability = MTTF / (MTTF + MTTR)• Improving Availability

– Increase MTTF: fault avoidance, fault tolerance, fault forecasting

– Reduce MTTR: improved tools and processes for diagnosis and repair

4

Disk Storage

• Nonvolatile, rotating magnetic storage

5

Disk Sectors and Access

• Access to a sector involves– Queuing delay if other accesses are pending– Seek: move the heads– Rotational latency– Data transfer– Controller overhead

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Disk Access Example

• Given– 512B sector, 15,000rpm, 4ms average

seek time, 100MB/s transfer rate, 0.2ms controller overhead

• Average read time– 4ms seek time

+ ½ / (15,000/60) = 2ms rotational latency+ 512 / 100MB/s = 0.005ms transfer time+ 0.2ms controller delay= 6.2ms

• If actual average seek time is 1ms– Average read time = 3.2ms

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Typical x86 PC I/O System

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Bus Design

• The bus is a shared resource – any device can send data on the bus (after first arbitrating for it) and all other devices can read this data off the bus

• The address/control signals on the bus specify the intended receiver of the message

• The length of the bus determines its speed (hence, a hierarchy makes sense)

• Buses can be synchronous (a clock determines when each operation must happen) or asynchronous (a handshaking protocol is used to co-ordinate operations)

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Memory-Mapped I/O

• Each I/O device has its own special address range

The CPU issues commands such as these: sw [some-data] [some-address]

Usually, memory services these requests… if the address is in the I/O range, memory ignores it

The data is written into some register in the appropriate I/O device – this serves as the command to the device

11

Polling Vs. Interrupt-Driven

• When the I/O device is ready to respond, it can send an interrupt to the CPU; the CPU stops what it was doing; the OS examines the interrupt and then reads the data produced by the I/O device (and usually stores into memory)

• In the polling approach, the CPU (OS) periodically checks the status of the I/O device and if the device is ready with data, the OS reads it

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Direct Memory Access (DMA)

• Consider a disk read example: a block in disk is being read into memory

• For each word, the CPU does a lw [destination register] [I/O device address] and a sw [data in above register] [memory-address]

• This would take up too much of the CPU’s time – hence, the task is off-loaded to the DMA controller – the CPU informs the DMA of the range of addresses to be copied and the DMA lets the CPU know when it is done

DMA/Cache Interaction

• If DMA writes to a memory block that is cached– Cached copy becomes stale

• If write-back cache has dirty block, and DMA reads memory block– Reads stale data

• Need to ensure cache coherence– Flush blocks from cache if they will be used for

DMA– Or use non-cacheable memory locations for I/O

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