Lecture 28- Oversampled ADCs & Final Remarks

7/25/2019 Lecture 28- Oversampled ADCs & Final Remarks

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EECS 247 Lecture 28: Oversampled ADCs Cont'd & Final Remarks 2007H. K. Page 1

EE247

Lecture 28 Administrative

Extra office hours next week @ 563 Cory:

Wed. Dec. 12th, 2pm-4pm

Thurs. Dec. 13th, 10am-12pm

Project submission:

Deadline extended: Thurs. Dec. 13th or Frid. Dec. 14th

If you have chosen to do the project, please make an

appointment with the instructor for 15mins per each project report

to present the results:

Thurs. Dec. 13th, after 1pm or

Frid. Dec.14th after 10am


EE247Lecture 28

Higher order modulators

Cascaded modulators (MASH) (last lecture)

Forward path multi-order filter (continued)

Bandpass modulators

Testing of modulator front-end

Acknowledgements

Examples of systems utilizing analog-digital interface circuitry(not part of final exam)


2/31


Higher Order Modulators(2) Multi-Order Filter

Zeros of NTF (poles of H(z)) can be strategically positioned to

suppress in-band noise spectrum Approach: Design NTF first and solve for H(z)

( ) 1( ) ( ) ( )

1 ( ) 1 ( )

H zY z X z E z

H z H z= +

+ +

E(z)

X(z) Y(z)( )H z

Y( z ) 1N T F

E( z ) 1 H( z )= =

+


Example: Modulator Specification

Example: Audio ADC

Dynamic range DR 18 Bits

Signal bandwidth B 20 kHz

Nyquist frequency fN 44.1 kHz

Modulator order L 5

Oversampling ratio M = fs/fN 64

Sampling frequency fs 2.822 MHz

The order L and oversampling ratio M are chosen

based on SQNR > 120dB


3/31


Noise Transfer Function, NTF(z)

% stop-band attenuation Rstop=80dB, L=5 ...

L=5;

Rstop = 80;

B=20000;

[b,a] = cheby2(L, Rstop, B, 'high');

% normalize

b = b/b(1);

NTF = filt(b, a, ...);

104 106-100

-80

-60

-40

-20

0

20

Frequency [Hz]

NTF

[dB]

Chebychev 2 filter chosen

zeros in stop-band


Loop-Filter CharacteristicsH(z)

( ) 1NTF

( ) 1 ( )

1( ) 1

Y z

E z H z

H zNFT

= =+

=

104

106

-20

0

20

40

60

80

100

Frequency [Hz]

Loop

filter

H

[dB]


4/31


Modulator Topology

Simulation Model

Q

I_5I_4I_3I_2I_1

Y

b2b1

a5a4a3a2a1

K1 z-1

1 -z-1

I1

gDAC Gain Comparator

X

-1

1 -z-1

I2

K2 z-1

1 -z-1

I3

K3 z-1

1 -z-1

I4

K4 z -1

1 -z-1

I5

K5 z

+1

-1

Filter


-40 -35 -30 -25 -20 -15 -10 -5 0

-20

-15

-10

-5

0

5

10

i1i2i3i4

i5q

Input [dBV]

Loop

filterpea

kvo

ltages

[V]

Internal Node Voltages

Internal signal peak

amplitudes are weak

function of input level

(except near overload)

Maximum peak-to-

peak voltage swing

approach +-10V!

Exceed supply

voltage!

Solutions:

Reduce Vref??

Node scaling

Integrator outputs

Quantizer input


5/31


Node Scaling Example:

3rd Integrator Output Voltage Scaled by

K3 * , b1 /, a3 / , K4 / , b2 *

Vnew=Vold*

Q

I_5I_4I_3I_2I_1

Y

b2b1

a5a4a3a2a1

K1 z-1

1 -z-1

I1


X

-1

1 -z-1

I2

K2 z-1

1 -z-1

I3

K3 z-1

1 -z-1

I4

K4 z -1

1 -z-1

I5

K5 z

EECS 247 Lecture 28: Oversampled ADCs Cont'd & Final Remarks 2007 H. K. Page 10

Node Voltage Scaling

-40 -35 -30 -25 -20 -15 -10 -5 0-1.5

-1

-0.5

0

0.5

1

1.5

Input [dBV]

Loopfilterpeakvoltages

[V]

=1/10

k1=1/10;

k2=1;

k3=1/4;

k4=1/4;

k5=1/8;

a1= 1;

a2=1/2;

a3=1/2;

a4=1/4;

a5=1/4;

b1=1/512;b2=1/16-1/64;

g =1;

Integrator output range reasonable for new parameters

But: maximum input signal limited to -5dB (-7dB with safety) fix?


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Input Range Scaling

Increasing the DAC levels by using higher value forgreduces theanalog to digital conversion gain:

Increasing VIN& gby the same factor leaves 1-Bit data unchanged

gzgH

zH

zV

zD

IN

OUT 1

)(1

)(

)(

)(

+=

Loop FilterH(z)

VINDOUT

+1 or -1

Comparator

g


Scaled Stage 1 Model

g modified:

From 1 to 2.5;

Overload

input level

shifted up by

8dB

-40 -35 -30 -25 -20 -15 -10 -5 0-1.5

-1

-0.5

0

0.5

1

1.5

Input [dBV]

Loop

filterpea

kvo

ltages

[V]

+2dB


7/31


Stability Analysis(not included in final exam)

Approach: linearize quantizer and use linear system theory!

One way of performing stability analysis use RLocus in Matlab with

H(z) as argument and Geff as variable

Effective quantizer gain

Can obtain Geff from simulation

22

2

yG

eff q

=

H(z)

Quantizer Model

e(kT)

x(kT)y(kT)Geff

q(kT)

Ref: R. W. Adams and R. Schreier, Stability Theory for Modulators, in Delta-Sigma DataConverters- S. Norsworthy et al. (eds), IEEE Press, 1997


Stability Analysis

Zeros of STF same as zeros of H(z)

Poles of STF vary with G

For G=0 (no feedback) poles of the STF same as poles of H(z) For G=large, poles of STF move towards zeros of H(z)

Draw root-locus: for G values for which poles move to LHP (s-plane) or

inside unit circle (z-plane) system is stable

( )

( )

( ) ( )

( )

( )

( ) ( )

1

G H zSTF

G H z

N zH z

D z

G N zSTF

D z G N z

=

+

=

=

+


8/31


Modulator z-Plane Root-Locus

As Geff increases, poles of STF

move from

poles of H(z) (Geff= 0) to

zeros of H(z) (Geff= )

Pole-locations inside unit-circle

correspond to stable STF and

NTF

Need Geff> 0.45 for stability

Geff = 0.45

z-Plane Root Locus

0.6 0.7 0.8 0.9 1 1.1

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4 Increasing Geff

Unit Circle


-40 -35 -30 -25 -20 -15 -10 -5 0 50

0.2

0.4

0.6

0.8

Input [dBV]

Effec

tive

Quan

tizer

Ga

in

Geff=0.45

stable unstable

Large inputs comparator

input grows

Output is fixed (1)

Geffdrops

modulator unstable for

large inputs

Solution:

Limit input amplitude

Detect instability (long

sequence of +1 or -1)

and reset integrators

Be ware that signals

grow slowly for nearly

stable systems use

long simulations

Effective Quantizer Gain, Geff


9/31


5th Order Modulator

Final Parameter Values

2.5V

Stable input range with margin ~ 1V

1/10 1 1/4 1/4 1/8

1/512 1/16-1/64

1 12 1/2 1/4 1/4

Input range

~ 1V

Q

I_5I_4I_3I_2I_1

Y

b2b1

a5a4a3a2a1

K1 z-1

1 -z-1

I1


X

-1

1 -z-1

I2

K2 z-1

1 -z-1

I3

K3 z-1

1 -z-1

I4

K4 z -1

1 -z-1

I5

K5 z

1


Summary Oversampled ADCs decouple SQNR from circuit

complexity and accuracy

If a 1-Bit DAC is used, the converter is to 1st order,inherently linearindependent of component matching

Typically, used for high resolution & low frequencyapplications e.g. digital audio

2nd order used extensively due to lower levels of limitcycle related spurious tones compared to 1st order

modulators of order greater than 2: Cascaded (multi-stage) modulators

Single-loop, single-quantizer modulators with multi-orderfiltering in the forward path


10/31


Bandpass Modulator

+

_

vIN

dOUT

DAC

Replace the integrator in 1st order lowpass with a

resonator 2nd order bandpass

Resonator


Bandpass ModulatorExample: 6th Order

Measured output

for a bandpass (prior to digitalfiltering)

Key Point:

NTF notchtypeshape

STFbandpassshape

Ref:

Paolo Cusinato, et. al, A3.3-V CMOS 10.7-MHz Sixth-Order Bandpass Modulator with 74-dBDynamic Range , JSSCC, VOL. 36, NO. 4, APRIL 2001

Input SinusoidQuantization

Noise


11/31


Bandpass Characteristics

Oversampling ratio defined asfs/2B whereB= signal bandwidth

Typically, sampling frequency is chosen to befs=4xfcenterwherefcenter bandpass filter centerfrequency

STF has a bandpass shape while NTF has anotch shape

To achieve same resolution as lowpass, needtwice as many integrators


Bandpass Modulator Dynamic RangeAs a Function of Modulator Order (K)

Bandpass resolution for order K is the same as lowpass resolution with order L= K/2

K=4

15dB/Octave

K=6

21dB/Octave

K=2

9dB/Octave


12/31


Example: Sixth-Order Bandpass Modulator

Ref:

Paolo Cusinato, et. al, A 3.3-V CMOS 10.7-MHz Sixth-Order Bandpass Modulator with 74-dBDynamic Range , JSSCC, VOL. 36, NO. 4, APRIL 2001

Simulated noise transfer function Simulated signal transfer function


Example: Sixth-Order Bandpass Modulator

Ref:

Paolo Cusinato, et. al, A 3.3-V CMOS 10.7-MHz Sixth-Order Bandpass Modulator with 74-dBDynamic Range , JSSCC, VOL. 36, NO. 4, APRIL 2001

Features & Measured PerformanceSummary

fs=4xfcenter

B

OSR=fs/2B


13/31


Modulator Front-End Testing

Should make provisions for testing the modulator (AFE) separate from the

decimator (digital back-end)

Data acquisition board used to collect 1-bit digital output atfs rate

Analyze data in a PC environment or dedicated test equipment in manufacturing

environments can be used

Need to run DFT on the collected data and also make provisions to perform the

function of digital decimation filter in software

Typically, at this stage, parts of the design phase behavioral modeling effort can

be utilized

Good testing strategy vital for debugging/improving challenging designs

AFE DataAcq.

PCMatlab

fs

FilteredSinwave


SummaryOversampled ADCs

Noise shaping utilized to reduce baseband quantization noisepower

Reduced precision requirement for analog building blockscompared to Nyquist rate converters

Relaxed transition band requirements for analog anti-aliasingfilters

Utilizes low cost, low power digital filtering

Speed is traded for resolution

Typically used for lower frequency applications compared toNyquist rate ADCs


14/31


Material Covered in EE247

Filters Continuous-time filters

Biquads & ladder type filters

Opamp-RC, Opamp-MOSFET-C, gm-C filters

Automatic frequency tuning

Switched capacitor (SC) filters

Data Converters D/A converter architectures

A/D converter

Nyquist rate ADC- Flash, Interpolating & Folding,Pipeline ADCs,.

Self-calibration techniques Oversampled converters


Acknowledgements

The course notes for EE247 are based on

numerous sources including:

Prof. P. Grays EE290 course

Prof. B. Bosers EE247 course notes

Prof. B. Murmanns Nyquist ADC notes

Fall 2004 & 05 & 06 EE247 class feedback

Last but not least, Fall 2007 EE247 class The instructor would like to thank the class of 2007 for

their enthusiastic & active participation!


15/31


Systems Including Analog-Digital Interface Circuitry

(Not Included in Final Exam)

Wireline communications

Telephone related (DSL, ISDN, CODEC)

Television circuitry (Cable modems, TV tuners)

Ethernet (10/1Gigabit, 10/100BaseT)

Wireless

Cellular telephone (CDMA, Analog, GSM.)

Wireless LAN (Blue tooth, 802.11a/b/g..)

Radio (analog & digital), Television

Disk drives

Fiber-optic systems


E.E. Circuit Coursevs. Frequency Range

DC500MHz

Baseband

IF Band

RF Band

455kHz 100MHz

500kHz 100GHz

10.7MHz 80MHzAM Radio FM Radio Cellular Phone

EE240, EE247

EE242


16/31


Wireline Communications

Telephone Based


Data Transmission Over Existing Twisted-PairPhone Lines

Xmitter

Receiver

Central Office

Backbone

DigitalNetwork

POTS

Xmitter

Receiver

Data transmitted over existing phone lines covering distances close to

3.5miles Voice-band MODEMs (up to 56Kb/s)

ISDN (160Kb/s)

HDSL, SDSL,

ADSL (up to 8Mb/s)

Customer

Twisted Pair

3 to 5km


17/31


Data Transmission Over Twisted-Pair Phone Lines

ISDN (U-Interface) Transceiver

Full duplex transmission (RX & TX signals sent simultaneously)

160kbit/sec baseband data (80kHz signal bandwidth)

Standardized line code 2B1Q (4 level code 3:1:-1:-3)

Max. desired loop coverage 18kft (~36dB signal attenuation) Final required BER (bit-error-rate) 10-7 (min. SNDR=27dB)

Xmitter

Receiver

Central Office

Backbone

DigitalNetwork

POTS

Xmitter

Receiver

Customer

Twisted Pair

3 to 5km


ISDN (U-Interface) TransceiverEcho Problem

Central Office

Transformer coupling to line

For a perfectly matched system no leakage of TX signal into RX path

Unfortunately, system has poor matching + complicating factor of bridged-

taps

Customer

Xmitter

Receiver

Xmitter

Receiver

Open

Line

Bridged

Tap

Problem


18/31


ISDN (U-Interface) Transceiver

Echo ProblemCentral Office

System full duplex transmission RX & TX signals sent simultaneous (& at thesame frequency band)

Leakage of TX signal to RX path (echo)

Worst case echo could be 30dB higher compared to the receivedsignal!!

Customer

Xmitter

Receiver

Xmitter

Receiver


ISDN (U-Interface) TransceiverEcho Cancellation

Echo cancellation performed in the digital domain Typically echo cancellation performed by transversal adaptive digital filter

Any non-linearity incurred by the analog circuitry makes echo cancellersignificantly more complex

Desirable to have high linearity analog circuitry (75dB range)


19/31


Simplified Transceiver Block Diagram

CMA Control, maintenance & access unit

DFE Decision feedback equalizer

DEC Decimation filter

REC Reconstruction filter

LEC & NECLinear/non-linear echo-canceller

Ref: H. Khorramabadi, et. al"An ANSI standard ISDN transceiver chip set, " IEEE International

Solid-State Circuits Conference, vol. XXXII, pp. 256 - 257, February 1989


Analog Front-End2b S.C.

DAC

2ndorder

ButterworthS.C. Filter

Class A/B

Line Driver

13bit2ndOrder

To avoid stringentrequirements for non-

linear echo canceller:

high linearity analog

circuitry needed (~ 75dB)

Peak signal frequency80kHz


20/31


Data Transmission Over Twisted-Pair Phone Lines

DSL (Digital Subscriber Loop)

HDSL &SDSL more like ISDN @ higher frequencies Full duplex transmission with RX & TX signals on the same

frequency band

Xmitter

Receiver

Central Office

Backbone

DigitalNetwork

POTS

Xmitter

Receiver

Customer

Twisted Pair

3 to 5km


Data Transmission Over Twisted-Pair Phone LinesADSL (Asymmetric Digital Subscriber Loop)

In USA mostly ADSL FDM (frequency division multiplex)

Signal from CO to customer on a different band compared tocustomer to CO

Echo cancellation can be performed by simple filtering

Data rates up to 8Mbps (much higher compared to ISDN)

Xmitter

Receiver

Central Office

Backbone

DigitalNetwork

POTS

Xmitter

Receiver

Customer


21/31


ADSL Signal Characteristics

Main difference compared to ISDN: TX & RX signals on different

frequency bands

Downstream (fast, from CO to customer) 138kHz to 1.1MHz

Upstream (slow, from customer to CO) 30kHz to 138kHz

Echo cancellation much easier

More severe signal attenuation at high frequencies (1MHz DSL v.s.

80kHz ISDN)


Typical ADSL Analog Front-End

ADC 16/14b with 14bit linearity, pipeline with auto. calibration @ 5Ms/s DAC 16/14b with 14bit linearity, with auto. calibration

On-chip filters 3rd to 4th order LPF withfc 1.1MHz for downstream and 138kHz upstream(typically continuous-time type filters with on-chip frequency tuning)Ref: D.S. Langford, et al, A BiCMOS Analog Front-End Circuit for an FDM-Based ADSL System,

IEEE Journal of Solid State Circuits, Vol. 33, No. 9, pp. 1383-1393, Dec. 1998.

Central Office

Customer Premise


22/31


Typical ADSL Analog Front-End

Note: Band selection filtersare off-chip due to stringentnoise requirements(3nV/rtHz) Discrete LC type

Line driver on aseparate bipolarchip to achieverequired highoutput signal levels

with high powerefficiency typically+-12V supply


Wireless Communication

Circuits


23/31


Wireless Circuits

Differ from wired comm. circuits

Includes RF circuitry+IF

circuitry+baseband circuits (three different

frequency ranges)

Signal scenarios in wireless receivers more

challenging

Requirement for received signal BER in the

order of 10-3 for voice-only(min. SNR~9dB)


Typical Cellular PhoneBlock Diagram

RFAmp

A/D

Digital

Signal

Processor

(DSP)

A/D

90

ImageRejectFilter

Duplexer

D/A

D/A

FrequencySynthesizer

90

PA

AGCAGC

AGC

IFFilter


24/31


Superheterodyne Receiver

One or more intermediate frequency (IF)

Periodic signal at a frequency equal to the desired RX signal + or IF frequencyis provided by a Local Oscillator

RX signal is frequency shifted to a fixed frequency (IF filter center frequency)

RFAmp

Image

RejectFilter

Frequency

Synthesizer

AGC

f1

fc = f2 -f1f2 -f1 f2 + f1

f2 -f1 f2 + f1f2


RF Superheterodyne ReceiverExample: CDMA Receiver

Received frequency is mixed down to a fixed IF

frequency and then filtered with a bandpass filter

RFAmp

ImageReject

Filter

Frequency

Synthesizer

AGCAGC

880MHz

965.38MHz

fc =85.38MHz

BW=1.25MHz

870M 893.3MHz85.38MHZ

RX Band


25/31


Why Image Reject Filter?

Any signal @ the image frequency of the RX signal with respectto Osc. frequency will fall on the desired RX signal and causeimpairment

RFAmp


fIF= f2 -f1f2 -f1f3 f2

f2 -f1 f2 + f1f2f1 f3f2

fIFfIF

f2 + f1


Why Image Reject Filter?

Image reject filter attenuate signals out of the RX band

Typically, image reject filters are ceramic or LC type filters

RFAmp


fIF= fosc -f1

fosc -f1

foscf1 f3fosc

fIFfIF

Image

RejectFilter

f1 f3


26/31


Quadrature Downconversion

In systems with phase or freq. modulation, since signal is not symmetric

aroundfIF , directly converting down to baseband corrupts thesidebands

Quadrature downconversion overcomes this problem

A/D

A/D

In-phase &

Quadrature

Channel Select

Filters

fIF-fIF0

sinC t

cosCt

RFAmp

AGC


Effect of Adjacent Channels

Adjacent channels can be as much as 60dB higher compared to the desired RXsignal!

Linearity of stages prior and including channel selection filters extremely important

RFAmp

fn1fRX fn2

2nd

Adjacent

Channel

1st

Adjacent

Channel

RelativeSignalAmplitude[dB]

0

30

60

DesiredChannel

fn1 fn2

RelativeSignalAmplitude[dB]

0

30

60

2fn1fn2 2fn2fn1

RFAmp


27/31


Effect of Adjacent Channels

Due to existence of large unwanted signals & limiteddynamic range for the front-end circuitry: Can not amplify the signal up front due to linearity issues

Need to allocate amplification/filtering numbers to RX blockscarefully

Can only amplify when unwanted signals are filteredadequately

System design critical with respect to tradeoffs affecting:

Gain

Linearity

Power dissipation

Chip area


Homodyne (Direct to Baseband) Receivers

No intermediate frequency, signal mixed directly down to baseband

Almost all of the filtering performed at baseband

Higher levels of integration possible Issue to be aware of:

Requirements for the baseband filters more stringent

Since the local oscillator frequency is exactly at the same freq. as the RXsignal freq. can cause major DC offsets & drive the receiver front-endinto non-linear region


f1

fIF =0

RFAmp

A/D

A/D

90

AGC

fosc = f1


28/31


Example: Wireless LAN 802.11b & Bluetooth

Ref: H. Darabi, et al, A Dual Mode 802.11b/Bluetooth Radio in 0.35um CMOS, IEEE

ISSCC, 2003 pp. 86-87.

2MHz IF


Digital IF Receiver(IF sampling)

IF signal is converted to digitalmost of signal processing performed in

the digital domain Performance requirement for ADC more demanding in terms of noise,

linearity, and dynamic range!

With advancements of ADCs could be the architecture of choice in thefuture

A/DDigital

Sinewave

GeneratorsinC t

cosCt

RF

Amp

AGC

Digital

Multiplier

Digital

LPFDigital

Multiplier

Digital

LPF


29/31


Typical Wireless Transmitter

D/A

D/A

90

PA

AGC

D

S

P

Transmit signal shipped from DSP to the analog front-end in the form of

I& Q signals

Signal converted to analog form by D/A

Lowpass filter provides signal shaping In-phase & Quad. Components combined and then mixed up to RF

Power amplifier amplifies and provides the low-impedance output

Frequency

Synthesizer


Analog Filters in Super-Heterodyne WirelessTransceivers

RF

Amp

A/D

Digital

Signal

Processor

(DSP)

A/D

90

Image

Reject

Filter

Duplexer

D/A

D/A

Frequency

Synthesizer

90

PA

AGCAGC

AGC

Filters Function Type

RF Filter Image Rejection Ceramic or LC

IF Filter Channel selection SAW

Base-band Filters Channel Selection Integrated Cont.-Time

& Anti-aliasing for ADC or S.C.

IF

Filter


30/31


Example: Dual Mode CDMA (IS95)& Analog Cellular Phone


Example: Dual Mode CDMA (IS95)& AnalogCellular Phone

Baseband analog circuitry includes: CDMA

4bit flash type ADC clock rate 10MHz

8bit segmented TX DAC clock rate 10MHz (shared with FM)

7th order elliptic RX lowpass filter corner freq. 650kHz

3rd order chebyshev TX lowpass filter corner freq. 650kHz

FM (analog) 8bit successive approximation ADCs clock rate 360kHz

5th order chebyshev RX lowpass filter corner frequency 14kHz

3rd order butterworth TX lowpass filter corner frequency27kHz


31/31


Summary

Examples of systems utilizingchallenging analog to digital interfacecircuitry- in the area of wireline &wireless systems discussed

Analog circuits still remain the interface connecting the digital world to the

real world!

Documents

Lecture 28- Oversampled ADCs & Final Remarks