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Lect12: Memory Devices and Subsystem

Maeng Lect 12-2

FLASH Memory

FLASH memory

• Similar to EPROMs in many ways

– nonvolatile, read just like an EPROM, and program with an EPROM-like algorithm

• Different in several ways

– memory cells are erased electrically (not byte erasable and writeable)

– erase process is complex and take as long as several seconds( Unlike RAM)

– write operation take a long time when compared to the write cycle times of a RAM

• Bulk-Erase, Boot Block, and FlashFileTM FLASH Memory FLASH memory array architecture : See Fig 10.27

• Bulk-erase type

– single block, the contents of all storage locations are cleared

• Boot block

– asymmetrical in size, boot block, parameter blocks, main blocks

– in-system programming

• Flashfile

– equal sized blocks

Maeng Lect 12-3

FLASH memory

• Standard Bulk-Erase FLASH Memories Types : 28F256 256k bits 32Kx8; 28F512, 28F010, 28F020 2M bits 256K x 8 Pin layout : See Fig 10.29 Quick-erase algorithm : See Fig 10.30

• Command registers : See Fig 10.31

• Standard Boot Block FLASH Memories Embedded microprocessor applications Types: 28F002(2MB), 28F004(4MB) 28F008(8MB); See Fig 10.33 Block Diagram: See Fig 10.34, See Fig 10.35

• Standard FlashFile FLASH Memories Types: 28F008SA, 28F016SA/SV

• large code storage applications and to implement solid-state mass-storage devices such as the FLASH card and FLASH drive

• See Fig 10.36

Maeng Lect 12-4

Memory Modules

• DRAM Example) 64K x 4 DRAM

• High Performance, CMOS silicon gate process

• 512-cycle refresh in 8 ms

• Optional FAST PAGE MODE access cycle

Maeng Lect 12-5

Memory Modules

• DRAM Modules 30-pin single-in-line memory module

Maeng Lect 12-6

• DRAM Modules 72-pin single-in-line memory module

Maeng Lect 12-7

Advanced DRAM Architectures

• New DRAM Types SDRAM(Synchronous DRAM), EDO(Extended data-out DRAM), RAMBUS DRAM, SyncLin

k DRAM, ... Bandwidth (Scaling) is the issue

• Clock rate scaling

• Data transfer

• Bus width

• Synchronous DRAM Differences

• Synchronized Operation(CLK input)

• Multiple Bank Architecture Example) 2x2Mx4 Bits MB81117422E - 125/-100/-84/-67

Maeng Lect 12-8

Maeng Lect 12-9

• RAMBUS RDRAM Rambus Inc.

• Silicon Graphics Indigo, Nintendo 64 Video game system, ...

• Intel’s decision to get behind the Rambus Approach

• Rambus licensee: Hitachi, Hyundai, LG, NEC, Samsung,... Direct Rambus Technology

• 1.6 GB/s from a single DRAM

• Rambus channel: 18 data pins cycling at 800Mbps per pin

Maeng Lect 12-10