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Lecture 11: Sequential Circuit Design Slide 2 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits2 Outline Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking Slide 3 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Sequential Logic 11: Sequential Circuits3 Slide 4 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits4 Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline Slide 5 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits5 Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high Delay fast tokens so they dont catch slow ones. Slide 6 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits6 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence Slide 7 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits7 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, D latch Flip-flop (or Register): edge triggered A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams Transparent Opaque Edge-trigger Slide 8 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Latch versus Register Latch stores data when clock is low D Clk Q D Q Register stores data when clock rises Clk D D QQ Slide 9 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Latches 11: Sequential Circuits9 Slide 10 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ Slide 11 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Characterizing Timing 11: Sequential Circuits11 Slide 12 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits12 Latch Design Pass Transistor Latch Pros +Tiny +Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970s Slide 13 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits13 Latch Design Transmission gate +No V t drop - Requires inverted clock Slide 14 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits14 Latch Design Inverting buffer +Restoring +No backdriving +Fixes either Output noise sensitivity Or diffusion input Inverted output Slide 15 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits15 Latch Design Tristate feedback +Static Backdriving risk Static latches are now essential because of leakage Slide 16 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits16 Latch Design Buffered input +Fixes diffusion input +Noninverting Slide 17 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits17 Latch Design Buffered output +No backdriving Widely used in standard cells + Very robust (most important) -Rather large -Rather slow (1.5 2 FO4 delays) -High clock loading Slide 18 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits18 Latch Design Datapath latch +smaller +faster - unbuffered input Slide 19 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits19 Flip-Flop Design Flip-flop is built as pair of back-to-back latches Slide 20 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits20 Enable Enable: ignore clock when en = 0 Mux: increase latch D-Q delay Clock Gating: increase en setup time, skew Slide 21 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits21 Reset Force output low when reset asserted Synchronous vs. asynchronous Slide 22 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits22 Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and reset Slide 23 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits23 Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches Slide 24 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits24 Timing Diagrams t pd Logic Prop. Delay t cd Logic Cont. Delay t pcq Latch/Flop Clk->Q Prop. Delay t ccq Latch/Flop Clk->Q Cont. Delay t pdq Latch D->Q Prop. Delay t cdq Latch D->Q Cont. Delay t setup Latch/Flop Setup Time t hold Latch/Flop Hold Time Contamination and Propagation Delays Slide 25 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits25 Max-Delay: Flip-Flops Slide 26 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits26 Max Delay: 2-Phase Latches Slide 27 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits27 Max Delay: Pulsed Latches Slide 28 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits28 Min-Delay: Flip-Flops Slide 29 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits29 Min-Delay: 2-Phase Latches Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! Slide 30 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits30 Min-Delay: Pulsed Latches Hold time increased by pulse width Slide 31 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Itanium 2 ALU 11: Sequential Circuits31 Slide 32 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Combinational Logic Delays ElementPropagation DelayContamination Delay Adder590 ps100 ps Result Mux60 ps35 ps Early Bypass Mux110 ps95 ps Middle Bypass Mux80 ps55 ps Late Bypass Mux70 ps45 ps 2 mm Wire100 ps65 ps 11: Sequential Circuits32 Slide 33 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits33 Time Borrowing In a flop-based system: Data launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system Data can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle Slide 34 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits34 Time Borrowing Example Slide 35 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits35 How Much Borrowing? 2-Phase Latches Pulsed Latches Slide 36 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits36 Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time Decreases maximum propagation delay Increases minimum contamination delay Decreases time borrowing Slide 37 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits37 Skew: Flip-Flops Slide 38 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits38 Skew: Latches 2-Phase Latches Pulsed Latches Slide 39 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits39 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) Slide 40 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits40 Safe Flip-Flop Past years used flip-flop with nonoverlapping clocks Slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk Slide 41 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits41 Adaptive Sequencing Designers include timing margin Voltage Temperature Process variation Data dependency Tool inaccuracies Alternative: run faster and check for near failures Idea introduced as Razor Increase frequency until at the verge of error Can reduce cycle time by ~30% Slide 42 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Conventional CMOS Latches 11: Sequential Circuits42 Slide 43 CMOS VLSI DesignCMOS VLSI Design 4th Ed. More CMOS Latches 11: Sequential Circuits43 Slide 44 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Clocked CMOS Latches Sometimes called C 2 MOS Actually, similar to (d) in that it is tristate 11: Sequential Circuits44 Slide 45 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Conventional CMOS Flip-Flops 11: Sequential Circuits45 Slide 46 CMOS VLSI DesignCMOS VLSI Design 4th Ed. CMOS Flip-Flops This design has a potential race condition. Is more likely if there is skew between the two phases of the clock. One alternative is NORA (NO Race) flip-flop. The other alternative is to use non-overlapping clocks. 11: Sequential Circuits46 Slide 47 CMOS VLSI DesignCMOS VLSI Design 4th Ed. NORA Flip-flops 11: Sequential Circuits47 Slide 48 CMOS VLSI DesignCMOS VLSI Design 4th Ed. NORA Flip-flops 11: Sequential Circuits48 Slide 49 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Pulse Generators 11: Sequential Circuits49 Slide 50 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Pulsed Latches The Naffziger pulsed latch is used in Itanium 2 processors. It consists of the latch from (k) and the generator from (b). The pulse width is 1/6 the clock cycle. The pulse generator of (d) is used in the NEC RISC processor. Note that pulses are very fast and have to be distributed in the latch. The Partovi pulsed latch (used on the AMD K6 and Athlon) builds the pulse generator into the latch. 11: Sequential Circuits50 Slide 51 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Pulsed Latches 11: Sequential Circuits51 Slide 52 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Resettable Latches and Flip-flops There are two types of reset: Asynchronous Synchronous Settable latches and flip-flops force the output high rather than low. 11: Sequential Circuits52 Slide 53 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Resettable Latches and Flip-flops 11: Sequential Circuits53 Slide 54 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Asynchronous Set and Reset 11: Sequential Circuits54 Slide 55 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Enabled Latches and Flip-flops 11: Sequential Circuits55 Slide 56 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Logic in Latches The sequencing overhead can be reduced by incorporating logic into latches. The DEC Alpha 21164 used a whole assortment of such latches. 11: Sequential Circuits56 Slide 57 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Klass Semidynamic FF (SDFF) A cross between pulsed latch and a flip-flop. Used in Sun UltraSparc III along with built in logic. 11: Sequential Circuits57 Slide 58 CMOS VLSI DesignCMOS VLSI Design 4th Ed. SDFF Similar to the Partovi pulsed latch. However, it uses a dynamic NAND gate. Faster than the Partovi pulsed latch. Worse skew tolerance and time borrowing capability. 11: Sequential Circuits58 Slide 59 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Differential Flip-flops 11: Sequential Circuits59 Slide 60 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Differential Flip-flops The design in (a) was used in the Alpha 21164. The SR latch formed by the NAND gates is just a salve and can be replaced by inverters if necessary. The StrongArm 110 processor adds the weak nMOS transistor to reduce the risk when the inputs switch while the clock is high. The AMD K6 uses the design in (b) at the interface between static and domino logic. 11: Sequential Circuits60 Slide 61 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Dual Edge Triggered FFs DET flip flops have a similar thoroughput at half the clock frequency. 11: Sequential Circuits61 Slide 62 CMOS VLSI DesignCMOS VLSI Design 4th Ed. DET FFs Zhao implicitly pulsed DET FF. 11: Sequential Circuits62 Slide 63 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Radiation Hardened FFs 11: Sequential Circuits63 Slide 64 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Some Design Guides Dynamic latches and registers have been avoided since the 0.35 m technology node. Use static latches and register. Include provisions for testing We will study these later. Clock distribution, especially multiple phases are problematic. We will study later. Unless required performance is at the cutting edge, use registers. 11: Sequential Circuits64 Slide 65 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Some Design Guides Pulsed latches are best in terms of performance. Remember that they have long hold times. Extra circuitry may be necessary for short logic paths. 11: Sequential Circuits65 Slide 66 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Characterizing Delays 11: Sequential Circuits66 Slide 67 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Characterizing Delays The set-up time cannot be crisply defined. If the data changes slightly less than a set-up time before the clock edge, the register will still capture the correct value, but its clock-Q delay will be high. Note that t DQ has a minimum when the slope of t CQ is -1. t setup is defined as the t DC at this point. The propagation delay is the t CQ at this point. The contamination delay t ccq is the minimum t CQ that occurs when the input arrives early. The hold time is the minimum delay from clock to D 11: Sequential Circuits67 Slide 68 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Characterizing Delays 11: Sequential Circuits68 Slide 69 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Characterizing Delays The aperture width, t a is the width of the window around the clock edge during which the data must not transition if the register is to produce the correct output with a propagation delay less than t pcq. 11: Sequential Circuits69 Slide 70 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Characterizing Delays 11: Sequential Circuits70 Slide 71 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Characterizing Delays If the data arrives before the clock rises (t DCr > 0), it must wait for the clock. In this region, t CrQ is nearly constant and t DQ increases as the data arrives earlier. If the data arrives after the clock rises, t DQ is essentially independent of arrival time. The data must set up before the falling edge of the clock. If the data arrives too close to the falling edge, t DQ increases. 11: Sequential Circuits71 Slide 72 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Characterizing Delays Choose the setup time before the knee of the curve, for example 5% greater than its minimum value. Pulsed latches have different definitions, but they can be converter to ordinary latches by adding or subtracting pulse widths. 11: Sequential Circuits72 Slide 73 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Delay Trade-offs 11: Sequential Circuits73 Slide 74 CMOS VLSI DesignCMOS VLSI Design 4th Ed. State Retention Registers 11: Sequential Circuits74 Slide 75 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Level Conversion 11: Sequential Circuits75 Slide 76 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Design Margins Designers derate their circuits by about 30% to cope with variations. Adaptive sequential elements seek to reduce this margin. Dynamic voltage scaling Precharacterize the circuit Canary circuit Double sampling the input 11: Sequential Circuits76 Slide 77 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Adaptive Sequencing 11: Sequential Circuits77 Slide 78 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Adaptive Sequencing (a) shows the conceptual diagram of a razor flip-flop, while (b) is the timing diagram. The razor flip-flop has the drawback that it may become metastable if D changes during the aperture. An improvement is double sampling with time borrowing (DSTB). (d) shows the Razor II pulsed latch. 11: Sequential Circuits78 Slide 79 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Synchronizers A synchronizer is a circuit that accepts an input that can change at arbitrary times and produces an output aligned to its clock. This is impossible to do in a finite time. 11: Sequential Circuits79 Slide 80 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Metastability 11: Sequential Circuits80 Slide 81 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Metastability 11: Sequential Circuits81 Slide 82 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Metastability 11: Sequential Circuits82 Slide 83 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Metastability The cross-coupled inverters behave like an amplifier with gain G when A is near the metastable voltage V m. The delay can be modeled with an RC network. Let the initial voltage be A and a small offset from the metastable point be a(0). 11: Sequential Circuits83 Slide 84 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Metastability Assume that the node reaches a legal logic level when The time to reach this level is Note that the speed is given by the RC time constant. High GBW is required. 11: Sequential Circuits84 Slide 85 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Synchronizers 11: Sequential Circuits85 Slide 86 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Synchronizers 11: Sequential Circuits86 Slide 87 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Synchronizers The probability of a synchronizer failure is The mean time between failures is 11: Sequential Circuits87 Slide 88 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Degrees of Synchrony ClassificationPeriodic ff Description SynchronousYes00Signal has same frequency and phase as clock. Example: register to register on chip. MesosynchronousYesConstant0Signal has same frequency, but is out of phase with clock. Safe to sample by delaying. Example: chip tp chip where both chips are using the same clock. PlesiosynchronousYesVaries slowly SmallSignal has nearly the same frequency. Phase drifts slowly with time. Safe to sample signal if it is delayed by a variable, but predictable amount. Example: Board to board with same frequency but different crystals. PeriodicYesVaries rapidly LargeSignal is periodic at arbitrary frequency. Board to board with different crystals. AsynchronousNoUnknown Signal changes arbitrarily. 11: Sequential Circuits88 Slide 89 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Asynchronous Domains 11: Sequential Circuits89 Slide 90 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Asynchronous Domains 11: Sequential Circuits90 Slide 91 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Two-Phase Handshake 11: Sequential Circuits91 Slide 92 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Arbiters An arbiter decides which of the two inputs came first. 11: Sequential Circuits92 Slide 93 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Pipelining 11: Sequential Circuits93 Slide 94 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Wave Pipelining 11: Sequential Circuits94 Slide 95 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Schmitt Triggers 11: Sequential Circuits95 Slide 96 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Noise Suppression 11: Sequential Circuits96 Slide 97 CMOS VLSI DesignCMOS VLSI Design 4th Ed. CMOS Schmitt Trigger 11: Sequential Circuits97 Slide 98 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Schmitt Trigger Simulated VTC 2.5 V X (V) V M2 V M1 V in (V) Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of the PMOS deviceM 4. The width is k* 0.5 m. m 2.0 1.5 1.0 0.5 0.0 0.51.01.52.02.5 V x (V) k = 2 k = 3 k = 4 k = 1 V in (V) 2.0 1.5 1.0 0.5 0.0 0.51.01.52.02.5 Slide 99 CMOS VLSI DesignCMOS VLSI Design 4th Ed. CMOS Schmitt Trigger 2 11: Sequential Circuits99 Slide 100 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Multivibrator Circuits Slide 101 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Transition-Triggered Monostable Slide 102 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Monostable Trigger (RC-based) Slide 103 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Astable Multivibrators (Oscillators) 11: Sequential Circuits103 Slide 104 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Relaxation Oscillator Slide 105 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Voltage Controller Oscillator (VCO) Slide 106 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Differential Delay Element and VCO in 2 two stage VCO v 1 v 2 v 3 v 4 V ctrl V o 2 V o 1 in 1 delay cell simulated waveforms of 2-stage VCO Slide 107 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Pitfalls and Fallacies Incompletely reporting flip-flop delay. Failing to check hold times. Choosing a sequencing method too late in the design. Failing to synchronize asynchronous inputs. Building faulty synchronizers. 11: Sequential Circuits107 Slide 108 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits108 Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing Pulsed Latches: Fast, some skew tol & borrow, hold time risk