LECTURE 050 - PN JUNCTIONS AND CMOS TRANSISTORSaicdesign.org/SCNOTES/2010notes/Lect2UP050_(100430).pdf · LECTURE 050 - PN JUNCTIONS AND CMOS TRANSISTORS LECTURE ORGANIZATION Outline

Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-1

CMOS Analog Circuit Design © P.E. Allen - 2010

LECTURE 050 - PN JUNCTIONS AND CMOS TRANSISTORSLECTURE ORGANIZATION

Outline• pn junctions• MOS transistors• Layout of MOS transistors• Parasitic bipolar transistors in CMOS technology• High voltage CMOS transistors• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 29-43



PN JUNCTIONSHow are PN Junctions used in CMOS?• PN junctions are used to electrically isolate one semiconductor region from another• PN diodes• ESD protection• Creation of the thermal voltage for bandgap purposes• Depletion capacitors – voltage variable capacitors (varactors)

Components of a pn junction:1.) p-doped semiconductor – a semiconductor having atoms containing a lack ofelectrons (acceptors). The concentration of acceptors is NA in atoms per cubiccentimeter.2.) n-doped semiconductor – a semiconductor having atoms containing an excess ofelectrons (donors). The concentration of these atoms is ND in atoms per cubiccentimeter.



Abrupt PN Junction

060121-02

p+ semiconductor n semiconductor

Metal-semiconductor junction pn junction Metal-semiconductor junction


Depletion RegionW

xW1 0 W2

W1 = Depletion width on p side W2 = Depletion width on n side

1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.2. As these fixed atoms lose their free carriers, they build up an electric field, which

opposes the diffusion mechanism.3. Equilibrium conditions are reached when:

Current due to diffusion = Current due to electric field



Influence of Doping Level on the Depletion RegionsIntuitively, one can see that the depletion regions are inversely proportional to the dopinglevel. To achieve equilibrium, equal and opposite fixed charge on both sides of thejunction are required. Therefore, the larger the doping the smaller the depletion regionon that side of the junction.The equations that result are:

W1 = 2 ( o -vD)

qNA 1 +NAND

1

NA

and

W2 = 2 ( o -vD)

qND 1 +NDNA

1

ND

Assume that vD = 0, o = 0.637V and ND = 1017 atoms/cm3. Find the p-side depletionregion width if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:

For NA = 1015 atoms/cm3 the p-side depletion width is 0.90 μm.

For NA = 1019 atoms/cm3 the p-side depletion width is 0.9 nm.



Graphical Characterization of the Abrupt PN JunctionAssume the pn junction is open-circuited.

Cross-section of an ideal pn junction:

060121-03


xpxn

xd

+ −vDiD

Symbol for the pn junction:Built-in potential, o:

o = Vt lnNAND

ni2 ,

where

Vt = kTq

ni is the intrinsic concentration of silicon.060121-04

0

Impurity Concentration (cm-3)

ND

NA

x

0

Impurity Concentration (cm-3)

qND

x-W1

-qNA

W2

x

Electric Field (V/cm)

E0

x

Potential (V)

ψο

xd

iD

vD+ -

vD+ -

iD

Fig. 06-03



Reverse-Biased PN JunctionsDepletion region:

xd = xp + xn = W1 + W2

xp = W1 vR

and

xn = W2 vR

Breakdown voltage (BV):If vR > BV, avalanche multiplication will

occur resulting in a high conduction state asillustrated.

vR

iD

vD

060121-05

+− vR = 0V

+− vR > 0V

xd

xd

Influenceof vR ondepletion

region width

vD

iD

BV

060121-06

ReverseBias

ForwardBias



Breakdown Voltage as a Function of DopingIt can be shown that†:

BV si(NA + ND)2qNAND E

2max

where Emax = 3x105 V/cm for silicon.

An example:Assume that ND = 1017 atoms/cm3.

Find BV if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:

NA = 1015 atoms/cm3:

If NA << ND, then BV si

2qNA E2

max = 1.04x10-12·9x1010

2·1.6x10-19·1015 = 291V

NA = 1019 atoms/cm3:

If NA >> ND, then BV si

2qND E2

max = 1.04x10-12·9x1010

2·1.6x10-19·1017 = 2.91V

† P. Allen and D. Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford University Press, 2002



Depletion CapacitancePhysical viewpoint of the depletion capacitance:

Cj = siAd =

siAW 1+W2

= siA

2 si( o-vD)q(ND+NA)

NDNA

+NAND

= AsiqNAND

2(NA+ND) 1o-vD

= Cj0

1 -vD

o

060204-01 + −vD

xd

W2W1

+− +− +−+− +− +−

d

060204-02

Cj0

Cj

vD0 ψo

Reverse Bias

Ideal

Gummel-Poon Effect



Forward-Biased PN JunctionsWhen the pn junction is forward-biased, the potential barrier is reduced and significantcurrent begins to flow across the junction. This current is given by:

iD = Is expvDVt

- 1 where Is = qADppno

Lp +Dnnpo

Ln qAD

L ni

2

N = KT 3exp-VGO

Vt

Graphically, the iD versus vD characteristics are given as:

-40 -30 -20 -10 0 10 20 30 40vD/Vt

iDIs

10

8

6

4

2

0

x1016

x1016

x1016

x1016

x1016

-5

0

5

10

15

20

25

-4 -3 -2 -1 0 1 2 3 4

iDIs

vD/Vt

060204-03

ln(iD/Is)

vD

Decade currentchange/60mV or Octave currentchange/18mV

0V



Graded PN JunctionsIn practice, the pn junction is graded rather than abrupt.

060204-04

p+n+

xx

ImpurityConcentration

0Surface Junction

Impurity profileapproximates aconstant slope

p+

IntrinsicConcentration

The previous expressions become:Depletion region widths-

W1 =2 si( o-vD)NDqNA(NA+ND)

m

W2 =2 si( o-vD)NAqND(NA+ND)

m W 1N

m

Depletion capacitance-

Cj = AsiqNAND

2(NA+ND)m

1

o-vD m

= Cj0

1 -vD

om

where 0.33 m 0.5.



Metal-Semiconductor JunctionsOhmic Junctions: A pn junction formed by a highly doped semiconductor and metal.

Energy band diagram IV Characteristics

ContactResistance

1

I

V

��

Vacuum Level

qφm qφsqφB EC

EF

EV

Thermionic or tunneling

n-type metal n-type semiconductor Fig. 2.3-4

Schottky Junctions: A pn junction formed by a lightly doped semiconductor and metal.Energy band diagram IV Characteristics

I

V

��

qφBECEF

EVn-type metal

Forward Bias

Reverse Bias

Reverse Bias

Forward Bias

n-type semiconductor Fig. 2.3-5



MOS TRANSISTORPHYSICAL ASPECTS OF MOS TRANSISTORS

Physical Structure of MOS Transistors in an n-well Technology

p+ p p- Metal Salicide n- n n+ Oxide Poly

070322-02

Polycide Gate Ox

n+

n-well

n+

p-well

n+

Substrate

n+

Substrate Salicide Substrate Salicide

Shallow Trench

Isolation

Well Salicide

p+ p+

Shallow Trench

Isolation

n+ n+

W

L

W

L

Width (W) of the MOSFET = Width of the source/drain diffusionLength (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusionsNote that the MOSFET is isolated from the well/substrate by reverse biasing theresulting pn junction



Enhancement MOSFETsThe channel of an enhancement MOSFET is formed when the proper potential is appliedto the gate of the MOSFET. This potential inverts the material immediately below thegate to the same type of impurity as the source and drain forming the channel.

060205-06

VDS<VDS(sat)VGS=0V

S G DVDS

VDS<VDS(sat)0V<VGS<VT

S G DVDS

VDS<VDS(sat)

S G DVDS

VGS>VT

Cutoff Weak Inversion Strong Inversion

VT = Gate-bulk work function ( MS) + voltage to change the surface potential (-2 F)+ voltage to offset the channel-bulk depletion charge (-Qb/Cox)+ voltage to compensate the undesired interface charge (-Qss/Cox)

VT = MS -2 F - Qb0

Cox -

QSS

Cox -

Qb - Qb0

Cox = VT0 + |-2 F + vSB| - |-2 F|

where VT0 = MS - 2 F -

Qb0

Cox -

QSS

Cox , =

2q siNA

Cox and Qb 2qNA si(|-2 F+vSB|)



Depletion Mode MOSFETThe channel is diffused into the substrate so that a channel exists between the source anddrain with no external gate potential.

Fig. 4.3-4n+ n+

p substrate (bulk)

Channel Length, L

n-channel

Polysilicon

Bulk Source Gate Drain

p+

Chann

el W

idth,

W

The threshold voltage for a depletion mode NMOS transistor will be negative (a negativegate potential is necessary to attract enough holes underneath the gate to cause thisregion to invert to p-type material).



Weak Inversion Operation

Weak inversion operation occurs when the appliedgate voltage is below VT and occurs when the surfaceof the substrate beneath the gate is weakly inverted.

Regions of operation according to the surfacepotential, S.

S < F : Substrate not inverted

F < S < 2 F : Channel is weakly inverted(diffusion current)

2 F < S : Strong inversion (drift current)

060205-07

VDS<VDS(sat)0V<VGS<VT

S G DVDS

Weak Inversion

DiffusionCurrent

log iD

10-6

10-120 VT

VGS

Drift CurrentDiffusion Current

Drift current versusdiffusion current in aMOSFET:



LAYOUT OF MOS TRANSISTORSLayout of a Single MOS transistor:

060223-01

STI

n-well

W

L

Drain

Gate Source

Well/Bulk

p-well

DrainWell/Bulk

W

L

Gate Source

Comments:• Make sure to contact the source and drain with multiple contacts to evenly distribute

the current flow under the gate.• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.



Geometric EffectsOrientation:Devices oriented in the same direction match more precisely than those oriented in otherdirections.

��

��

��

��

Good Matching041027-02

Poorer Matching



Diffusion and Etch Effects• Poly etch rate variation – use dummy elements to prevent etch rate differences.

��

��

��

041027-03

��Dummy

Gate

��Dummy

Gate

• Do not put contacts on top of the gate for matched transistors.• Be careful of diffusion interactions for diffusions near the channel of the MOSFET



Thermal and Stress Effects• Oxide gradients – use common centroid geometry layout• Stress gradients – use proper location and common centroid geometry layout• Thermal gradients – keep transistors well away from power devices and use common

centroid geometry layout with interdigitated transistorsExamples of Common Centroid Interdigitated transistor layout:

A B B A

Dum

my

Gat

e

Dum

my

Gat

e

DA SA/SB DB SA/SB DA

GA GAGB GBInterdigitated, common centroid layout

041027-04

Dum

my

Gat

e

Dum

my

Gat

e

BA

AB

SA/SBDA DB

GA GBGB GA

SB/SADB DACross-Coupled Transistors



MOS Transistor LayoutPhotolithographic invariance (PLI) are transistors that exhibit identical orientation. PLIcomes from optical interactions between the UV light and the masks.Examples of the layout of matched MOS transistors:1.) Examples of mirror symmetry and photolithographic invariance.

Mirror Symmetry��

��

Photolithographic Invariance��

��

Fig. 2.6-05



MOS Transistor Layout - Continued2.) Two transistors sharing a common source and laid out to achieve both

photolithographic invariance and common centroid.

��

��

��

��

��

��

��

��

Metal 2

Via 1

Metal 1

Fig. 2.6-06



MOS Transistor Layout - Continued3.) Compact layout of the previous example.

��

��

��

Fig. 2.6-07

Metal 2

Metal 2

Via 1

Metal 1



PARASITIC BIPOLAR TRANSISTORS IN CMOS TECHNOLOGYA Lateral Bipolar Transistorn-well CMOS technology:• It is desirable to have the lateral

collector current much larger than thevertical collector current.

• Lateral BJT generally has goodmatching.

• The lateral BJT can be used as aphotodetector with reasonably goodefficiency.

• Triple well technology allows thecurrent of the vertical collector toavoid the substrate.

060221-01

p+

n-well

n+

Substrate

E LCBVC

STI STI

LC

STI Lateral Collector

Emitter

Base

VerticalCollector

p+ p+



060221-02

p+

n-well

n+

Substrate

BVC

STI STI

LC

STI Lateral Collector Emitter

Base

VerticalCollector

p+ p+p+

E LC

Keeps carriers fromflowing at the surfaceand reduces 1/f noise

A Field-Aided Lateral BJT

Use minimum channel length toenhance beta:ßF 50 to 100 depending onthe process



HIGH VOLTAGE CMOS TRANSISTORSExtended Voltage MOSFETSThe electric field from the source to drain in the channel is shown below.

��Source n+

��Drain n+

��Channel

p - substrate

xp xdDistance, x

ElectricField

Emax

0

Draindepletion

region

Substrate depletion region

Sourcedepletion

region

Area = Vp Area = Vd

040920-01

Pinch-off region

The voltage drop from drain to source is,VDS = Vp + Vd = 0.5(Emaxxp + Emaxxd) = 0.5Emax(xp + xd)

Emax and xp are limited by hot carrier generation and channel length modulationrequirements whereas these limitations do not exist for xd.Therefore, to get extended voltage transistors, make xd larger.



High Voltage ArchitecturesThe objective is to create a lightly doped, extended drain region where the high voltageof the drain can drop down to a level that will not cause the gate oxide to breakdown.LOCOS Architecture:

DSM Architecture:



Lateral DMOS (LDMOS) Using LOCOS CMOS TechnologyThe LDMOS structure is designed to provide sufficient lateral dimension and to preventoxide breakdown by the higher drain voltages.One possible implementation using LOCOS technology:

n well

p substrate

p epi p epi

n+ n+

071025-01

xd xdp-bodyp-body

Drain DrainGate Source/Bulk Gate

n+ n+ p+

• Structure is symmetrical about the source/bulk contact• Channel is formed in the p region under the gates• The lightly doped n region between the drain side of the channel and the n+ drain

contact (xd) increases the depletion region width on the drain side of the channel/drainpn junction resulting in larger values of vDS.

• Drain voltage can be 20-30V



Lateral DMOS (LDMOS) Using DSM CMOS TechnologyCross-section of anNLDMOS using DSMtechnology:

Differences between an NLDMOS and NMOS:• Asymmetry• Non-uniform channel• Current flow (not all at the surface)• No self-alignment (larger drain-gate overlap

capacitance)• Note the extended drift region on the drain side of the

channel



SUMMARY• pn junction usage in CMOS include:

- Electrical isolation, pn diodes, ESD protection, depletion capacitors• Depletion region widths are inversely proportional to the doping• Depletion region widths are proportional to the reverse bias voltage• Ohmic metal-semiconductor junctions require a highly doped semiconductor• MOSFETs can be:

- Enhancement – the applied gate voltage forms the channel- Depletion – the channel is physically constructed in fabrication

• The threshold voltage of MOSFETs consists of the following components:- Gate bulk work function ( MS)- Voltage to change the surface potential (-2 F)- Voltage to offset the channel-bulk depletion charge (-Qb/Cox)- Voltage to compensate the undesired interface charge (-Qss/Cox)

• Weak inversion is MOSFET operation with the gate-source voltage less than thethreshold voltage

• Layout of the MOSFET is important to its performance and matching capabilities• Extended drain regions lead to higher voltage capability MOSFETs

Documents

LECTURE 050 - PN JUNCTIONS AND CMOS TRANSISTORSaicdesign.org/SCNOTES/2010notes/Lect2UP050_(100430).pdf · LECTURE 050 - PN JUNCTIONS AND CMOS TRANSISTORS LECTURE ORGANIZATION Outline