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8/26/2018
1
Lect 13
AdderCS221: Digital Design
Ref Chapter 10 of the Book: Introduction to Digital System, E M L T d M J H Wil I di 2013Ercegovac M, Lang T and Moreno J H, Wiley India, 2013
Dr. A. SahuDept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati
1
Outline• Combinational Block• Adder, Substractor, BCD Adder• Efficient : Adder Design
• RCA, CSkA, CSlA, CLARCA, CSkA, CSlA, CLA
• Binary Multiplier• Array, Sequential, Booth
• Floating Point
2
• One‐bit Half Adder:
O bi F ll Add
Adding Two One‐bit Operands
Sum = A ⊕ B Cout = A.BHA
A B
Cout
Sum
A B Sum Cout0 0 0 00 1 1 01 0 1 01 1 0 1
C A B S C
3
• One‐bit Full Adder:
Sum = A ⊕ B ⊕ CinCout = A.B + B.Cin
+ A.CinFAFAA B
CinCout
Sum
Cin A B Sum Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
NN‐‐Bit RippleBit Ripple‐‐Carry Adder: Series of FA CellsCarry Adder: Series of FA Cells• To add two n‐bit numbers
C0FA
A0 B0
FA
A1 B1
FA
A2 B2
FA
An-1Bn-1
Cn. . .
4
S0S1S2Sn-1
• Adder delay = Tc * n• Tc = (Cin to Cout delay) of a FA• Adder Area: N*AFA FA
A B
CinCout
Sum
4 bit Binary Adder
CiFA
A0
S
B0
FA
A1
S
B1
FA
A2
S
B2
FA
A3
S
B3
Co
5
S0S1S2S2
4 Bit Adder
B3 B2 B1 B0 A3 A2 A1 A0 Ci
S3 S2 S1 S0C0
4 bit Binary Adder: Serial
FA
Shift Register AShift Register A
Shift Register SShift Register S
FAShift Register BShift Register B
ControllerCLK
D FF
Shift Reg. PIPO Right Shift
Delay : O(N) : Tc * nArea:O(1) in term of Area of FA : 1*AFA
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Adder/Substractor• C= A‐B=A+(‐B)=A+ (Bb+1), Bb is complement of B• D is control bit: D=0/1 operation is add/sub
A
7
ALU
Operation
B
Result
Decimal Adder
• Decimal numbers are represented with BCD code.
• When two BCD digits A and B are addedif A B 10 lt i lid BCD di it– if A+B<10 result is a valid BCD digit
– if A+B>9 result will not be valid BCD digit. ˙It must be corrected by adding 6 to the result
• If A+B >9 add 6 to solve this issue
Decimal Adder
4 bit binary adderZ8 Z4 Z2 Z1
KCarry out
O t t
Carry in
C=K+Z8Z4+Z8Z2If (C ) add 6
4 bit binary adder
OutputCarry
Binary Multiplier: 2 Bits
A1 A0
B1 B0
X
B0 A1 B0A0
Partial Products
10
0 1 0 0
B1 A1 B1 A0
C3 C2 C1 C0 C0 =B0A0
C1 = B0A1 +B1A0
C2 = B1A1 +Carry of C1C3 = Carry of C2
Binary Multiplier: 2 Bits
11
B1 B0
x A1 A0
A0B1 A0B0
+ A1B1 A1B0
C3 C2 C1 C0
HAHA
Binary Multiplier: 4 BitsB3 A0 B2A0 B1 A0 B0A0
B3 A1 B2A1 B1 A1 B0A1
B3 A2 B2A2 B1 A2 B0A2
4 bit Adder
4 bit Adder
0
A0
A1
A2
12
B3 A3 B2A3 B1 A3 B0A3
4 bit Adder
4 bit Adder
C7 C6 C5 C4 C3 C2 C1 C0
A3
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Area & Delay (Critical Path): Multiplier
Delay α CP =2NArea : N2 FAFor NxN bit multiplication
Area & Delay (Critical Path): Multiplier
FA FA FA FA
FA FA FA FA
FA
FA FA FA FA
FA FA FA FA
FA FA FA FA
Delay α CP =2NArea : N2 FAFor NxN bit multiplication
Efficient Adder DesignAdder Design
15
Adder Universal Use• Adder : A = B + C• Substractor: A = B + (‐C), 2’s complement• Compare : C = A> B ? 1 : 0 , (A‐B > 0) ? 1 : 0
– Special case of compare with 0p p
• Multiply• Divide• Mod• Floating point: Add/sub/mul…
16
• One‐bit Full adderAdding Two One‐bit Operands
FAA B
CinCout
Cin A B Sum Cout0 0 0 0 00 0 1 1 00 1 0 1 0
17
Sum = A ⊕ B ⊕ CinCout = A.B + B.Cin
+ A.Cin
Sum0 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Addition of Two N‐Bit numbers
x + y + cin = 2n cout + sThe solution:
s = (x + y + c ) mod 2ns = (x + y + cin) mod 2cout = 1 if (x + y + cin) ≥ 2n else 0
18
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Example• 011110 + 101101 = 1 (x 2x 266 )+ 001011
• X=30, Y=45• 30 + 45 = 75= 26 x 1 + 11• Solution
– S= (30+45+0) % 26=11– Cout= 1 if (30+45+0 >= 26) else 0 = 1
Primitive module FAxi + yi + ci = 2 ci+1 + si
with solution• si = (xi + yi + ci) mod 2
Xi Yi
si (xi + yi + ci) mod 2• ci+1 =floor [ (xi + yi + ci)/2]
20
FA Ci
Ci+1 S
N‐Bit Ripple‐Carry Adder: Series of FA Cells• To add two n‐bit numbers
C0FA
A0 B0
FA
A1 B1
FA
A2 B2
FA
An-1Bn-1
Cn. . .
21
S0S1S2Sn-1
• Adder delay = Tc * n• Tc = (Cin to Cout delay) of a FA
FA
A B
CinCout
Sum
Adder Schemes• Step1: Obtain carries
– (Carry at i depends on j < i), Non‐trivial to do fast
• Step2: Compute sum bits (local function)
C0=Cin
X Y
22
Step1: Obtain Carries
Step2: Computer Sum
0 in
Cout=Cn
yixi
y1x1
y0x0
yn‐1xn‐1
sn‐1 si s1 s0
Mathematically: Ci & Si• Ci =FuncC ( xi‐1, ..,x0, yi‐1, ..,y0, cin)
S S ( )• Si =FuncS (xi, yi, ci) = ( xi + yi + ci) mod 2
23
Ripple Carry Adder Analysisi 9 8 7 6 5 4 3 2 1 0xi 1 0 1 0 1 1 1 1 0 0yi 0 0 0 1 0 1 0 0 1 0
P K P P P G P P P KC 0 0 1 1 1 1 0 0 0 0
Cin=0
24
Ci+1 0 0 1 1 1 1 0 0 0 0
Case Xi Yi Xi+Yi Ci+1 Comment
Kill (Ki=1) 0 0 0 0 Kill/Stop Cin/Cout=0
PropagatePi=1
0 1 1 Ci Propagate CinCout=Cin1 0 1 Ci
Generate 1 1 2 1 (Gi=1), Generate Cout, Cout=1
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Propagate, Generate & Kill• Case 1 (Kill): ki = xi’yi’ = (xi+yi)’• Case 2 (Propagate): pi = xi XOR yi• Case 3 (Generate): gi = xi + yiThen
ci+1 = gi + pici = xiyi + (xi XOR yi) ciAlternative (simpler) expression:
ci+1 = gi + aiciSince ai = ki’, we call it "alive" 25
Reducing Adder Delay• Ripple Carry Adder: N(tc)+max(tc,ts)• Reducing Carry Delay tc: Manchester Switch• Changing linear factor to smaller
– N/k or logN/ g– Carry Look Ahead, Carry Skip, Carry Select, Conditional Sum Adder
• Including a competition signal: addition always may not be the worst case.
• Changing number representation: Carry Saved Adder
26
Switched Carry Ripple (Manchester) Adder
• Idea: Fast circuit to propagating carry chain
xi+yi Gi Pi Ki Ci+10 0 0 1 0
27
0 0 0 1 0
1 0 1 0 Ci
2 1 0 0 1
Chain Control Switch Module
Carry ControlGKP
xi yi
g
28
1 0
gi kipi
CiCi+1
Manchester Adder (MRCA)
• Delay: tsw+(n‐1)*tp• Here tp < tc, so total delay is less
X0Y0X1Y1XiYiXn‐1Yn‐1
29
CC
S0
Cin
CC
S1
CC
Si
CC
Sn‐1
Carry Skip Adder• Smaller modification to Ripple Carry Adder• Reduce worst case delay by reducing the number of FA cell through carry has to Propagate
• Divide n bits in to (n/m) groups of m bits( / ) g p• If sum of group is 2m‐1 then carry is propagated• Carry is propagated when it propagated by all the bits of the groups
Pj= pj0 pj1pj2 ..pjm‐‐1
• Cin,j+1 = Cout, j . P’j + Cin,j+Pj30
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6
Carry Skip Example
101110
010110
100101100011100110101100
P=0 P=1 P=1 P=0 P=1 P=0
31
0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0
Ci
CjCj+1
P
CSK Module• If Pj=1: simply skip the group j, Cin,j+1=Cin,j
M‐bit RCAGroup J
CinCout
MU0Cin,j+1
Pjmm
yjxj
32
pX1
CSK Module
mmModule n‐1
m
msj
CSK Module
mmModule i
m
CSK Module
mmModule 1
m
CSK Module
mmModule 0
m
Carry Skip Path
33
skipped
Skip is Data Dependent
Carry Select Adder
FA FA FA FA
FA FA FA FA
For All Groups: For Both Carry =0 and carry =1 Sum & Carry is already calculated
Simply select Carry & Sum based on carry
34
Sum based on carry input
Skip is Data Independent
Delay Analysis of Adder• Ripple Carry Adder (RCA) = N * Tc• Machester RCA = N*Tm• Carry Skip Adder = Depend on Data
– Let probability of skip is p– If skip delay for Group is Ts– Else Delay of Group m*TcTotal Delay = p (N/m) Ts + (p‐1) *(N/m)* m * Tc
• Carry Select Adder = Independent of DataDelay of select = TsT = ( N/m ‐ 1) Ts + m Tc
Delay of Adder α N : Linear Delay • Ripple Carry Adder (RCA) = N * Tc = α N • Machester RCA = N * Tm = α N • Carry Skip Adder
Total Delay = p (N/m) Ts + (p‐1) *(N/m)* m * TcT= N * ( p/m*Ts+(p‐1)Tc) = α N
• Carry Select Adder = Independent of DataDelay of select = TsT = ( N/m ‐ 1) Ts + m TcT = N*Ts/m + ( mTc‐Ts) = α N +c
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Delay is linear• Always carry moves from Right to Left • Some time Skip/Always Skip It have to select • Linear Arrangement == > O(N) delay• How to reduced to Logarithmic delay ?
– Tree Fashion/ Hierarchical FashionTree Fashion/ Hierarchical Fashion – Design a block which can be used in Tree Fashioned Adder === > Solution is CLA Block
Carry Look Ahead Adder (CLA)• Basic Idea: Compute Several Carries Simultaneously and use it
• Use as Ripple Carry or MultiLevel CLAA3 B3 A2 B2 A1 B1 A0 B0
38
FA FA FA FA
P3 G3 C3 P2 G2 C2 P1 G1 C1 P0 G04 Bit Carry Look Ahead Generator
S3 S2 S1 S0
C4
CLG
iii
0121-ii1iii
iii1iiii
PCSCPP ... PP+ ... GPG=
BAG whereCPGC
⊕=⋅⋅⋅+⋅+
⋅=⋅+=
−
−
39
4)inputs of (#for Availableiii
≤
CLG (Carry Lookahead Generator)C0
P1G1P2
G2
C1
C2
6.40
P3
G3
P4
G4
C3
C4
RCA with CLA units• As Carry are generated with CLG it takes less time • Time complexity : O(N) ===> useless approach
Module n‐1mm
Module imm
Module 1mm
Module 0
41
CLAModule
mm
m
CLAModule
mm
m
CLAModule
mm
m
CLAModule
mm
m
Not a good approach
2 Levels of look ahead
a4..7 s
c4
a0..3b0..3
s0..3
c0 P0c0
G0
CP4G
no rippling f b4..7
s4..7
a8..11b8..11
s8..11
c8
a12..15b12..15
s12..15c16
c12
LA
unit
G4
P8G8
P12G12
of carry
Can be extended to log4N levels
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Group propagate & generate
c1 = p0 c0 + g0c2 = p1 c1 + g1 = p1p0c0+p1g0+g1c3 = p2 c2 + g2 = p2p1p0c0+p2p1g0+p2g1+g2c = p c + g =c4 = p3 c3 + g3 =
p3p2p1p0c0+p3p2p1g0+p3p2g1+p3g2+g3P0 = p3p2p1p0G0 = p3p2p1g0+p3p2g1+p3g2+g3c4 = P0 c0 + G0
Group propagate & generate
Pi = pi+3 pi+2 pi+1 piGi = pi+3 pi+2 pi+1 gi + pi+3 pi+2 gi+1 + pi+3 gi+2 + gi+3
c4 = P0 c0 + G0
c8 = P4 P0 c0 + P4 G0 + G4
c12 = P8 P4 P0 c0 + P8 P4 G0 + P8 G4 + G8
c16 = P12 P8 P4 P0 c0 + P12 P8 P4 G0 + P12 P8 G4 + P12 G8 + G12
Summery: Two operand Additions• Speeding up addition
–Ripple carry adder (carry propagate): O(n)–Carry look ahead: O(log n)
• What about Multi‐Operand Adder–A=N0+N1+N2+…..+Nn
• Where we require: possibly in multiply or advance computing places
45
Adding multiple operandsb0a0
e0
b1a1
e1
b2a2
e2
b3a3
e3
+ + + +E FBA
Traditional adderTraditional Adder
s5 s0
f0
s1
f1
s2
f2
s3
f3
s4
++++
+ + + ++S
Traditional adder
Traditional adder
Traditional Adder
Traditional Adder
Carry save addition
f0e0b0f1e1b1f2e2b2f3e3b3
0a1a2a3
Carry save adder
E FBA
++ ++ ++ ++ Carry Save Adder
s4 s3 s2 s1 s0
a0a1a2a3
s5
c'3 s'3s'4 c'2 s'2 c'1 s'1 c'0 s'0
Carrysave adder
Traditional adder
S
C' S'++ ++ ++ ++
++ ++ ++ ++
Carry Save Adder
Traditional Adder