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Lecture 360 Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-1

CMOS Analog Circuit Design P.E. Allen - 2010

LECTURE 360 CHARACTERIZATION OF ADCS AND SAMPL

AND HOLD CIRCUITS

LECTURE ORGANIZATION

Outline

Introduction to ADCs

Static characterization of ADCs

Dynamic characteristics of ADCs

Sample and hold circuits

Design of a sample and hold

Summary

CMOS Analog Circuit Design,2nd Edition Reference

Pages 652-665



INTRODUCTIONGeneral Block Diagram of an Analog-Digital Converter

Digital

Processor

Prefilter Sample/Hold Quantizer Encoder

x(t) y(kTN)

Fig.10.5-1

Prefilter - Avoids the aliasing of high frequency signals back into the baseband of the

ADC Sample-and-hold - Maintains the input analog signal constant during conversion

Quantizer - Finds the subrange that corresponds to the sampled analog input

Encoder - Encoding of the digital bits corresponding to the subrange

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Nyquist Frequency Analog-Digital Converters

The sampled nature of the ADC places a practical limit on the bandwidth of the inputsignal. If the sampling frequency isfS, andfB is the bandwidth of the input signal, then

fB < 0.5fSwhich is simply theNyquistrelationship which states thatto avoid aliasing, the

sampling frequency must begreater than twice thehighest signal frequency.

fB-fB 0

fB-fB 0 fSfS-fB fS+fB 2fS2fS-fB 2fS+fB

-fB 0 fS 2fS

AntialiasingFilter

fS2

fB-fB 0

fS2

fS2

fS

fS

Continuous time frequency response of the analog input signal.

Sampled data equivalent frequency response wherefB < 0.5fS.

Case wherefB> 0.5fScausing aliasing.

Use of an antialiasing filter to avoid aliasing.

Fig. 10.5-



Classification of Analog-Digital ConvertersAnalog-digital converters can be classified by the relationship offB and 0.5fSand by their

conversion rate.

Nyquist ADCs - ADCs that havefB as close to 0.5fSas possible.

Oversampling ADCs - ADCs that havefB much less than 0.5fS.

Classification of Analog-to-Digital Converter Architectures

ConversionRate

Nyquist ADCs Oversampled ADCs

Slow Integrating (Serial) Very high resolution

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STATIC CHARACTERIZATION OF ANALOG-TO-DIGITAL CONVERTERS

Digital Output Codes

Digital Output Codes used for ADCs

Decimal Binary Thermometer Gray TwosComplement

0 000 0000000 000 0001 001 0000001 001 1112 010 0000011 011 1103 011 0000111 010 1014 100 0001111 110 1005 101 0011111 111 0116 110 0111111 101 0107 111 1111111 100 001



Input-Output Characteristics

Ideal input-output characteristics of a 3-bit ADC

Analog Input Value Normalized to VREF

000

001

010

011

100

101

110

111

DigitalOutputCode

Ideal 3-bit

Characteristic

Figure 10.5-3 Ideal input-output characteristics of a 3-bit ADC.

Infinite Resolution

Characteristic

1 LSB

18

28

38

48

58

68

08

78

1 LSB

vinVREF

0.5

1.0

0.0

-0.5Quantization

NoiseLSBs

88

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Definitions

The dynamic range, signal-to-noise ratio (SNR), and the effective number of bits(ENOB) of the ADC are the same as for the DAC

Resolution of the ADC is the smallest analog change that distinguishable by an ADC.

Quantization Noise is the 0.5LSB uncertainty between the infinite resolutioncharacteristic and the actual characteristic.

Offset Error is the difference between the ideal finite resolution characteristic andactual finite resolution characteristic

Gain Error is thedifference betweenthe ideal finiteresolution charact-eristic and actualfinite resolutioncharacteristicmeasured at full-scale input. Thisdifference is

proportionalto theanalog inputvoltage.

000

001

010

011

100

101

110

111

vinVREF

DigitalOutputCode

Offset = 1.5LSBs

000

001

010

011

100

101

110

111

08

18

28

38

48

58

68

78

88

vinVREF

DigitalOutputCode

Gain Error = 1.5LSBs

(a.) (b.)Figure 10.5-4 - (a.) Example of offset error for a 3-bit ADC. (b.) Example of gain

error for a 3-bit ADC.

Ideal

Characteristic

Ideal

Characteristic

08

18

28

38

48

58

68

78

88

Actual

Characteristic



Integral and Differential NonlinearityThe integral and differential nonlinearity of the ADC are referenced to the vertical(digital) axis of the transfer characteristic.

Integral Nonlinearity (INL) is the maximum difference between the actual finiteresolution characteristic and the ideal finite resolution characteristic measured verticall(% orLSB)

Differential Nonlinearity (DNL) is a measure of the separation between adjacent levelsmeasured at each vertical step (% orLSB).

DNL = (Dcx - 1)LSBs

whereDcx is the size of the actual vertical step inLSBs.

Note thatINL andDNL of an analog-digital converter will be in terms of integers incontrast to theINL andDNL of the digital-analog converter. As the resolution of theADC increases, this restriction becomes insignificant.

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Example ofINL and DNL

000

001

010

011

100

101

110

111

08

18

28

38

48

58

68

78

88

vinVREF

DigitalOutputCode

Example ofINL andDNL for a 3-bit ADC.) Fig.10.5-5

Ideal

Characteristic

ActualCharacteristic

INL =

+1LSB

INL =

-1LSB

DNL =

+1LSB

DNL =

0LSB

Note that the DNL and INL errors can be specified over some range of the analog input.



MonotonicityA monotonic ADC has all vertical jumps positive. Note that monotonicity can only bedetected byDNL.

Example of a nonmonotonic ADC:

000

001

010

011

100

101

110

111

08

18

28

38

48

58

68

78

88

vinVREF

DigitalO

utputCode

DNL =

-2LSB

Actual

Characteristic

Ideal

Characteristic

Fig. 10.5-6L

If a vertical jump is 2LSB or greater, missing output codes may result.

If a vertical jump is -1LSB or less, the ADC is not monotonic.

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Example 360-1 - INLandDNLof a 3-bit ADC

Find theINL andDNL for the 3-bit ADC shown on the previous slide.

Solution

With respect to the digital axis:

1.) The largest value ofINL for this 3-bit ADC occurs between 3/16 to 5/16 or 7/16 t9/16 and is 1LSB.

2.) The smallest value ofINL occursbetween 11/16 to 12/16 and is-2LSB.

3.) The largest value ofDNL occurs at3/16 or 6/8 and is +1LSB.

4.) The smallest value ofDNL occursat 9/16 and is -2LSB which iswhere the converter becomesnonmonotonic.

000

001

010

011

100

101

110

111

08

18

28

38

48

58

68

78

88

vinVREF

DigitalOutputCode

DNL =

-2LSB

Actual

Characteristic

Ideal

Characteristic

Fig. 10.5-6DL

INL =

+1LSB

INL =

-2LSB

DNL =

+1LSB



DYNAMIC CHARACTERISTICS OF ADCsWhat are the Important Dynamic Characteristics for ADCs?

The dynamic characteristics of ADCs are influenced by:

Comparators

- Linear response

- Slew response

Sample-hold circuits

Circuit parasitics

Logic propagation delay

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Comparator

The comparator is the quantizing unit of ADCs.

Open-loop model:

+

-

Av(s)ViVi

VOS

Ri

RoVo

V1

V2Comparator

Fig.10.5-7

Nonideal aspects:

Input offset voltage, VOS(a static characteristic)

Propagation time delay

- Bandwidth (linear)

Av(s) =Av(0)

sc+1

=Av(0)

sc+1- Slew rate (nonlinear)

T =CV

I (Iconstant) =V

SlewRate



SAMPLE AND HOLD CIRCUITSRequirements of a Sample and Hold Circuit

The objective of the sample and hold circuit is to sample the unknown analog signal andhold that sample while the ADC decodes the digital equivalent output.

The sample and hold circuit must:

1.) Have the accuracy required for the ADC resolution, i.e. accuracy =100%

2N

2.) The sample and hold circuit must be fast enough to work in a two-phase clock. For aADC with a 100 Megasample/second sample rate, this means that the sample and holdmust perform its function within 5 nanoseconds.

3.) Precisely sample the analog signal at the same time for each clock. An advantage ofthe sample and hold circuit is that it removes the precise timing requirements from theADC itself.

4.) The power dissipation of the sample and hold circuit must be small. Unfortunately,the above requirements for accuracy and speed will mean that the power must beincreased as the bits are increased and/or the clock period reduced.

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Sample-and-Hold Circuit

Waveforms of a sample-and-holdcircuit:

Definitions:

Acquisition time (ta) = time required

to acquire the analog voltage

Settling time (ts) = time required tosettle to the final held voltage to withinan accuracy tolerance

Tsample = ta + ts Maximum sample rate =fsample(max) =1

Tsample

Other consideratons:

Aperture time= the time required for the sampling switch to open after the S/Hcommand is initiated

Aperture jitter = variation in the aperture time due to clock variations and noise

Types of S/H circuits:

No feedback - faster, less accurate

Feedback - slower, more accurate

ta ts

Hold Sample Hold

S/H Command

vin*(t)

vin*(t)

vin(t) vin(t)

Time

Amplitude

Fig.10.5-9

Output of S/H

valid for ADC

conversion



Open-Loop, Buffered S/H CircuitCircuit:

+

-

vin(t)vout(t)

CHSwitchClosed

(sample)

SwitchOpen(hold)

SwitchClosed

(sample)

vin(t)

vout(t)vin(t), vout(t)

vin(t), vout(t)

Time

Amplitude

Fig.10.5-10

Attributes:

Fast, open-loop

Requires current from the input to charge CH

DC voltage offset of the op amp and the charge feedthrough of the switch will create dcerrors

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Settling Time

Assume the op amp has a dominant pole at -a and a second pole at -GB.

The unity-gain response can be approximated as, A(s)GB2

s2+GBs+GB2

The resulting step response is, vout(t) = 1 -

43e

-0.5GBt sin

34GBt+

Defining the error as the difference between the final normalized value and vout

(t), gives,

Error(t) = = 1 - vout(t) =43e

-0.5GBt

In most ADCs, the error is equal to 0.5LSB. Since the voltage is normalized,

1

2N+1 =43e

-0.5GBts e-0.5GBts = 43

2N

Solving for the time, ts, required to settle with 0.5LSB from the above equation gives

ts =2

GBln

4

32N =

1GB [1.3863N+ 1.6740]

Thus as the resolution of the ADC increases, the settling time for any unity-gain buffer

amplifiers will increase. For example, if we are using the open-loop, buffered S/H circuitin a 10 bit ADC, the amount of time required for the unity-gain buffer with a GB of 1MHzto settle to within 10 bit accuracy is 2.473s.



Open-Loop, Switched-Capacitor S/H Circuit

Circuit:

+

-

1d

1

2

vin(t) vout(t)C

+

-

1d

1

2

vin(t) vout(t)

C

+

-

C

2 1

1d

+

-

+

-

Fig.10.5-11

Switched capacitor S/H circuit. Differential switched-capacitor S/H

Delayed clock used to remove input dependent feedthrough.

Differential version has lower PSRR, cancellation of even harmonics, and reduction ofcharge injection and clock feedthrough

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Open-Loop, Diode Bridge S/H Circuit

Diode bridge S/H circuit:VDD

060927-01

vIN(t) vOUT(t)

CH

IBClock

IBClock

vIN(t) vOUT(t)

CH

rd rd

rd rd

RON= rd

Sample phase - diodes

forward biased.

vIN(t) vOUT(t)

CH

ROFF=

Hold phase - diodes

reversed biased.

D1 D2

D3 D4

Blowthru Capacitor

MOS diode bridge S/H circuit:VDD

060927-02

vIN(t) vOUT(t)

CH

IBClock

IBClock

vIN(t) vOUT(t)

CH

gm

RON= 1/gm

Sample phase - MOS

diodes forward biased.

vIN(t) vOUT(t)

CH

ROFF=

Hold phase - MOS

diodes reversed biased.

1gm1

gm1 gm1

M1 M2

M3 M4

Blowthru Capacitor



Practical Implementation of the Diode Bridge S/H Circuit

060927-03

IB IB

VDD

VSS

CH

vout(t)vin(t)

D1 D2

D3 D4 +

-

2IB

D5

D6SampleHold

M1 M2

Practical implementation of the diode bridge

sample and hold (sample mode).

IB IB

VDD

VSS

CH

vout(t)vin(t)

D1 D2

D3 D4 +

-

2IB

D5

D6SampleHold

M1 M2

2IB

IB

IB

Hold mode.

IB2

IB2

During the hold mode, the diodes D5 and D6 become forward biased and clamp the uppeand lower nodes of the sampling bridge to the sampled voltage.

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Closed-Loop S/H Circuit

Circuit:

+

-

+

-

1

1

2

CH

vout(t)

vin(t)

+

- +

-

1

2

CH

vout(t)vin(t)

Fig.10.5-13

Closed-loop S/H circuit. 1 is the sample

phase and 2 is the hold phase.

An improved version.

Attributes:

Accurate

First circuit has signal-dependent feedthrough

Slower because of the op amp feedback loop



Closed-Loop, Switched Capacitor S/H CircuitsCircuit:

+

-vout(t)vin(t)

1d1

2

CH+

-

2

1 2d1d

2 1d

2d

1d

2d

1d 2

1

21

CH

CH

CH

CH

CH

CH

vout(t)vin(t)

+

-

+

-

1 2d

-

+

070616-02

Switched capacitor S/H circuit

which autozeroes the op amp

input offset voltage.A differential version that avoids

large changes at the op amp output

New charge (2)

Old charge (2)

New charge (2)

Old charge (2)

Attributes:

Accurate

Signal-dependent feedthrough eliminated by a delayed clock

Differential circuit keeps the output of the op amps constant during the1 phase

avoiding slew rate limits

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Current-Mode S/H Circuit

Circuit:

VDD

IB

CH

11

2

iin iout

Fig.10.5-15

Attributes:

Fast

Requires current in and out

Good for low voltage implementations



Aperature Jitter in S/H Circuits

Illustration:

If we assume that vin(t) =Vpsint, then themaximum slope is equal toVp.

Therefore, the value ofVis given as

V=

dvin

dt t= Vpt.

The rms value of this noise is given as

V(rms) =

dvin

dt t=Vpt 2 .

The aperature jitter can lead to a limitation in the desired dynamic range of an ADC. Forexample, if the aperature jitter of the clock is 100ps, and the input signal is a full scalepeak-to-peak sinusoid at 1MHz, the rms value of noise due to this aperature jitter is111V(rms) if the value ofVREF= 1V.

Analog-Digital

Converter

Clock

Analog

InputDigital

Output V

vin

Aperature Jitter = t

Figure10.5-14 - Illustration of aperature jitter in an ADC.

vin(to)

to

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DESIGN OF A SAMPLE AND HOLD AMPLIFIER

Specifications

Accuracy = 10 bits

Clock frequency is 10 MHz

Power dissipation 1mW

Signal level is from 0 to 1V

Slew rate 100V/s with CL

= 1pF

Use 0.25m CMOS

Technology Parameters (Cox = 60.6x10-4 F/m2):

Typical Parameter ValueParameterSymbol

Parameter DescriptionN-Channel P-Channel

Units

VT0Threshold Voltage(VBS = 0)

0.5 0.15 -0.5 0.15 V

K' Transconductance Para-meter (insaturation)

120.0 10% 25.0 10% A/V2

Bulk thresholdparameter

0.4 0.6 (V)1/2

Channel lengthmodulation parameter

0.32 (L=Lmin)

0.06 (L 2Lmin

)

0.56 (L=Lmin)

0.08 (L 2Lmin

)(V)-1

2|F|Surface potential at strong inversion 0.7 0.8 V



Op Amp DesignGain:

Gain error =1

1+LoopGain 0.5 LSB =1

211

Therefore, the op amp gain 211 = 2048 V/V

Choose the op amp gain as 5000 V/V

Gainbandwidth:

For a dominant pole op amp with unity-gain feedback, the relationship between thegain-bandwidth (GB), accuracy (N) and speed (ts) is

ts =

N+1

GB ln(2) = 0.693

N+1

GB Therefore, ifts 0.5 Tclock= 50 ns (choose ts = 10 ns). ForN= 10, the gain-bandwidth

is

GB = 0.762x109 = 120 MHz

Dominant pole is 24 kHz and with an output capacitance of 1pF this means the outputresistance of the op amp must be 6.6 M.

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Op Amp Design Continued

The previous specifications suggest aself-compensated op amp. The gain andoutput resistance should be easy to achievewith a cascaded output. A folded-cascodeop amp is proposed for the design. Inorder to have the 0-1V signal range, ap-

channel, differential input is selected. Thiswill give the input 0-1V range. The outputwill effectively be 0-1V with the unity gainfeedback around the op amp.

Bias Currents:

The 100V/s slew rate requiresI3 = 100A. SettingI4 = I5 = 125A gives a power

dissipation of 0.875mW with VDD = 2.5V.

061021-01

VNB1

M4 M5

I6

VPB2

I4 I5

VDD= 2.5V

I7M6 M7

VNB2

M8 M9

M10 M11

+

vIN vOUT

VPB1

I1 I2

M1 M2

M3

I3

CL



Op Amp Design ContinuedTransistor sizes:

Design M4-M7 to give a saturation voltage of 0.1V with 125A.

W4L4

=W5L5

=W6L6

=W7L7

=2ID

Kn'VDS(sat)2 =

21251200.01 200

Since the upper swing is not as important, choose a saturation voltage of 0.25 for M8 M11.

W8L8

=W9L9

=W10L10

=W11L11

=2ID

Kp'VDS(sat)2 =

2125250.0625 = 160

To get the GB of 120 MHz, this implies the gm of M1 and M2 isgm = GBCL = (120x10

62)(10-12) = 762 S

W1L1

=W2L2

=gm

2

2IDKp'=

76276222550 = 232

Let the upper input common mode voltage be 1.5V which gives the W/L of M3 as,

1V = VSG1 + VSD3 = 0.631 + VSD3 VSD3 = 0.369V W3L3 60

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Op Amp Design Continued

We now need to check the output resistance and the gain to make sure the specificationsare satisfied. Let us choose twice minimum channel length to keep the capacitiveparasitics minimized and not have the output resistance too small. Therefore at quiescentconditions,

rds5 = 133k, rds7 = 222k, gm7 = 1.935mS and rds2 = 250k

Routdown (rds5||rds2)gm7rds7 = 37.29M

rds9 =rds11 = 167k, and gm11 = 1.697mS

Routuprds11gm9rds9 = 47.33M

Rout 20.86M

The low frequency gain is,

Avgm1Rout= 762S20.86M = 15,886 V/V

The frequency response will be as shown:

061023-02

log10f

15,886

Gain

5,000

24kHz 120MHz

7.55kHz1



Op Amp Bias VoltagesWe also need to design the bias voltages VNB1, VNB2, VPB1 and VPB2. This can be done

using the following circuit:

Note, the W/L of M3, M4 and M7 will be 6 so thata current of 10A gives 100A in M3 of the opamp. Also, W/L of M1 and M5 will be 16 so acurrent of 10A gives 125A in M4 and M5 of theop amp.

If M2 is 4 times larger than M1, which gives a W/Lof 64 for M2. Under these conditions,

I2 =I1 =

1

21R2 R =

106

21201610 = 5.1k

The extra 40A brings the power dissipation to

0.975mW which is still in specification.

The W/L of M6 and M8 are designed as follows:

VGS8 = VT+ 2VON VGS8 - VT= 0.2V = 210120(W8/L8) W8L8

= 4.167

VSG6 = |VT| + 2VONVSG6 - |VT| = 0.5V = 21025(W6/L6) W6L6

= 3.20

061021-02

VDD

VPB1

VPB2

VNB2

VNB1

M1 M2

M3 M4

M5

M6

M7

M8

R

10A 10A

10A

10A

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Switch and Hold Capacitor Design

Switch:

Since the signal amplitude is from 0 to 1V, a single NMOS switch should besatisfactory. The resistance of a minimum size NMOS switch is,

RON(worst case) 1Kn'(W/L)(VGS-VT) = 10

6

120(1)(1.5-0.5) = 8.33kFor a CH= 1pf, the time constant is 8 ns. This is too close to the 50 ns so let us increasethe switch size to 0.5m/0.25m which gives a time constant of 4ns.

Therefore, the W/L ratio of the NMOS switch is 0.5m/0.25m and the hold capacitor is1pf.

Check the error due to channel injection and clock feedthrough-

If we assume the clock that rises and falls in 1ns, then a 0.5m/0.25m switch works inthe fast transition region. The channel/clock error can be calculated as:

Verror= -

WCGDO+Cchannel

2CL

VHT-V

3HT

6UCL-

WCGDOCL

(VS+2VT -VL)



Switch and Hold Capacitor Design ContinuedAssuming CGDO is 200x10-12 F/m we can calculate VHTas 0.8131V. Thus,

Verror =

-

100x10-18+0.5(7.57x10-16)

1x10-12

0.8131-0.105x10-3

15x10-3-

100x10-18

1x10-12(1+1-0) = -0.586mV

For a 1volt signal with 10 bit accuracy, the error must be less than 1LSB which is0.967mV. The channel/clock error is close to this value and one may have to considerusing a CMOS switch or a dummy switch to reduce the error.

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Design Summary

At this point, the analog designer understands the weaknesses and strengths of thedesign. The next steps will not be done but are listed below:

1.) Simulation to confirm and explore the hand-calculated performance

2.) Layout of the op amp, hold capacitor and switch.

3.) Verification of the layout

4.) Extraction of the parasitics from the layout5.) Resimulation of the design.

6.) Check for sensitivity to ESD and latchup.

7.) Select package and include package parasitics in simulation.


SUMMARY

An ADC is by nature a sampled data circuit (cannot continuously convert analog intodigital)

Two basic types of ADCs are:

- Nyquist analog bandwidth is as close to the Nyquist frequency as possible

- Oversampled analog bandwidth is much smaller than the Nyquist frequency

The active components in an ADC are the comparator and the sample and hold circuit

A sample and hold circuit must have at least the accuracy of 100%/2N

Sample and hold circuits are divided into two types:

- Open loop which are fast but not as accurate

- Close loop which are slower but more accurate

An example of designing a sample and hold amplifier was given to illustrate theelectrical design process for CMOS analog circuits

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