Lect 7 : IIT Computer Architecture

7/29/2019 Lect 7 : IIT Computer Architecture

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CS222:

(b)Architecture

Space

RISC/CISC

Dr.A.Sahu

De t of Com . Sc. & En .

IndianInstituteofTechnologyGuwahati

1


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ActivationRecordinRecursion:

MergeSort

Activation

Record

Features

of

MIPS

ISA Otherarchitecturalvariations

Examples


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localdata

$sp

saveds re isters

(ifany)

returnaddr

arguments$fp


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constm=20;

int N,i;int X[m],Y[m];

cou ;

cout X[i];

sort(X,Y,N);

cout


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Recursivemergesortprocedure

voidsort(int A[],int B[],int n){

, ,

if(n

==

1)

B[0]

=A[0];

e se

n1=n/2;

n2

=n

n1;

sort(A,A1,n1);

+

merge(A1,A2,B,n1,n2);

}


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voidmerge(int P[],int Q[],int R[],int p,int q){

int i,

j,

;

i =j=k=0;

while(i


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$sp ij c

als

voi merge int P ,

int Q[],int R[],

returnaddr

P

k lo

s

n p, n q

{

R

Q

meterint i,j,k;

..

q par}


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$sp ij

returna r

qp

returnaddr

P

k

Pa0 P

R

QR

a

a2 R

q ij

t0t1

ij


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spA1

voidsort(intA[],

intB[

],

int

n)

A2

n1lo

cal

intA1[m],A2[m];

intn1,

n2;

returnaddr

n2

ers

}

n

B

rame

p


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..

while(i


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Callingmerge

addi $a0,$sp,0returnaddr

merge(A1,A2,B,n1,n2);

a a , sp,

lw $a2,176($sp)qp

w , sp

sw $t8,

8($sp)A2 Pa0w , sp

sw $t8, 4($sp)n2

n1 R

a

a2

a sp,

sp,

jal mergereturn

addr

B

Ai

jt0t1

.

merge:sw $ra,

0($sp)

n


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returnaddr

w ra,0 sp

addi $sp,$sp,12q

p

jr $ra

A2 Pa0

n2

n1 R

a

a2

returnaddr

B

Ai

jt0t1

n


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sort(A,A1,n1);A

sort:sw $ra,168($sp)

.n

B

w t , sp

sw $t8, 12($sp)A2 , ,

sw $t8, 8($sp)

lw $t8 160 $sn2

n1

sw $t8, 4($sp)

addi $sp,$sp, 184

returnaddr

B

A

jal sortn


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A

w ra,168 sp

addi$sp,$sp,184n

B

jr$ra

A2

n2

n1

returnaddr

B

A

n


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sort Writea ointerversion Candassembl

Includecodetotrackthemaxstacksize

Writemorespaceefficientprogram(Cand

assembl stillrecursive


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RISC

and

CISC

Examples

16


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Setofbasic/primitiveoperations

Storagestructure registers/memory

Howinstructionsareencoded


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Logical

Re ationa

Branch/jump

Datamovement


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Memory

0

0

4Registers

1

31

2304


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ImmediateP r

Register

Operandsources

PCrelative

ResultDestinations

(pseudo)Direct

eg s er n rec


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Immediateaddressing

Registeraddressing

op rs rt rd func0

1

Registers


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Memory

op rs rt constant

0

4

register + data

op rs rt constant

PCrelativeaddressing

PC + instruction


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Memory

op constant

0

4

PC + instruction

op rs rt

Registerindirectaddressing

rd func

Register instruction


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addi,lui,

beq,

bne,

lw,

sw I

format

j,jal J format

op 26bitnumber

add,jr R format

op

rs rt rd

shamt funct


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Only3formats

FairnumberofGPregisters

ormemoryaccessorcontroltransfer

Limitedaddressing

modes

,


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Providemorepowerfuloperations

e.g.J++

and

branch

to

Lif

J>N,

where

Jis

in

Goal

is

to

reduce

number

of

instructions

executed

Dangeris

aslower

cycle

time

and or

a

hi her CPI


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RM one

operand

in

register

and

one

inmemory

R+M CombinesRR,RMandMM


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2address

machine r1

=r1

+r2

1addressmachine Acc=Acc+x

0addressmachine addvalueson

topof

stack


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Accumulatorbasedmachine

Afewspecialpurposeregisters

Severalgeneralpurposeregisters

windows


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Indirect

Basevs.Index

Pre(post)increment/decrement

Stack


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Reduced vs.Com lex InstructionSet

Computer

Uniformityofinstructions

modes

Registerbasedarchitecturewith3address

instructions


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1970sJohnCocke atIBM

Majorityof

combinations

of

orthogonal

notused

ymos programsgenera e ycomp ers

Difficultinmanycasestowritea

compiler

by

conventional

CPUs. 32


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Virtuallyallnewinstructionsetssince1982have

beenRISC

SUNsSPARC(Scalable ProcessorARChitecture)

HPsPARISC

ARM(Advance

RISC

Machine)

MotorolasPowerPC(Performance Optimization

With EnhancedRISCPerformanceComputing,) DECs

Alpha

MIPS

CDC6600(1960s)

Documents

Lect 7 : IIT Computer Architecture