lec4.4 Power Descipation

8/7/2019 lec4.4 Power Descipation

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Lec4.4P O W E R D E S I P A T I O N

Engr. Anees ul Husnain ( [email protected] )

Department of Computer Systems Engineering,College of Engineering & Technology, IUB


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Power and Energy

Power is drawn from a voltage source attached to the VDDpin(s) of a chip.

Instantaneous Power:

Energy:

Average Power:

( ) ( )DD DDP t i t V !

0 0

( ) ( )

T T

DD DDE P t dt i t V dt ! !

avg

0

1( )

T

DD DD

EP i t dt

T T! !


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Power Dissipation

Static Power Dissipation Sub-thresh hold conduction Tunneling Current Leakage through diode

Dynamic Power Dissipation Charging & Discharging of load Capacitances Short circuit currents while both N-MOS & P-MOS are ON together.

P total = P static + P dynamic


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Dynamic power

Dynamic power is required to charge and discharge loadcapacitances when transistors switch.

One cycle involves a rising and falling output.

On rising output, charge Q = CVDD is required

On falling output, charge is dumped to GND

This repeats Tfsw times over an interval of T

Cfsw

iDD(t)

VDD


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Dynamic power dissipation

Vin Vout

CL

Vdd

Energy delivered by the supply during input 1 p 0transition:

Energy stored at the capacitor at the end of 1 p 0 transition:

dissipated in NMOS duringdischarge(input: 0p 1)

load capacitance (gate +diffusion + interconnects)


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Capacitive dynamic power

If the gate is switched on and offf0p1 (switching factor) times per second,the power consumption is given by

For entire circuit

where iis activity factor [0..0.5] in comparison to the clock frequency

(which has switching factor of 1)

2

dynamic DDP CV f E!


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Short circuit current When transistors switch, both nMOS and pMOS networks may be momentarily

ON at once

Leads to a blip of short circuit current.

< 10% of dynamic power if rise/fall times are comparable for input and output


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Techniques for low-power design

Reduce dynamic power

E: clock gating, sleep mode (floating point, caches,etc)

Fast transitions.. (may become noisy.. Tradeoff)

C: small transistors (esp. on clock), short wires (bus length )

VDD: lowest suitable voltage

f: lowest suitable frequency

2

dynamic DDP CV

fE!


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Clock Gating The best way to reduce the activity is to turn off the clock to registers in

unused blocks Saves clock activity (E = 1) Eliminates all switching activity in the block

Requires determining if block will be used

Enable

Clock

Clock Gating


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Dynamic power reduction via dynamic VDD scaling

Scaling down supply voltage reduces dynamic power reduces saturation current

p increases delay p reduce the frequency

Dynamic voltage scaling (DVS):

Supply and voltage of the circuit should dynamic adjust according to the

workload of criticality of the tasks running on the circuitse.g: laptops in case connected with ac and on batteries.

2

d y n a m ic D DP C V f E!


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Leakage reduction via adjusting ofVth

Leakage depends exponentially on Vth. How to control Vth? Remember: Vth also controls your saturation current p delay

1. Oxide thickness

I1I2I3I4

I5I6

O1

O2

criticalpath

Sol1: statically choose high Vt cells fornon critical gates


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Static (leakage) power Static power is consumed even when chip is quiescent.

Leakage draws power from nominally OFF devices

0 1

gs t ds

T T

V V V

nv v

ds dsI I e e

!


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Leakage Control Leakage and delay trade off

Aim for low leakage in sleep and low delay in active mode

To reduce leakage:

Increase Vt: multiple Vt Use low Vt only in critical circuits

Increase Vs: stackeffect (series OFFtransistorshave less leakage) Inputvectorcontrolin sleep

Decrease Vb R

everse bodybia

s

in sleep Or forward body bias in active mode


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Gate Leakage Extremely strong function of tox and Vgs

Negligible for older processes Approaches subthreshold leakage at 65 nm and below in some processes

An order of magnitude less for pMOS than nMOS

Control leakage in the process using tox > 10.5 High-k gate dielectrics help Some processes provide multiple tox

e.g. thicker oxide for 3.3 V I/O transistors

Control leakage in circuits by limiting VDD


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Power Gating Turn OFF power to blocks when they are idle to save leakage

Use virtual VDD (VDDV) Gate outputs to prevent

invalid logic levels to next block

Voltage drop across sleep transistor degrades performance duringnormal operation Size the transistor wide enough to minimize impact

Switching wide sleep transistor costs dynamic power Only justified when circuit sleeps long enough


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Leakage reduction via Cooling

Impact of temperature on leakage current


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SummaryWe are still in chapter 4:

Delay estimation Power estimation

Interconnects and wire engineering Scaling theory

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lec4.4 Power Descipation