lec20-130220024011-phpapp01.ppt

Embed Size (px)

Citation preview

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    1/24

    1

    EET 3350 Digital Systems Design

    Textbook: John Wakerly

    Chapter 9: 9.1

    MemoryRead-Only Memory: ROM, PROM, EPROM

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    2/24

    Memory

    Sequential circuits all depend upon the presence of

    memory A flip-flop can store one bit of information

    A register can store a single word

    typically 32 or 64 bits

    Memory stores a large number of words

    Memory stores this large amounts of data using twoprimary device types

    Read Only Memory (ROM, PROM, EPROM, EEPROM)

    Random Access Memory (RAM)

    Static RAM (SRAM)

    Dynamic RAM (DRAM)

    2

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    3/24

    Memory

    You can think of memory as being

    one big array (list) of data The address serves as an array

    index

    Each address refers to one word

    of data (e.g., 8-bits, 16-bits, etc.)

    You can read (or modify) the dataat any given memory address,

    just like you can read (or modify)the contents of an array at anygiven index

    3

    Address Data

    00000000

    00000001

    00000002

    .

    .

    .

    .

    .

    .

    .

    .

    .

    .

    FFFFFFFD

    FFFFFFFE

    FFFFFFFF

    word

    0110101100111101

    1011111100100100

    1001110011110111

    0110101111010000

    1100101000110001

    0000101100001111

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    4/24

    Memory

    Memory signals fall into three groups:

    Address bus - selects one of many memory locations

    Data bus -

    Read (ROM/RAM): the selected locations stored data is

    put on the data bus

    Write (RAM): The data on the data bus is stored into theselected location

    Control signals - specifies what the memory is to do

    Control signals are usually active low

    Most common signals are:

    CS: Chip Select; must be active to do anything

    OE: Output Enable; active to read data

    WR: Write; active to write data

    4

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    5/24

    Memory

    Memory is not a single chip (device)

    Made up of many identical or similar devices

    A specific device (part of memory) is selected by controlsignals and the address lines (bus)

    All devices are connected to the same bus, and see the

    signals at the same time

    5

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    6/24

    Memory

    Memory Connection to CPU

    RAM and ROM chips are connected to a CPU throughthe data and address buses

    The low-order lines in the address bus select the bytewithin the chips and other lines in the address bus select

    a particular chip through its chip select inputs

    6

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    7/24

    Memory

    Location - the smallest selectable unit in memory

    Has 1 or more data bits per location

    All bits in location are read/written together

    Cannot manipulate single bits in a location

    For k address signals, there are 2k locations in a

    memory device

    Each location contains an n-bit word

    Memory size is specified as

    #loc x bits per location

    224 x 16 RAM - 224 = 16M words, each 16 bits long

    24 address lines, 16 data lines

    #bits

    The total storage capacity is 224 x 16 = 228 bits

    7

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    8/24

    Memory

    Memory sizes are usually specified in numbers of

    bytes(1 byte= 8 bits)

    The 228-bit memory on the previous page translatesinto:

    228

    bits / 8 bits per byte = 225

    bytes

    With the abbreviations below, this is equivalent to 32megabytes

    8

    Prefix Base 2 Base 10

    K Kilo 2 = 1,024 10 = 1,000M Mega 2 = 1,048,576 10 = 1,000,000

    G Giga 2 = 1,073,741,824 10 = 1,000,000,000

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    9/24

    Memory

    Non-volatile

    If un-powered, its content is retained

    Read-only normal operation cannot change

    contents

    k-bit ADRS specifies the address orlocation to read from

    A Chip Select, CS, enables ordisables the RAM/ROM

    An Output Enable, OE, turns on or offtri-state output buffers

    Data Out will be the n-bit value storedat ADRS

    9

    2k x n ROM

    ADRS Data

    Out

    kn

    CS

    OE

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    10/24

    Memory

    Content loading (programming) done many

    ways depending on device type ROM: mask programmed, loaded at the factory

    hardwired - cant be changed

    embedded mass-produced systems

    PROM: OTP (One Time Programmable),programmed by user, using an externalprogramming device

    EPROM: reusable, erased by UV light,programmed by user, using an externalprogramming device

    EEPROM: electrically erasable, clears entireblocks with single operation, programmed in-place (no need to remove from circuit board)

    10

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    11/24

    Read-Only Memories

    Definition

    ROM consists of an array of semiconductor devicesinterconnected to store an array of memory data.

    Data can only be read, it cannot be changed undernormal operating conditions.

    Types of ROM

    Mask programmable ROM (at the factory)

    Field-Programmable ROM (PROM)

    UV-Erasable and re-Programmable ROM (EPROM) Electrically-Erasable and re-Programmable ROM

    (EEPROM)

    Flash

    11

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    12/24

    Read-Only Memories

    The logic symbol below is used in circuit diagrams

    Focus is on the basic structure of a ROM

    A combinational logic circuit

    12

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    13/24

    Logic-in-ROM Example

    As we discussed previously, a ROM is simply a

    combinational circuit, basically a truth-table lookup Can perform any combinational logic function

    Address inputs = function inputs

    Data outputs = function outputs

    13

    (address) (data)

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    14/24

    Logic-in-ROM Example

    Two alternative implementations for the 3-input, 4-output

    logic function 2-to-4 decoder with output polarity control

    14

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    15/24

    4x4 Multiplier Example

    ROM implementation of a 4x4 unsigned binary

    multiplier Multiplier and multiplicand form the address

    Product is pre-programmed into the storage location

    15

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    16/24

    4x4 Multiplier Example

    ROM contents for the 4x4 unsigned binary multiplier

    16

    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    17/24

    Internal ROM Structure

    Typical implementation of primitive ROM

    17

    5

    active low

    data output

    Diode means a

    1 is stored at

    this location

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    18/24

    ROM

    Commercial ROM types

    18

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    19/24

    19

    Typical Commercial EEPROMs

    Logic symbols for representative EEPROMs

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    20/24

    ROM Control and I/O Signals

    n Address lines

    An-1 A0

    b Data lines

    Db-1 D0

    Chip Select

    One or more

    Active low

    Output Enable

    Active low

    Tri-state outputbuffers

    20

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    21/24

    21

    ROM Timing

    tAA (access time from address): propagation delay from stable

    address inputs to valid data output

    tACS ( access time from chip select): propagation delay from timeCS is asserted until the valid data output

    tOE (output-enable time): propagation delay from time OE and

    CS are asserted until the tri-state drivers have left Hi-Z state

    tOZ (output-disable time): propagation delay from time OE andCS are negated until the tri-state drivers have entered Hi-Zstate

    tOH (output-hold time): the length of time the outputs remainvalid after a change in the address inputs, or after OE and CSare negated

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    22/24

    22

    ROM Timing

    tAA access time from address

    tACS access time from chip select

    tOE/tOZ output-enable/disable time

    tOH output-hold time

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    23/24

    23

    ROM -Advantages and Disadvantages

    Ease of speed and design

    For moderately complex function a ROM-based circuit isusually faster than a circuit using multiple SSI/MSI devices andPLDs

    The program that generates the ROM contents can easily be

    structured to handle unusual or undefined cases that wouldrequire additional hardware in any other design. e.g. the adderprogram easily handles out-of-range sums.

    A ROMs function is easily modified just by changing the stored

    pattern, usually without changing any external connections The prices of ROMs are dropping and densities increasing

    making them more economical and expanding the scope with asingle chip

  • 7/29/2019 lec20-130220024011-phpapp01.ppt

    24/24

    24

    ROM -Advantages and Disadvantages

    May consume more power

    For functions with more inputs a ROM based circuit isimpractical because of the limit on ROM sizes that are available