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IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 12, DECEMBER 2012 1985 Lead-Free Flip-Chip Packaging Affects on Ultralow-k Chip Delamination Kuo Ming Chen, Yunn Horng Guu, and Tsung Shu Lin Abstract— Ultralow- k dielectric materials generally show weak mechanical strength ( E < 8 GPa), a high coefficient of thermal expansion (5 ppm/°C–8 ppm/°C), and poor adhesion (<5 J/m 2 –10 J/m 2 ). As a result, ultralow- k delamination becomes a major failure mode after the packaging reliability test. This paper investigates the propagation mechanism of ultralow- k delamination during the temperature cycling test (TCT). A full understanding this delamination processes is critical for selecting an adequate underfill and protecting both the ultralow- k chip and the lead-free solder bump. This paper shows that the ultralow- k delamination of lead free-flip-chip packaging after TCT starts near the outermost bump, and then propagates simultaneously to the corner and the central area of the chip. Finite element simula- tion is employed to analyze the packaging stress distribution and the ultralow- k delamination mechanism. An underfill selection methodology is proposed to prevent ultralow- k delamination and lead-free solder bump cracks. In addition, an underfill experiment is carried out to confirm the finite element simulation result and verify the ultralow- k delamination mechanism. Index Terms— Delamination, flip-chip, lead free, ultralow- k, underfill. I. I NTRODUCTION T HE Cu and ultralow-k combination is commonly used in microelectronic devices for the 40 nm and below technology node. Ultralow-k materials generally have low mechanical strength ( E < 8 GPa), a high coefficient of thermal expansion (CTE) (5 ppm/°C–8 ppm/°C), and poor adhesion (<5 J/m 2 –10 J/m 2 ) [1], [2]. The processes of solder or copper pillar bump fabrication, wafer sawing, die bonding, underfill curing, and solder reflow all induce a thermal stress directly in the ultralow-k chip, resulting in the risk of breaking the ultralow-k structure and/or cracking the bumps. In addition, the ultralow-k chip with lead-free solder bumps lowers the reliability performance of the flip-chip (FC) packaging com- pared to that of eutectic Sn/Pb bumps. This is due to the fact that the lead-free solder has a larger Young’s mod- ulus (28 GPa–49 GPa) and a higher melting temperature (217 °C–221 °C). As a result, ultralow-k delamination and Manuscript received January 14, 2011; revised March 4, 2012; accepted March 21, 2012. Date of publication November 16, 2012; date of current version December 3, 2012. Recommended for publication by Associate Editor D. Goyal upon evaluation of reviewers’ comments. K. M. Chen is with United Microelectronics Corporation, Hsinchu 300, Taiwan, and also with the Department of Mechanical Engineering, National United University, Miaoli 350, Taiwan (e-mail: [email protected]). Y. H. Guu is with the Department of Mechanical Engineering, National United University, Miaoli 350, Taiwan (e-mail: [email protected]). T. S. Lin is with United Microelectronics Corporation, Hsinchu 300, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2012.2193880 solder bump cracking are the common failure modes after the reliability test of the FC packaging. Chen et al. [3] have evalu- ated the underfills by comparing low-k and solder bump stress. Their results showed that an optimized underfill could enhance the reliability of Cu/low-k chip packaging. Wang et al. [4] demonstrated the correlation between the underfill properties and Cu/low-k delamination. Chang et al. [5] provided some design guidance to increase the reliability of low-k FC ball grid array assemblies through simulation. Lee et al. [6] demon- strated the process for selecting the underfill and discussed their concerns regarding low-k high lead/lead-free FC pack- aging. Most research papers seem to indicate that the underfill selection strategy for eliminating the low-k delamination and solder bump cracks was contradictory. However, all these stud- ies assume that the delamination is initiated at the corner of the chip (marked A in Fig. 1), then propagates toward the inside of the chip (center), and at the same time extends into the under- fill fillet. However, based on finite element simulation and the experimental results, this paper provides a clear explanation of the process of ultralow-k delamination and the direction and propagation of the solder bump cracks. This finding provides a good basic understanding for solving the issue of ultralow-k delamination. Next we provide a methodology for selecting the underfill so as to prevent ultralow-k delamination and solder bump cracking. Finally, an underfill evaluation experiment confirms the results of the finite element simulation. II. ULTRALOW-k DELAMINATION FAILURE The structure of the test vehicle consists of nine layers of copper combined with ultralow-k dielectrics with a constant value of 2.9 and 2.5, respectively. Fig. 2 shows a C-mode scan- ning acoustic microscope (CSAM) image of the delamination of a chip corner after 1000 temperature cycling test (TCT) cycles (-55 °C–125 °C) followed by JEDEC MSL4/245 °C, which was later identified as ultralow-k delamination by a scanning electron microscope, as shown as Fig. 3. The chip size of the test vehicle was 16 mm × 16 mm × 0.775 mm with a solder bump pitch of 162 μm. The lead-free solder bump composition was Sn–2.3%Ag. The built-up substrate consisted of eight copper layers (3/2/3) with an Ajinomoto dielectric film. The dimensions of the substrate were 40 mm × 40 mm × 1.16 mm. Fig. 3 shows the delamination at the interface of the underfill and the nitride passivation that extends into the ultralow-k layers. The dashed line in Fig. 2 shows the cross- section location of the FC packaging. The point of origin of the delamination is not identified at this stage. In the first stage, we assumed two possible failure mechanisms. The first 2156–3950/$31.00 © 2012 IEEE

Lead-Free Flip-Chip Packaging Affects on Ultralow-$k$ Chip Delamination

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IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 12, DECEMBER 2012 1985

Lead-Free Flip-Chip Packaging Affects onUltralow-k Chip Delamination

Kuo Ming Chen, Yunn Horng Guu, and Tsung Shu Lin

Abstract— Ultralow-k dielectric materials generally showweak mechanical strength (E < 8 GPa), a high coefficient ofthermal expansion (5 ppm/°C–8 ppm/°C), and poor adhesion(<5 J/m2–10 J/m2). As a result, ultralow-k delamination becomesa major failure mode after the packaging reliability test. Thispaper investigates the propagation mechanism of ultralow-kdelamination during the temperature cycling test (TCT). A fullunderstanding this delamination processes is critical for selectingan adequate underfill and protecting both the ultralow-k chip andthe lead-free solder bump. This paper shows that the ultralow-kdelamination of lead free-flip-chip packaging after TCT startsnear the outermost bump, and then propagates simultaneously tothe corner and the central area of the chip. Finite element simula-tion is employed to analyze the packaging stress distribution andthe ultralow-k delamination mechanism. An underfill selectionmethodology is proposed to prevent ultralow-k delaminationand lead-free solder bump cracks. In addition, an underfillexperiment is carried out to confirm the finite element simulationresult and verify the ultralow-k delamination mechanism.

Index Terms— Delamination, flip-chip, lead free, ultralow-k,underfill.

I. INTRODUCTION

THE Cu and ultralow-k combination is commonly usedin microelectronic devices for the 40 nm and below

technology node. Ultralow-k materials generally have lowmechanical strength (E <8 GPa), a high coefficient of thermalexpansion (CTE) (5 ppm/°C–8 ppm/°C), and poor adhesion(<5 J/m2–10 J/m2) [1], [2]. The processes of solder or copperpillar bump fabrication, wafer sawing, die bonding, underfillcuring, and solder reflow all induce a thermal stress directlyin the ultralow-k chip, resulting in the risk of breaking theultralow-k structure and/or cracking the bumps. In addition,the ultralow-k chip with lead-free solder bumps lowers thereliability performance of the flip-chip (FC) packaging com-pared to that of eutectic Sn/Pb bumps. This is due to thefact that the lead-free solder has a larger Young’s mod-ulus (28 GPa–49 GPa) and a higher melting temperature(217 °C–221 °C). As a result, ultralow-k delamination and

Manuscript received January 14, 2011; revised March 4, 2012; acceptedMarch 21, 2012. Date of publication November 16, 2012; date of currentversion December 3, 2012. Recommended for publication by Associate EditorD. Goyal upon evaluation of reviewers’ comments.

K. M. Chen is with United Microelectronics Corporation, Hsinchu 300,Taiwan, and also with the Department of Mechanical Engineering, NationalUnited University, Miaoli 350, Taiwan (e-mail: [email protected]).

Y. H. Guu is with the Department of Mechanical Engineering, NationalUnited University, Miaoli 350, Taiwan (e-mail: [email protected]).

T. S. Lin is with United Microelectronics Corporation, Hsinchu 300, Taiwan(e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2012.2193880

solder bump cracking are the common failure modes after thereliability test of the FC packaging. Chen et al. [3] have evalu-ated the underfills by comparing low-k and solder bump stress.Their results showed that an optimized underfill could enhancethe reliability of Cu/low-k chip packaging. Wang et al. [4]demonstrated the correlation between the underfill propertiesand Cu/low-k delamination. Chang et al. [5] provided somedesign guidance to increase the reliability of low-k FC ball gridarray assemblies through simulation. Lee et al. [6] demon-strated the process for selecting the underfill and discussedtheir concerns regarding low-k high lead/lead-free FC pack-aging. Most research papers seem to indicate that the underfillselection strategy for eliminating the low-k delamination andsolder bump cracks was contradictory. However, all these stud-ies assume that the delamination is initiated at the corner of thechip (marked A in Fig. 1), then propagates toward the inside ofthe chip (center), and at the same time extends into the under-fill fillet. However, based on finite element simulation and theexperimental results, this paper provides a clear explanation ofthe process of ultralow-k delamination and the direction andpropagation of the solder bump cracks. This finding providesa good basic understanding for solving the issue of ultralow-kdelamination. Next we provide a methodology for selecting theunderfill so as to prevent ultralow-k delamination and solderbump cracking. Finally, an underfill evaluation experimentconfirms the results of the finite element simulation.

II. ULTRALOW-k DELAMINATION FAILURE

The structure of the test vehicle consists of nine layers ofcopper combined with ultralow-k dielectrics with a constantvalue of 2.9 and 2.5, respectively. Fig. 2 shows a C-mode scan-ning acoustic microscope (CSAM) image of the delaminationof a chip corner after 1000 temperature cycling test (TCT)cycles (−55 °C–125 °C) followed by JEDEC MSL4/245 °C,which was later identified as ultralow-k delamination by ascanning electron microscope, as shown as Fig. 3. The chipsize of the test vehicle was 16 mm × 16 mm × 0.775 mm witha solder bump pitch of 162 μm. The lead-free solder bumpcomposition was Sn–2.3%Ag. The built-up substrate consistedof eight copper layers (3/2/3) with an Ajinomoto dielectricfilm. The dimensions of the substrate were 40 mm × 40 mm ×1.16 mm. Fig. 3 shows the delamination at the interface ofthe underfill and the nitride passivation that extends into theultralow-k layers. The dashed line in Fig. 2 shows the cross-section location of the FC packaging. The point of origin ofthe delamination is not identified at this stage. In the firststage, we assumed two possible failure mechanisms. The first

2156–3950/$31.00 © 2012 IEEE

1986 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 12, DECEMBER 2012

Fig. 1. Ultralow-k delamination initiated from chip corner (point A), thenpropagated into the chip and underfill.

was that the delamination initially started at the interface ofthe underfill and the nitride passivation layer at the cornerof the chip (marked B in Fig. 3), and that it then broke thenitride passivation layer and propagated into the ultralow-klayer (marked C in Fig. 3). This assumption was based on ourprevious experience. However, by comparing the failure modewith other underfill delamination failure cases, we found thatthe underfill delamination propagated along the interface ofthe underfill and the nitride passivation but did not penetratethe nitride passivation layer. However, there was a sticking-out geometry due to the fact that nitride passivation has ahigh Young’s modulus (270 GPa) and creates a high hardnessmaterial, usually showing poor adhesion with the underfill.The second assumption was that the delamination was initiatedby the ultralow-k layer near the outermost bump in the cornerof the chip (marked C in Fig. 3), then propagated to thecentral area of the chip, and then to the chip’s outer edge andcorner along the interface of the nitride passivation (Si3N4)and the underfill (marked B in Fig. 3). This indicates that thedelamination propagated from C to B in Fig. 3. However, thisassumption differs slightly from those of previous reports andneeds to be verified.

III. FINITE ELEMENT ANALYSIS

Fig. 4(a) shows the top view of the FC packaging. Thispaper uses a slice model with one ultralow-k layer insteadof a detailed ultralow-k structure to establish a FC packag-ing finite element model. An element of Solid 185 type isused to construct the finite element model. The 3-D slicemodel includes 511 810 nodes and 477 404 elements. Fig. 4(b)shows the cross-section geometry and the applied boundarycondition of the slice model for the finite element analysis.Fig. 5(a) and (b) shows the one of detailed bump geometryand the meshed model. The underfill material is temperaturedependent, and the other materials are assumed to be linearlyelastic. Table I lists the material properties that were usedin the finite element simulation. The stress-free temperaturewas set at 165 °C, which is the underfill curing temperature.The cooling down process (125 to −55 °C) was simulated tocatch the stress distribution in the ultralow-k layer during the

Fig. 2. CSAM showing ultralow-k delamination at chip corner.

TABLE I

MATERIAL PROPERTIES

Items Young’smodulus (GPa) CTE (ppm/°C) Poisson’s

ratio

Bump(Sn-2.3%Ag)

59 at −55 °C45 at 40 °C28 at 135 °C

22 0.35

Silicon 131 2.8 0.28

Underfill

8/0.047 (Tg =80 °C)

(under Tg /overTg )

32/102 (Tg =80 °C)

(under Tg /overTg )

0.35

UBM 149 14.5 0.33

Solder mask 3.5

42/98 (Tg =120 °C)

(under Tg /overTg )

0.43

Substrate 26/26/11(x/y/z)

12.4/12.4/57(x/y/z)

0.39/0.22/0.22xy/yz/xz

Aluminum 71 23 0.33

Copper 121 16.3 0.34

Oxide (SiO2) 72 2.7 0.16

Ultralow-kdielectric

8 5 0.16

Nitridepassivation

270 5 0.28

Polyimide 3.5 35 0.35

TCT. The change in underfill modulus is not quick when thetemperature drops across the glass transition temperature (Tg)of the underfill. In this paper, we assumed that the underfillmodulus increased starting at 85 °C and was stabilized at 75 °Cduring the cooling down process.

IV. SIMULATION RESULTS

A. First Principal Stress of the Ultralow-k Layer

The positive first principal stress (σ1) indicates the directionof the greatest tensile stress of a point in a stressed solid body.

CHEN et al.: LEAD-FREE FLIP-CHIP PACKAGING AFFECTS ON ULTRALOW-k CHIP DELAMINATION 1987

Fig. 3. Cross section of the delamination area.

(a)

(b)

Fig. 4. Test vehicle. (a) Top view picture. (b) Cross-section geometry.

This maximum tensile stress has the highest possibility ofcausing a crack or fracture. This crack or fracture is roughlyperpendicular to the first positive principal stress [7], [8].In our previous study, we demonstrated that the first principalstress shows high correlation with the ultralow-k delamina-tion [3]. Fig. 6 shows the maximum first principal stress(σ1) in the ultralow-k layer and the underfill modulus overthe TCT range. It is evident that the tensile stress is highlycorrelated to the modulus of the underfill. The maximum stressoccurred at 85 °C. It is apparent that, without the support ofa hard underfill at the high-temperature stage, the increase instress is faster than that at the low-temperature stage when

(a)

(b)

Fig. 5. Solder bump. (a) Solder bump geometry. (b) Meshed solder bumpmodel.

the temperature decreases. The largest temperature differencewas at −55 °C and the maximum stress occurred at 85 °C.Fig. 7 shows the σ1 contour plot of the ultralow-k layer at 85and −55 °C, respectively. Mark D indicates the location of themaximum stress, which is above the outmost bump. The chipcorner was subjected to the largest tensile stress at −55 °C, asindicated by mark E. The underfill modulus above Tg (8 GPa)is about 170 times lower than that below Tg (0.047 GPa).The low underfill modulus cannot provide enough support tothe bump to absorb the thermal stress caused by the organicsubstrate and the chip CTE mismatch. The low underfill mod-ulus does not damage the ultralow-k chip because the eutectic

1988 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 12, DECEMBER 2012

Fig. 6. Maximum first principal stress (σ1) in the ultralow-k layer.

(a)

(b)

Fig. 7. σ1 contour plot of ultralow-k layer. (a) σ1 contour at 85 °C.(b) σ1 contour at −55 °C (dark blue color means compress stress).

solder bump is softer than a lead-free solder bump at the sametemperature. Thus the thermal stress is relieved by the shearingdeformation action of the solder bump. However, the lead-free solder bump possesses a higher stiffness over the entiretemperature range of the TCT [9], [10]. The shearing force atthe bottom of the lead-free bump caused by the shrinking ofthe substrate forces the solder bump to rotate clockwise. Asa result, the maximum tensile stress in the ultralow-k layeroccurs at point D, which is the top right of the lead-free

(a)

(b)

Fig. 8. Uniformed σ1 tensor plot of ultralow-k layer (dash arrow is apotential crack propagation direction). (a) σ1 contour and tensor plot ofwith interfacial delamination case. (b) σ1 contour and tensor plot of withoutinterfacial delamination case.

outermost bump in Fig. 7(a). When the temperature decreases,the underfill gradually hardens. The high stiffness underfillconstrains the bump movement and results in the tensile stressat mark D decreasing significantly, as shown in Fig. 7(a). TheCTE of the underfill (32/102 ppm/°C) is larger than that ofthe solder bumps (22 ppm/°C) and, at −55 °C, causes a shrinkstress between the chip and the organic substrate, resulting in alarge compressive stress region [the dark blue area in Fig. 7(a)]above the solder bump. The ultralow-k layer is located on theoutside outmost bumps, and behaves like a cantilevered beam,because only one side is supported by the solder bump. Theshrinking underfill then induces a tensile stress at the free endof the cantilevered beam. In addition, the hard underfill alsopasses the shrinking stress of the substrate to the corner of thechip, resulting in an oblique tensile stress at the ultralow-klayer on the corner of the chip. Although the stress at mark Dis higher than that at mark E, it is not adequate to judge thedelamination initiation point by comparing the stress levels.This simulation does not consider the details of the copperand ultralow-k interconnected structure but estimates the diesaw damage at the corner of the chip. However, the simulationresults show that the ultralow-k layer located on the solderbump surface also sustains a large tensile stress, except forthe corner of the chip.

CHEN et al.: LEAD-FREE FLIP-CHIP PACKAGING AFFECTS ON ULTRALOW-k CHIP DELAMINATION 1989

(a)

(b)

Fig. 9. Underfill first principal stress contour and tensor plot. (a) Underfillmodulus variation. (b) Underfill CTE variation.

B. First Principal Stress Direction of the Ultralow-k Layer

Fig. 8(a) and (b) shows the σ1 tensor plots of the ultralow-klayer at 85 and −55 °C, respectively. The stress directionis indicated by the arrow. Both ultralow-k stresses for thedifferent temperatures have a similar direction. The dashedarrow shows the potential crack propagation direction basedon the crack propagation rule prediction. If the initial crackpoint occurs at the ultralow-k layer in the corner of the chip,then the crack will propagate toward to chip’s silicon substrateand will be trapped in the top (last) ultralow-k layer. As aresult, the crack cannot penetrate the silicon substrate of thechip (shown in Fig. 1). This delamination status fulfills thecrack propagation rule prediction. If the initial starting pointof the crack occurs at the inside of the chip, then the crackwill propagate toward the nitride passivation layer of the chip(shown in Fig. 3). If the initial crack point occurs at theinterface of the corner of the chip between the underfill and thenitride passivation layer of the chip, then the failure mode alsomeets the crack propagation rule. The finite element simulationresult provides the possibility of the second assumption, whichassumes that the delamination is initiated by the ultralow-klayer near the outmost bump in the chip inside corner, thenpropagates to the central area of the chip, and then travel tothe chip’s outer edge, extending to the chip’s corner along theinterface of the nitride passivation and underfill (chip corner).

C. First Principal Stress of the Underfill

By comparing the direction of the propagation of theunderfill cracks at the corner of the chips, it is easy to see that

(a)

(b)

Fig. 10. Underfill modulus and CTE variation study results. (a) Underfillmodulus variation. (b) Underfill CTE variation.

Fig. 11. Underfill Tg variation study result.

the crack in Fig. 3 is more vertical than the one in Fig. 1. If thedelamination is initiated from the inside of the chip, and thenpropagates to chip’s corner, then the interfacial delaminationbetween the underfill and the chip nitride passivation layerwill occur prior to the initial crack point in the underfill.This may result in a different direction for the propagationof the underfill crack. This can be verified by comparingthe direction of the first principal stresses in the underfillwith and without interfacial delamination between underfilland chip nitride passivation simulation models. The maximumfirst principal stress (σ1) of the underfill at the chip’s corneroccurred at −55 °C. Fig. 9(a) shows the contour and the tensor

1990 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 12, DECEMBER 2012

TABLE II

UNDERFILL EVALUATION EXPERIMENTS RESULT

Items UF-A UF-B UF-C UF-D

Tg (°C) 80 100 100 90

CTE(ppm/°C)(over

Tg /underTg)

32/102 27/92 32/110 28/103

Modulus(GPa)(over

Tg /underTg)

8/0.047 9.5/0.11 7.3/0.085 9/0.08

σ1 pointD (MPa)

95.6 60.7 73 75.6

σ1 pointE (MPa)

75 70 69 75

σeqvbump(MPa)

920 803 890 870

TCT 500cycles(failure

rate)

Ultralow-kdelamination:

15/450/45

Ultralow-kdelamination:

1/45Bump crack:

4/45

Ultralow-kdelamination:

3/45

TCT1000cycles(failure

rate)

- 0/45

Ultralow-kdelamination:

5/45Bump crack:

8/45

Ultralow-kdelamination:

3/45

Fig. 12. Ultralow-k layer delamination.

plot underfill stress with and without interfacial delamination.The direction of the stress in the underfill with interfacialdelamination is more horizontal than that without interfacialdelamination. This indicates that underfill cracks propagatemore in the vertical direction. This result provides robustevidence that the delamination is initiated from inside the chip,and then propagates to the corner of the chip.

D. Study of the Variation in the Properties of the UnderfillMaterial

The variation of properties of the underfill material wasinvestigated in order to evaluate the effect of the mechanicalproperties of the underfill on the stress in the ultralow-k layer.The evaluated items included the underfill modulus, the CTE,and Tg . The range of variation for each item was ±20%. Whenone of the evaluated properties was varied, the rest of the

Fig. 13. Lead-free solder bump crack.

evaluated properties were kept fixed. Fig. 10(a) and (b) showsthe normalized modulus of the underfill and the result of theCTE variation, respectively. An underfill with a high modulusand a high CTE is preferred for preventing delamination insidethe ultralow-k (mark D). On the other hand, an underfill witha low modulus and a low CTE is preferred for preventingdelamination of ultralow-k at the chip corner (point E). It isevident that the stress at point E is more sensitive to theunderfill with a normalized modulus and CTE due to the largeslope of the simulation results. Fig. 11 shows the effect of Tg

on the first principal stress of points D and E. The high-Tg

underfill significantly reduces the stress at point D, becausethis underfill can provide a more robust support earlier to thebump than a low-Tg underfill when the temperature is broughtdown from 125 to −55 °C. In addition, the high-Tg underfillcan reduce the stress at point E since such an underfill has asmaller thermal expansion at −55 °C, and the effect is similarto that of a low-CTE underfill. However, it should be notedthat this improvement is relatively small.

V. EXPERIMENTAL RESULTS AND DISCUSSION

Table II lists the mechanical properties of the three underfillcandidates selected and the results of the TCT evaluationexperiments. The failure modes of underfill C (UF-C) arebump cracking and ultralow-k delamination. The failure modeof underfill D (UF-D) is ultralow-k delamination. Only under-fill B (UF-B) passes the reliability test. The finite elementsimulation result correlates well with the experimental result.UF-B has the lowest stress in the ultralow-k layer and thelead-free solder bump. Fig. 12 shows the cross-section ofthe failed sample using UF-C. It shows that the delaminationpropagates in the ultralow-k layer and does not penetrate thenitride passivation layer of the chip. Fig. 12 provides robustevidence for the second assumption, in which the ultralow-k delamination is initiated from inside the chip and thenpropagates to the chip’s corner. Fig. 13 shows the lead-freesolder bump crack in the UF-C sample.

CHEN et al.: LEAD-FREE FLIP-CHIP PACKAGING AFFECTS ON ULTRALOW-k CHIP DELAMINATION 1991

VI. CONCLUSION

This paper demonstrated the failure mechanism of ultralow-k delamination for lead-free solder bump FC packaging. Thestrategy of selecting the underfill for eliminating ultralow-kdelamination is based on the starting point of the delamination.The selection of the underfill for solving ultralow-k delamina-tion assuming that the starting point of the delamination is atthe corner of the chip is contrary to the common assumptionthat the starting point of the ultralow-k delamination is atthe outermost bump inside the chip. The delamination ofthe chip’s corner is more sensitive to the underfill modulusand CTE. In addition, inside the chip delamination, theoutermost bump is more sensitive to the underfill Tg . Thisfinding prevents the underfill selection strategy from gettingtrapped in a dilemma. Furthermore, the underfill selectionstrategy also takes into consideration the elimination of bumpcrack failure for lead-free FC packaging. Finally, the finiteelement simulation results of this paper correlated well withthe results of the experimental FC packaging reliability test.

ACKNOWLEDGMENT

The authors would like to thank Silicon Precision IndustryLtd., Taichung, Taiwan, for its strong support in the flip-chipassembly.

REFERENCES

[1] K. M. Chen, “Ultralow-k die crack study for lead free solder bumpflip-chip packaging,” J. Mater. Sci.: Mater. Electron., vol. 22, no. 8, pp.988–994, Nov. 2010.

[2] L. L. Mercado, S.-M. Kuo, C. Goldberg, and D. Frear, “Impact of flip-chip packaging on copper/low-k structures,” IEEE Trans. Adv. Packag.,vol. 26, no. 4, pp. 433–440, Nov. 2003.

[3] K. M. Chen, D. S. Jiang, N. H. Kao, and J. Y. Lai, “Effects of underfillmaterials on the reliability of low-k flip-chip packaging,” Microelectron.Rel., vol. 46, no. 1, pp. 155–163, Jan. 2006.

[4] T. H. Wang, Y.-S. Lai, and M.-J. Wang, “Underfill selection for reducingCu/low-K delamination risk of flip-chip assembly,” in Proc. Electron.Packag. Technol. Conf., Dec. 2006, pp. 233–236.

[5] K.-C. Chang, Y. Li, C.-Y. Lin, and M.-J. Lii, “Design guidance for themechanical reliability of low-k flip chip BGA package,” in Proc. Int.Microelectron. Packag. Soc. Conf., Austin, TX, Jun. 2004, pp. 1–5.

[6] W. H. Lee, D. S. Jiang, Y. P. Wang, and C. S. Hsiao, “Underfill selectionstrategy for low-k, high lead/lead free flip chip application,” in Proc.Microsyst., Packag., Assembly Circuits Technol., 2007, pp. 338–341.

[7] J. Lemaitre and R. Desmorat, Engineering Damage Mechanics: Duc-tile, Creep, Fatigue and Brittle Failures. New York: Springer-Verlag,2005.

[8] E. E. Gdoutos, Fracture Mechanics: An Introduction, 2nd ed. New York:Springer-Verlag, 2005.

[9] D. H. Kim, P. Elenius, and S. Barrett, “Solder joint reliability andcharacteristics of deformation and crack growth of Sn-Ag-Cu versuseutectic Sn-Pb on a WLP in a thermal cycling test,” IEEE Trans.Electron. Packag. Manuf., vol. 25, no. 2, pp. 84–90, Apr. 2002.

[10] A. A. Shapiro, J. K. Bonner, O. A. Ogunseitan, J.-D. M. Saphores, andJ. M. Schoenung, “Implications of Pb-free microelectronics assemblyin aerospace applications,” IEEE Trans. Compon. Packag. Technol., vol.29, no. 1, pp. 60–70, Mar. 2006.

Kuo Ming Chen received the B.E. degree inmechanical engineering from the National TaiwanUniversity of Science and Technology, Taipei, Tai-wan, the M.E. degree in mechanical engineeringfrom the National Cheng Kung University, Tainan,Taiwan, and the Ph.D. degree in power mechanicalengineering from the National Tsing Hua University,Hsinchu, Taiwan.

He joined the United Microelectronics Corpora-tion, Hsinchu, in 2000. Currently, he is a SeniorManager in the Department of Packaging Engineer-

ing and 3-DIC Chip Stacking Engineering. He has been working on variousadvanced packaging developments. His current research interests includeCu/ultralow-k, bumping, flip-chip, copper wire bonding CPI packaging, 3-DIC through-silicon via, 2.5-D Si interposer assembly, fine pitch bonding,wafer-level integration, and microsystem packaging.

Yunn Horng Guu received the Ph.D. degree inpower mechanical engineering from the NationalTsing Hua University, Hsinchu, Taiwan, in 2000.

He is currently an Associate Professor with theNational United University, Miaoli, Taiwan. He iscurrently devoted to developing the industry-orientedcourse in electronic flip-chip packaging technology.His current research interests include the fabrica-tion of microdevices, electronic packaging, computeraided engineering, fatigue of microdevices, and non-conventional machining.

Tsung Shu Lin received the M.Sc. degree inmechanical and aerospace engineering fromChuang-Hua University, Hsinchu, Taiwan.

He joined CADMEN (ANSYS distributor inTaiwan), Taipei, Taiwan. Then, he progressed toElitecrown Ltd., Taipei, and after a few years of con-sultancy work, he moved to United MicroelectronicsCorporation (UMC), Hsinchu. He is currently aTechnical Manager with the Packaging Department,UMC, where he is in charge of simulation work forthe development of wafer-level chip-scaled pack-

ages, flip-chip ball grid arrays, flip-chip chip-scale packages, and assemblyprocesses. He has over ten years of experience in finite element analysis.