LD Lab Manual 2011 Final

Logic Design Lab 2011-12

a. AND GATE (7408)

b. OR GATE(7432)

c. NOT GATE( 7404)

Dept. of ECE, CIT, Gubbi 1


Experiment No. 1: Verification of Logic Gates

Aim: To study and verify the truth table of logic gates.

Apparatus required: IC Trainer Kit, patch chords, IC 7408, IC 7432, IC 7400, IC 7402, IC 7404.

Procedure:

1. Place the IC on IC Trainer Kit.2. Connect VCC and ground to respective pins of IC Trainer Kit.3. Connect the inputs to the input switches provided in the IC Trainer Kit.4. Connect the outputs to the switches of O/P LEDs.5. Apply various combinations of inputs according to the truth table and observe

condition of LEDs.

Theory:1. BASIC GATES;

a) AND GATE: The AND gate performs a logical multiplication commonly known as AND function. The output is high when both the inputs are high. The output is in low level when any one of the inputs is low.Symbol:

b) OR GATE: The OR gate performs a logical addition commonly known as OR function. The output is high when any one of the inputs is high. The output is low level when both the inputs are low.Symbol:

c) NOT GATE: The NOT gate is called an inverter. The output is high when the

input is low. The output is low when the input is high.Symbol:


A Y

Y=


d) NAND GATE (7400)

e) NOR GATE (7402)

f) EX-OR GATE (7486)



2. UNIVERSAL GATES:

g) NAND GATE: The NAND gate is a compliment of AND-NOT. The output is high when both inputs are low and any one of the input is low .The output is low

level when both inputs are high. Symbol:

h) NOR GATE: The NOR gate is a compliment of OR-NOT. The output is high when both inputs are low. The output is low when one or both inputs are high.Symbol:

i) X-OR GATE: The output is high when any one of the inputs is high. The output is low when both the inputs are low and both the inputs are high.Symbol:

Result:


A

BY


1) Y1= (A+BC)(B+A )

Simplification:

Y1= (A+BC)(B+A ) ( Given Expression)

= AB+ A +BC (Using basic gates)

=

= . . (Using NAND Gates)

Y1= ( A+BC)(B+ A )

= (A+B)(A+C)(B+A)(A+ )

=

= + + ( (Using only NOR gates)

Using Basic Gates Truth table

Using only NAND gates Using only NOR gates

Experiment No. 2: Simplification and Realization of Boolean Expression


A B C Y10 0 0 00 0 1 00 1 0 00 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1

A B C

Y1

A B C

Y111

A B C

Y

11


Aim: Simplify and realize the given Boolean expressions using logic gates/universal

gates.

Apparatus required: IC Trainer Kit, patch chords, IC 7408, IC 7432, IC 7400, IC 7402, IC 7404.

Procedure:

1. Fix the IC on the base board.

2. Connections are made as shown in the circuit Diagram.

3. Verify the truth Table for each expression.

2) Y=(A,B,C,D)= Σ(5,7,9,11,13,15) Simplification:



Y= A’BC’D+A’BCD+AB’C’D+AB’CD+ABC’D+ABCD =A’BD(C+C’)+AB’D(C+C’)+ABD(C+C’) =A’BD+AB’D+ABD =BD(A+A’)+AB’D =BD+AB’D =D(B+AB’) =D(A+B) =AD+BD

Using Basic Gates

Using NAND gates Using NOR gates

Truth table

Simplification:



3) Q = AB + BC(B + C)

Using Basic gates:

Truth table:

A B C Q0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Half Adder:



a) Half Adder using Basic gates

b) Half Adder using NAND Gates

Truth table


A B SUM (S)

CARRY(C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

AB

S= AB

C= AB

A

B

S=AB

C=AB


Experiment No 3: Half Adder & Full Adder

Aim: Realization of Half & Full adder using logic gates.

Apparatus Required:

Procedure: 1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Switch on VCC and apply various combinations of input according to the truth

table.

4. Note down the output readings for half & full adder (sum and carry bits) for

different combinations of inputs.


Sl no Particulars Quantity

1 IC 7400 3

2 7404,7486,7408 1


FULL ADDER:

a) Full Adder using Basic Gates

b) Full Adder using NAND Gates only



Theory:

A half adder is a logical circuit that performs an addition operation on two binary

digits. The half adder produces a sum and a carry value which are both binary digits.

The drawback of this circuit is that in case of a multi bit addition, it cannot include a

carry. A full adder is a logical circuit that performs an addition operation on three

binary digits. The full adder produces a sum and carry value, which are both binary

digits. It can be combined with other full adders or work on its own.

K-Map Simplification

1) SUM

2) CARRY


0000SUM= S= ABC

00 01 11 10

0

1

AB

C

1 1

0010011

C= AB+C(AB)

00 01 11 10

0

1

AB

C


Half Subtractor:

a) Half Subtractor using Basic gates

b) Half Subtractor using NAND Gates

Truth Table:


A B Diff(D) Borrow( Bo )

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

A

BD= AB

Bo = A B

A

B

D=AB

Bo = B


Experiment No 4: Half Subtractor & Full Subtractor

Aim: Realization of Half & Full subtractor using logic gates.

Apparatus Required:

Procedure: a) Verify the gates.

b) Make the connections as per the circuit diagram.

c) Switch on VCC and apply various combinations of input according to the truth

table.

d) Note down the output readings for half & full subtractor (difference and borrow

bits) for different combinations of inputs.



1 IC 7400 3

2 7432,7404,7486,7408 1


Full Subtractor:

1. Full Subtractor using Basic Gates

2. Full Subtractor using NAND Gates only

Truth Table:

Diff= A B C B0= B+C(A B)


A B C Diff Borrow0 0 0 0 00 0 1 1 10 1 0 1 10 1 1 0 11 0 0 1 01 0 1 0 01 1 0 0 01 1 1 1 1

Bo= B+C(A B)

A

B

C

D= ABC

A

B

Bo= B+C(A B)

D= AB C

C


Theory:

The half-subtractor is a combinational circuit which is used to perform subtraction of two

bits. It has two inputs, A (minuend) and B (subtrahend) and two outputs D (difference)

and B (borrow).

K-Map Simplification

a) DIFFERENCE:

b) BORROW:


0000Diff= ABC

00 01 11 10

0

1

AB

C

1 1

0100110

B0= B+C (AB)

00 01 11 10

0

1

AB

C


PARALLEL ADDER/SUBTRACTOR Circuit

Truth Table:

Addition:

Decimal no

Binary Equivalent No. 1


Output Sum

A B A3 A2 A1 A0 B3 B2 B1 B0 Co S3 S2 S1 S09 5 1 0 0 1 0 1 0 1 0 1 1 1 012 8 1 1 0 0 1 0 0 0 1 0 1 0 0

Subtraction:

Decimal no



Output Difference

A B A3 A2 A1 A0 B3 B2 B1 B0 Co S3 S2 S1 S08 14 1 0 0 0 1 1 1 0 0 1 0 1 08 2 1 0 0 0 0 0 1 0 1 0 1 1 0


B3 B2 B1 B0

1 3 8 10 16 4 7 11

5

1214 15 2 6 9

13VCC

GND

Cout S3 S2 S1 S0

A3 A2 A1 A0

Ctrl=0 to add=1 to subtract

IC 7483 Cin


Experiment No. 5: Parallel Adder/ Subtractor

Aim: To Realize Parallel Adder / subtractor using IC7483

Apparatus Required:

Procedure:

1. Make the connections as shown in the fig.

2. For Addition make Cin=0 and apply 4 bits of i/p for A and apply another set of 4 bits to

B. Observe the O/P at S3 S2 S1 S0 and Carry generated at Cout. Repeat the steps for

different inputs and tabulate the results.

3. For Subtraction, Cin=1(A-B) By XOR-ing the i/p bits of B by1,1’s complement of B is

obtained.

4. Verify the difference at S0,S1,S2,S3 and Cout. If Cout is 1, difference is -ve and

difference is in 2’s complement. If Cout is 0, difference is +ve.

e) Repeat the above steps and tabulate the result.

Block Diagram



1 IC 7483 1

2 IC 7404 1


Circuit diagram for BCD to Excess-3 Code Conversion

Truth Table:BCD to Excess-3 Excess-3 to BCD

Experiment No. 6: BCD TO EXCESS 3 AND EXCESS 3 TO BCD


BCD i/p Excess o/pB3 B2 B1 B0 E3 E2 E1 E00 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 0

Excess i/pE3 E2 E1 E00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 0

BCD o/pB3 B2 B1 B00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1

B3 B2 B1 B0

E0

E1

E2

E3


Aim: To verify BCD to excess –3 code conversion using NAND gates. To study and verify the truth table of excess-3 to BCD code converter. Apparatus Required:

Procedure: 1. Make the connections as shown in the fig.

2. Pin [14] of all IC’S are connected to +5V and pin [7] to the ground.

3. The inputs are applied at E3, E2, E1, and E0 and the corresponding outputs at B3, B2,

B1, and B0 are taken for excess – 3 to BCD.

4. B3, B2, B1, and B0 are the inputs and the corresponding outputs are E3, E2, E1 and E0

for BCD to excess – 3.

5. Repeat the same procedure for other combinations of inputs.

Theory:

In computing and electronic systems, binary-coded decimal (BCD) (sometimes called

natural binary-coded decimal, NBCD) is an encoding for decimal numbers in which

each digit is represented by its own binary sequence. Its main virtue is that it allows easy

conversion to decimal digits for printing or display and faster decimal calculations. Its

drawbacks are the increased complexity of circuits needed to implement mathematical

operations and a relatively inefficient encoding—it occupies more space than a pure

binary representation. To BCD-encode a decimal number using the common encoding,

each decimal digit is stored in a four-bit nibble.

Decimal: 0 1 2 3 4 5 6 7 8 9

BCD: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

Thus, the BCD encoding for the number 127 would be: 0001 0010 0111

Excess-3 is a non weighted code used to express decimal numbers. In XS-3, numbers are

represented as decimal digits, and each digit is represented by four bits as the BCD value

plus 3 (the "excess" amount). The primary advantage of XS-3 coding over BCD coding is

that a decimal number can be nines' complemented (for subtraction) as easily as a binary

number can be ones' complemented; just invert all bits.

Circuit diagram for Excess-3 to BCD Code Conversion



1 IC 7486.7408,7404 1

2 IC 7432,7483 1


K-map Simplification: a) BCD to Excess-3 Conversion

E3: B3+B2(B0+B1) E2= (B0+B1)+B2

E0=


B0

B1

B2

B3

E3 E2 E1 E0

00000111XXXX11XX

00 01 11 10

00

01

11

10

B1B0

B3B2

01111000XXXX01XX

00 01 11 10

00

01

11

10

B1B0

B3B2

E1=


b) Excess-3 to BCD Conversion:

B3= E2E3+E3E1E0 B2=E2E1E0+ ( + )

B1=E0 E1 B0=

Circuit diagram for BINARY to GRAY Code Conversion using X-OR gates


10101010XXXX10XX

00 01 11 10

00

01

11

10

B1B0

B3B2

10011001XXXX10XX

00 01 11 10

00

01

11

10

B1B0

B3B2

XX0X00001XXX0010

00 01 11 10

00

01

11

10

E1E0

E3E2

XX0X00100XXX1101

00 01 11 10

00

01

11

10

E1E0

E3E2

XX0X01010XXX0101

00 01 11 10

00

01

11

10

E1E0

E3E2 XX0X10011XXX1001

00 01 11 10

00

01

11

10

E1E0

E3E2

B3

B2

B1

B0

G3

G2

G1

G0


Truth Table:

Binary i/p Gray code o/pB3 B2 B1 B0 G3 G2 G1 G00 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 0 1 1 10 1 1 0 0 1 0 10 1 1 1 0 1 0 01 0 0 0 1 1 0 01 0 0 1 1 1 0 11 0 1 0 1 1 1 11 0 1 1 1 1 1 01 1 0 0 1 0 1 01 1 0 1 1 0 1 11 1 1 0 1 0 0 11 1 1 1 1 0 0 0

Experiment No. 7: BINARY TO GRAY AND GRAY TO BINARY



Aim: To verify Binary to gray conversion using EX-OR and Universal gates and to study and verify the truth table of Gray to Binary code converter. Apparatus Required:

.

Procedure:1. Make the connections as shown in the fig.

2. Pin [14] of all IC’S are connected to +5V and pin [7] to the ground.

3. The inputs are applied at G3, G2, G1, and G0 and the corresponding outputs at B3, B2,

B1, and B0 are taken for Gray to Binary.

4. B3, B2, B1, and B0 are the inputs and the corresponding outputs

Theory:

This is a variable weighted code and is cyclic. This means that it is arranged so that every

transition from one value to the next value involves only one bit change. The gray code is

sometimes referred to as reflected binary, because the first eight values compare with

those of the last 8 values, but in reverse order.

Circuit diagram for BINARY to GRAY Code Conversion using NAND gates


Sl no Particulars Quantity1 IC 7486.7400 1

Bo

B1

B2

B3

Go

G1

G2

G3


G3= B3 G2= B2 B3

Circuit diagram for GRAY to BINARY Code Conversion using basic gates


0000000

011111111

00 01 11 10

00

01

11

10

B1B0

B3B2

0000111

100001111

00 01 11 10

00

01

11

10

B1B0

B3B2

G3

G2

G1

G0

B3

B2

B1

B0


Truth Table:

Circuit diagram for GRAY to BINARY Code Conversion using NAND gates


GRAY i/p BINARY o/pG3 G2 G1 G0 B3 B2 B1 B00 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 10 1 0 1 0 1 1 00 1 1 0 0 1 0 00 1 1 1 0 1 0 11 0 0 0 1 1 1 11 0 0 1 1 1 1 01 0 1 0 1 1 0 01 0 1 1 1 1 0 11 1 0 0 1 0 0 01 1 0 1 1 0 0 11 1 1 0 1 0 1 11 1 1 1 1 0 1 0

G0o

G1

B2

B3

B1

G2

G3


K – Map simplification:

B3= G3 B2= G2 G3

B1= G1 G2 G3 B0= G0 G1 G2 G3


Bo

0000000

011111111

00 01 11 10

00

01

11

10

G1G0

G3G2

0000111

100001111

00 01 11 10

00

01

11

10

G1G0

G3G2

11

G1G0

G3G2 0011110

000111100

00 01 10

00

01

11

10

0101101001011010

00 01 11 10

00

01

11

10

G1G0

G3G2


Multiplexer 74153:


12 7

4153

3

4

5

6

7

8

1G

S1

1D3

1D2

1D1

1D0

1Y

GND

Vcc

2GS0

2D3

2D2

2D1

2D0

2Y

16

15

14

13

12

11

10

9


Truth Table:

Strobe(G) S1 S0 Y1 X X L0 0 0 D00 0 1 D10 1 0 D20 1 1 D3

Multiplexer using NAND gates only

Truth Table:

S1 S0 Y0 0 D00 1 D11 0 D21 1 D3

Experiment No. 8: Multiplexer


Y= D0+ S0D1+S1 D2+S1S0D3

S1 S0

D0

D1

D2

D3

Y


Aim: To realize and verify the truth table of multiplexer using IC 74153 and NAND

gates.

Apparatus required:

Procedure:

a) IC 74153:

1. The Pin [16] is connected to + Vcc.

2. Pin [8] is connected to ground.

3. The inputs are applied either to ‘A’ input or ‘B’ input.

4. If MUX ‘A’ has to be initialized, Ea is made low and if MUX ‘B’ has to be initialized,

Eb is made low.

5. Based on the selection lines one of the inputs will be selected at the output and thus the

truth table is verified.

b) NAND gates:

1. Connections are made as shown in the Circuit diagram.

2. Change the values of the inputs as per the truth table and note down the outputs

Theory:

In electronics, a multiplexer or mux is a device that performs multiplexing; it selects one

of many analog or digital input signals and forwards the selected input into a single line.

A multiplexer of 2n inputs has n select bits, which are used to select which input line to

send to the output. An electronic multiplexer can be considered as a multiple-input,

single-output switch. An electronic multiplexer makes it possible for several signals to

share one device or resource, for example one A/D converter or one communication line,

instead of having one device per input signal. An electronic multiplexer can be considered

as a multiple-input, single-output switch.

Demultiplexer 74139:


Sl no Particulars Range Quantity

1 IC 7400,7420,74153 1 2 each

2 IC 7410 2

12 7

4139

3

4

5

6

7

8

1G

1S0

1S1

1Y0

1Y1

1Y2

1Y3

GND

Vcc

2G2S0

2S1

2Y0

2Y1

2Y2

2Y3

16

15

14

13

12

11

10

9


Truth Table:

G S1(A) S0(B) Y0 Y1 Y2 Y31 X X 1 1 1 10 0 0 0 1 1 10 0 1 1 0 1 10 1 0 1 1 0 10 1 1 1 1 1 0

Demultiplexer using NAND gates only:

Truth Table:

Experiment No. 9: Demultiplexer


Select Lines OutputsA B Y0 Y1 Y2 Y30 0 0 1 1 10 1 1 0 1 11 0 1 1 0 11 1 1 1 1 0

A B

Y0

Y1

Y2

Y3

Y0= A+B

Y1= A+

Y2= +B

Y3= +


Aim: To realize and verify the truth table of demultiplexer using IC 74139 and NAND

gates.

Apparatus required:

Procedure:

1. IC 74139:

1. The inputs are applied to either ‘a’ input or ‘b’ input

2. The demux is activated by making Ea low and Eb low.

3. The truth table is verified.

2. NAND gates:

1. Connections are made as shown in the Circuit diagram.

2. Change the values of the inputs as per the truth table and note down the outputs

Theory:

In electronics, a demultiplexer (or demux) is a device taking a single input signal and

selecting one of many data-output-lines, which is connected to the single input. A

multiplexer is often used with a complementary demultiplexer on the receiving end. An

electronic demultiplexer can be considered as a single-input, multiple-output switch.

Half Adder using 74153



1 IC 7400,7420,74139 1 2 each

2 IC 7410 2


Full Adder using 74153

`

Experiment No. 10: Half/Full Adder Using IC 74153



Aim: To realize half Adder and Full Adder using IC 74153.

Apparatus required:

Procedure: (IC 74153)




4. In case of half adder using MUX, sum and carry is obtained by applying a constant

inputs at 1D0, 1D1, 1D2, 1D3 and 2D0, 2D1, 2D2 and 2D3 and the corresponding values

of select lines are changed as per table and the output is taken at 1Y as sum and 2Y as

carry.

5. In full adder using MUX, the input is applied at A, B and C. According to the table

corresponding outputs are taken at S and CY.

Half Subtractor using 74153


Sl No Particulars Quantity1 IC 74153,7404 1 Each


Full Subtractor using 74153

Experiment No. 12: Half/Full Subtractor Using IC 74153



Aim: To realize half Subtractor and Full Subtractor using IC 74153.

Apparatus required:

Procedure: (IC 74153)




4. In case of half Subtractor using MUX, difference and borrow is obtained by applying a

constant inputs at 1D0, 1D1, 1D2, 1D3 and 2D0, 2D1, 2D2 and 2D3 and the

corresponding values of select lines are changed as per table and the output is taken at 1Y

as difference and 2Y as borrow.

5. In full Subtractor using MUX, the input is applied at A, B and Bin. According to the

table corresponding outputs are taken at diff and borrow.

Circuit Diagram:





2A 2B

G2

01Y

1

1

1

74139Gnd

G0

B0

B1

2A 2B

G2

02Y

2

2

2

74139Gnd

G1

B2

1A 1B

G1

01Y

1

1

1

74139Gnd

G2

B3G3


Experiment no. 13: Binary To Gray Code Conversion Using 74139 Decoder

Aim: To perform the following code conversions using 74139 Decoder BCD to GRAY

code

Apparatus required:

Procedure:

1. Connections are made as shown in circuit diagram

2. Truth Table is verified for different combinations of input

Truth Table

Binary i/p Gray code o/pB3 B2 B1 B0 G3 G2 G1 G00 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 0 1 1 10 1 1 0 0 1 0 10 1 1 1 0 1 0 01 0 0 0 1 1 0 01 0 0 1 1 1 0 11 0 1 0 1 1 1 11 0 1 1 1 1 1 01 1 0 0 1 0 1 01 1 0 1 1 0 1 11 1 1 0 1 0 0 11 1 1 1 1 0 0 0



1 IC 74139.7400 1


a) One Bit Comparator using XOR Gate and Basic Gates

b) One Bit Comparator using NAND Gates

Truth Table:

Inputs Outputs A B AB

0 0 0 1 00 1 1 0 01 0 0 0 11 1 0 1 0

ABA


A

B

AB

A

B

A>B

A<B

A=B


Experiment No. 13: Comparators

Aim: To verify the truth table of one bit and two bit comparators using logic gates.

Apparatus Required:

Sl no Particulars Quantity1 IC 7400,7404,7408 2 each2 IC 7402,7432,7486 1 each

Procedure:

1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Applying inputs check for the corresponding outputs.

4. The Outputs are verified.



2-Bit Comparator:

Truth Table:

I/p O/pA1 A0 B1 B0 AB0 0 0 0 0 1 00 0 0 1 1 0 00 0 1 0 1 0 00 0 1 1 1 0 00 1 0 0 0 0 10 1 0 1 0 1 00 1 1 0 1 0 00 1 1 1 1 0 01 0 0 0 0 0 11 0 0 1 0 0 11 0 1 0 0 1 01 0 1 1 1 0 01 1 0 0 0 0 11 1 0 1 0 0 11 1 1 0 0 0 1



1 1 1 1 0 1 0

K-map Simplification:

1) AB


0111001100000010

00 01 11 10

00

01

11

10

B1B0

A1A0

1000010000100001

00 01 11 10

00

01

11

10

B1B0

A1A0

1

1

1

1

0000100011011100

00 01 11 10

00

01

11

10

B1B0

A1A0A<BB1B0+B1+B0

A=B(A1B1)( A0B0)

A>B((A<B)+(A=B))


4-Bit Comparator using IC 7485

Example: Let A= 1000 and B=1010 Here A3=1, A2=0, A1=0,A0=0 and B3=1, B2=0,B1=1, B0=0 Output: (A<B) is high, other two outputs are low

8-Bit Comparator using Two 7485:


(A=B)out

(A=B)in

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

B3

(A<B)in

(A>B)in

(A>B)out

(A<B)out

Gnd

Vcc

A3

B2

A2

A1

B1

A0

B0

VCC

IC7485


Experiment No. 14: Magnitude Comparator Using IC 7485

Aim: To compare two 4-Bit and 8-Bit data using IC 7485

Apparatus required:


1 IC 74851

Procedure:

1. Connections are made as shown in the circuit diagram

2. Supply voltage of 5 V is applied between Vcc and Gnd

3. The 3rd pin (A=B) in is Connected to Vcc

4. The 2nd and 4th pin (A>B)in and (A<B)in are connected to Gnd

5. Truth Table is verified for different combinations of input



Circuit Diagram of 7-Segment Display:

True table of BCD Seven Segment Decoder & displayINPUTS OUTPUTS

RB1 D C B A a b c d e f g Display

1 1 1 0 0 0 0 0 0 0 0 0 0 1

1 1 1 0 0 0 1 1 0 0 1 1 1 1

1 1 1 0 0 1 0 0 0 0 0 0 1 0

1 1 1 0 0 1 1 0 0 0 0 1 1 0

1 1 1 0 1 0 0 1 0 0 1 1 0 0

1 1 1 0 1 0 1 0 1 0 0 1 0 0

1 1 1 0 1 1 0 1 1 0 0 0 0 0

1 1 1 0 1 1 1 0 0 0 1 1 1 1

1 1 1 1 0 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 1 0 0 0 1 1 0 0

1 1 1 1 0 1 0 1 1 1 0 0 1 0

1 1 1 1 0 1 1 0 0 1 1 0 0 1

1 1 1 1 1 0 0 0 1 0 0 0 1 1

1 1 1 1 1 0 1 0 1 1 0 1 0 0



1 1 1 1 1 1 1 1 1 0 0 0 0 0

Experiment No. 15: Use of Decoder Chip to Drive LED Display

Aim: To conduct a suitable experiment to display the given data using 7-Segment LED decoder driver using IC 7447

Apparatus required:

Procedure:

1. Fix the IC into the IC base Board


3. Truth Table is verified for various input combinations.


Sl no Particulars Quantity1 IC 7447 1


Decimal to BCD conversion using IC 74147

Truth Table:

INPUTS OUTPUTS0 1 2 3 4 5 6 7 8 9 A3 A2 A1 A0H H H H H H H H H H H H H HX L H H H H H H H H H H H LX X L H H H H H H H H H L HX X X L H H H H H H H H L LX X X X L H H H H H H L H HX X X X X L H H H H H L H LX X X X X X L H H H H L L HX X X X X X X L H H H L L LX X X X X X X X L H L H H HX X X X X X X X X L L H H L


1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

A2

6

4

5

7

8

A1

Gnd

Vcc

0

A3

3

2

1

9

A0

IC74147


Experiment No. 16: Priority Encoder

Aim: Realize a suitable circuit to convert decimal to BCD using IC 74147

Apparatus required:

Sl No Particulars Quantity1 IC 74147 1

Procedure:

1. Connection are made as shown in circuit diagram.

2. Truth table is verified.

Theory:

A priority encoder is a combinational circuit with inputs and outputs. Each

of the inputs is assigned a priority. The most significant bit of the input has the

highest priority while the least significant bit has the lowest priority. The bits of the

output are the binary index of the non-zero input bit with highest priority, all input bits

with lower priority will be ignored. For example, when and , the behavior

of the priority encoder can be described as the following truth table:

Priority encoders are typically used when multiple components (e.g., processor, memory,

I/O devices, etc.) are to share a common resource (e.g., a bus). Each component is

Assigned a certain priority according to its nature, so that whenever there is a conflict, the

component with the highest priority will be granted the usage of the resource.



Circuit Diagram:

Truth Table:Mode Jn Kn Clock Qn+1 StatusAsync

hronous 0 1 X X 0 1 0 Set

1 0 X X 0 0 1 Reset

Synchronous

1 1 0 0 Qn No Change

1 1 0 1 0 1 Reset

1 1 1 0 1 0 Set

1 1 1 1 Qn Toggle

Experiment No. 17: Flip-Flops


Clr

PrJ

K

Q

Q

Master Slave

Clk


Aim: a) Rig up a Master Slave J-K Flip-Flop and verify its Truth Table. b) Rig up a T & D Flip-Flop using Master Slave J-K Flip-Flop and verify its Truth table

Apparatus required:

Sl No Particulars Quantity1 IC 7410 22 Ic 7400 1

Procedure:

1. Connections are made as shown in circuit diagram 1, 2 and 3.

2. Suitable truth tables are verified.

Theory:

In digital circuits, a flip-flop is a term referring to an electronic circuit (a bistable

multivibrator) that has two stable states and thereby is capable of serving as one bit of

memory.

Master-Slave JK Flip-flop

The Master-Slave Flip-Flop is basically two JK bistable flip-flops connected together in

a series configuration with the outputs from Q and Q from the "Slave" flip-flop being fed

back to the inputs of the "Master" with the outputs of the "Master" flip-flop being

connected to the two inputs of the "Slave" flip-flop as shown below.

Master-Slave JK Flip-Flops

The input signals J and K are connected to the "Master" flip-flop which "locks" the input

while the clock (Clk) input is high at logic level "1". As the clock input of the "Slave"

flip-flop is the inverse (complement) of the "Master" clock input, the outputs from the

D- FlipFlop:



Truth Table:

T Flip Flop:

Truth Table:


Dn Clock Qn+1 Status

1 1 0 0 1Reset

1 1 1 1 0Set

Tn Clock Qn+1 Status1 1 0 High Qn NC

1 1 1 High Qn Toggle

Q

Clr

Pr

Q

Master Slave

Clk

D

TPr

Q

Master Slave

Clk

Q

Clr


"Master" flip-flop are only seen by the "Slave" flip-flop when the clock input goes

"LOW" to logic level "0". Therefore on the "High-to-Low" transition of the clock pulse

the locked outputs of the "Master" flip-flop are fed through to the JK inputs of the "Slave"

flip-flop making this type of flip-flop edge or pulse-triggered.

Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data

to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK

Flip-flop is a "Synchronous" device as it only passes data with the timing of the clock

signal.

D-FlipFlop:

The D type flip-flop has only one input (D for Delay or Data) apart from the clock. The

INDETERMINATE state is avoided with this flip-flop. When the clock goes high, D (a 0

or a 1) is transferred to Q. When the clock goes low, Q remains unchanged. Q stores the

data until the clock goes high again, when new data may be available.

T-FlipFlop:

T(Toggle)-flip-flop toggles (Q changes state) when T is high. T acts as an ENABLE /

INHIBIT control.



Circuit Diagram of 3-Bit Asynchronous UP Counter:

Truth Table:

Wave Forms:


Clock QC QB QA0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 18 0 0 0

J Q

Clk

K

J Q

Clk

K

J Q

Clk

K

VccVcc

Clk

QA QB QC

Vcc

0

0

0

1

0

0

0

1

0

1

1

0

0

0

1

1

0

1

0

1

1

1

1

1

0

0

0

Clk

QA

QB

QC


Experiment No. 18: Asynchronous Up/Down Counter Using 7476

Aim: 1) Rig up a 3-bit Asynchronous UP counter.

2) Rig up a 3-bit Asynchronous DOWN counter.

3) Rig up a Mod N counter

Apparatus required:

Sl No Particulars Quantity

1 IC 7476 2

Procedure:

1. Connections are made as shown in circuit diagram.

2. Clock pulses are applied one by one at the clock i/p and the o/p is observed at QA,

QB and QC.

3. Truth table is verified.

4. Continuous clock pulses are applied.

5. Waveforms at QA, QB and QC are observed on CRO.

Theory:

In digital logic and computing, a counter is a device which stores (and sometimes

displays) the number of times a particular event or process has occurred, often in

relationship to a clock signal. In electronics, counters can be implemented quite easily

using register-type circuits such as the flip-flop, and a wide variety of designs exist,

Example:

Asynchronous (ripple) counter – changing state bits are used as clocks to

subsequent state flip-flops

Synchronous counter – all state bits change under control of a single clock

Result:

Truth Table is verified

Fclk=…………..

FQA=………….

FQB=………….

FQC=………….



Circuit Diagram: 3 Bit Asynchronous DOWN Counter

Truth Table:

Wave Forms:


Clock QC QB QA0 1 1 11 1 1 02 1 0 13 1 0 04 0 1 15 0 1 06 0 0 17 0 0 08 1 1 1

J Q

Clk

K

J Q

Clk

K

J Q

Clk

K

VccVcc

Clk

QA QB QC

Vcc

Clock

QA

QB

QC

1

1

1

0

1

1

1

0

1

0

0

1

1

1

0

0

1

0

1

0

0

0

0

0


Circuit Diagram: Mod 5 Counter

Truth Table:

Wave Forms:


Clock QC QB QA0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 0 0 0

J Q

Clk

K

J Q

Clk

K

J Q

Clk

K

VccVcc

Clk

QA QB QC

0

0

0

1

0

0

0

1

0

1

0

0

1

0

0

0

1 0

Clk

QA

QB

QC


Circuit Diagram: Mod 4 Down Counter:

Truth Table:

Waveforms:


Clock QC QB QA0 1 1 11 1 1 02 1 0 13 1 0 04 1 1 1

J Q

Clk

K

J Q

Clk

K

J Q

Clk

K

Vcc

Clk

QA QB QC

Clock

QA

QB

QC

1

1

1

0

1

1

1

0

1

0

0

1

1

1

0

0

1

0

1

0

0

0

0

01

Vcc




Circuit Diagram: Decade Counter 7490

Mode 8 Counter using 7490


5 12 9 8 11

14

10 1 2 3 6 7

Mod 2 Mod5

QA QA QB QCVcc

I/p A

Clk

I/p B R1 R2 S1 S2

I/p B

5 12 9 8 11

14

10 1 2 3 6 7

Mod 2 Mod5

QA QA QB QCVcc

I/p A

Clk

R1 R2 S1 S2


Experiment No. 19: Counter

Aim: Rig up Mod N Counter using 7490

Apparatus:

Sl No Particulars Quantity1 IC 7490 1 No

Procedure:


2. Clock pulses are applied one by one at the i/p and the o/p is observed at QA, QB

QC and QD.

3. Truth Table is verified.

4. Continuous clock pulses are applied.

5. Waveforms QA, , QB QC and QD are observed on CRO.

Result:

1) Fclk=……………………………..

2) FQA=……………………………

3) FQB=…………………………….

4) FQC=…………………………….

5) FQD=……………………………..



Truth Table:

Decade Counter Mod 8 Counter

Waveforms for Mod 10 Counter:

Waveforms for Mod 8Counter:


Clock QD QC QB QA0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 110 0 0 0 0

Clock QD QC QB QA0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 0 0 0 0

0

0

0

0

1

0

0

0

0

1

0

0

1

1

0

0

0

0

1

0

1

0

1

0

0

1

1

0

1

1

1

0

0

0

0

1

1

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

1

1

0

0

0

0

1

0

1

0

1

0

0

1

1

0

1

1

1

0

0

0

0

0

Clk

QA

QB

QC

QD


Circuit Diagram: Count from 3 to 8



Preset Value=3, N=6

Truth Table:


Clock QD QC QB QA0 0 0 1 11 0 1 0 02 0 1 0 13 0 1 1 04 0 1 1 15 1 0 0 06 0 0 1 1

NC NC

Vcc QD QC QB QA

Count up

Count Down

8Clear DATA I/P

D C B A

Clki/p

Vcc

(0 0 1 1)=3

16 7 6 2 3

5

4

14

13 12 9 10 1 15

11

74193


Experiment No. 20: Programmable 4 Bit Synchronous Up/Down Counter (Binary Counter)

Aim: Rig up a MOD N Synchronous Up/Down Counter using 74193 & 74192

Apparatus required:

Procedure:

1) Connections are made as shown in the circuit diagram with the load pin open

2) The Preset value is made available at the data inputs C,B and A.

3) The Load pin is made low so that the preset value appears at QD, QC, QB and QA

4) Now connect the o/p of the gate to the load i/p.

5) Clock pulses are applied and the truth table is verified.

6) Continuous clock pulses are applied.


Sl No Particulars Quantity

1 IC 74193,7400.7432 1



Preset value=12, N=8

Truth Table:


Clock QD QC QB QA0 1 1 0 01 1 0 1 12 1 0 1 03 1 0 0 14 1 0 0 05 0 1 1 16 0 1 1 07 0 1 0 15 1 1 0 0

NC NC

Vcc QD QC QB QA

Count up

Count Down

8Clear DATA I/P

D C B A

Vcc

Clk

(1 1 0 0)=12

16 7 6 2 3

5

4

14

13 12 9 10 1 15

1174193



Preset Value=5, N=4

Truth Table:


Clock QD QC QB QA1 0 1 0 12 0 1 1 03 0 1 1 14 1 0 0 05 0 1 0 1

NC NC

Vcc QD QC QB QA

Count up

Count Down

8Clear DATA I/P

D C B A

Clki/p

Vcc

(0 1 0 1)=5

16 7 6 2 3

5

4

14

13 12 9 10 1 15

11

74192



Preset value=8, N=6

Truth Table:


Clock QD QC QB QA0 1 1 0 01 1 0 1 12 1 0 1 03 1 0 0 14 1 0 0 05 0 1 1 16 0 1 1 07 0 1 0 15 1 1 0 0

NC NC

Vcc QD QC QB QA

Count up

Count Down

8Clear DATA I/P

D C B A

Vcc

Clk

(1 0 0 0)=8

16 7 6 2 3

5

4

14

13 12 9 10 1 15

1174192




Circuit Diagram of 3-Bit synchronous Counter:

Truth Table:

Wave Forms:


Clock QC QB QA0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 1

0

0

0

1

0

0

0

1

0

1

1

0

0

0

1

1

0

1

0

1

1

1

1

1

0

0

0

Clk

QA

QB

QC

JA QA

Clk

KA A

JB QB

Clk

KB B

JC QC

Clk

K C C

Clk

Vcc

Vcc

VccQA

QBQC


Experiment No. 21: 3 BIT SYNCHRONOUS COUNTER

Aim: 1) To design and test a 3 bit synchronous counter using 7476

Apparatus:


Procedure:


2. Clock pulses are applied one by one at the clock i/p and the o/p is observed at QA,

QB and QC.

3. Truth table is verified

4. Continuous clock pulse are applied.

5. Waveforms at QA, QB and QC are observed on CRO

Result:

Truth Table is verified

1) Fclk=…………..

2) FQA= =………….………….

3) FQB= =………….………….

4) FQC= =……………………..



State Diagram:

Excitation Table:

Transition Table:

Present State Next StateJC KC JB KB JA KA

QC QB QA QC QB QA

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 1 1 0 X 0 1 X X 1

1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 0 0 0 X 1 X 1 X 1


State Change J-K Input

From To J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

000

001

111

110

101

100

010

011


Karnaugh Map to derive the flipflop input function:

JA: KA:


1XX11XX1JA=1

00 01 11 10

0

1

QAQB

QC

X11XX11XKA=1

00 01 11 10

0

1

QAQB

QC

01XX01XXJB=QA

00 01 11 10

0

1

QAQB

QC

XX10XX10KB=QA

00 01 11 10

0

1

QAQB

QC

0010XXXXJC=QB.QA

00 01 11 10

0

1

QAQB

QC

XXXX0010KC=QB.QA

00 01 11 10

0

1

QAQB

QC


Circuit Diagram for serial in serial Out (SISO): vcc

1

6

13 12 11 10 7

Truth Table:

Clock Serial QA QB QC QD

1 DO = 0 0 X X X

2 D1 = 1 1 0 X X

3 D2 = 1 1 1 0 X

4 D3 = 1 1 1 1 0 = D0

5 X X 1 1 1 = D1

6 X X X 1 1 = D2

7 X X X X 1 = D3

Circuit Diagram for serial in serial Out (SIPO/Right Shift): vcc

1

6

13 12 11 10 7


Serial Input

Clock M=0

QA QB QC QD

7495

14

9

7495

Serial Input

Clock M=0

QA QB QC QD

14

9


Experiment No. 22: SHIFT REGISTERS

Aim: To conduct an experiment to perform the following operations on a given 4 bit data

using IC 7495.

i. SISO, ii. Right shift/SIPO, iii. PIPO, iv. PISO, v. left shift , vi, Ring counter

Procedure:

i) Serial In Serial Out: (SISO)

1. Connection is made as shown in the circuit diagram.

2. The shift register is loaded with 4 bits of data one by one serially.

3. At the end of the 4th clock pulse the first data ‘do’ appears at QD.

4. Another clock pulse is applied; the second data ‘d1’ appears at QD.

5. Another clock pulse is applied; the third data ‘d2’ appears at QD.

6. Application of next clock pulse will enable the fourth data ‘d3’ to appear at QD.

Thus the data applied serially at the input comes out serially at QD.

ii) Right shift/Serial In Parallel Out (SIPO):

1. Connections are made as shown in the circuit diagram.

2. The data is applied at the serial input.

3. One clock pulse is applied at 1 (Right shift) and this data is observed at QA.

4. The next data is applied at serial input.

5. One more clock pulse is applied at clock 1 and it is observed that the data on QA

will shift to QB and the new data applied will appear at QA.

6. Step 2 and 3 are repeated till all the 4 bits of data are entered one by one into the

shift register.



Truth Table for SIPO:

Clock Serial Data QA QB QC QD

1 DO = 0 0 X X X

2 D1 = 1 1 0 X X

3 D2 = 1 1 1 0 X

4 D3 = 1 1 1 1 0 = D0

Circuit diagram for Parallel in Parallel Out: (PIPO)

vcc

6

13 12 11 10 7

Truth Table for PIPO:

Mode Clock Parallel data input Parallel data output

A B C D QA QB QC QD

1 1 1 0 1 1 1 0 1 1

Circuit diagram for Parallel in Parallel Out: (PISO)

vcc

6

13 12 11 10 7

iii) Parallel in serial Out: (PIPO):


QA

QB QC QD

8

7495Clock M=1

14

A B C D

2 3 4 5

QA

QA

QB QC QD

8

7495Clock M=

14

A B C D

2 3 4 5

QA

9

Mode=1 for Parallel loadingMode=0 for serial shifting



2. The 4 bit data is applied at A, B, C & D.

3. Keeping the Mode control M =1, one clock pulse is applied. The data

applied at A, B, C & D will appear at QA, QB, QC, & QD respectively.

iv) Parallel in serial Out: (PISO):


2. The 4 bit data is applied at A, B, C & D.

3. Keeping the Mode control M =1, one clock pulse is applied. The data

applied at A, B, C & D will appear at QA, QB, QC, & QD respectively.

4. Keeping the Mode control M = 0, clock pulse are applied one by one and

data arriving out serially at QD is observed.

Note: Mode = 1 for Parallel loading.

Mode = 0 for serial shifting.

v) Procedure for Left shift:


2. Apply the first data at D and apply one clock pulse. This data appears at QD.

3. Now the 2nd data is made available at D and one clock pulse is applied. The data

appears at QD to QC and new data appears at QD.

1. Step 3 is repeated until all the bits are entered one by one.

2. At the end of 4th clock pulse 4 bits are available at QA, QB, QC and QD.

.

Truth Table for PISO:



Mode Clock Parallel data input Parallel data output

A B C D QA QB QC QD

1 1 1 0 1 1 1 0 1 1

0 2 X X X X X 1 0 1

0 3 X X X X X X 1 0

0 4 X X X X X X X 1

Data comes out serially at QD.

Circuit diagram for Left Shift :

Note: Give Pin No.7 to Ground and Pin No.14 to Vcc.

Truth Table for Left Shift:

Mode Clock Serial data

input

Parallel data output

QA QB QC QD

1 1 1 X X X 1

1 2 0 X X 1 0

1 3 1 X 1 0 1

1 4 1 1 0 1 1

vii) Ring Counter:


Clock 1 13121110

8

6 2345M=1

ABCD

QAQBQCQD

7495

9

Serial I/P



2. The data 1 0 0 0 is applied at A B C D respectively.

3. Keeping the mode M = 1, one clock pulse is applied.

4. Keeping the mode M = 0, one clock pulse are applied one by one and truth table is

verified.

Circuit diagram for Ring Counter:

Truth Table:

Mode Clock QA QB QC QD

1 1 1 0 0 0

0 2 0 1 0 0

0 3 0 0 1 0

0 4 0 0 0 1

0 5 1 0 0 0

0 6 Repeated

Basic Structure of a Sequence Generator:


13121110

8

6 2345

BCCD

QAQBQCQD

7495 1

9Clock 1

M

Serial I/P

NEXT STATE DECODER

QN-1 QN-2 Q1 Q0

SHIFT REGISTERClk

Serial i/p


Sequence=1001011, Sequence Length=7

QA QB QC QD Y1 1 1 1 0

0 1 1 1 00 0 1 1 11 0 0 1 00 1 0 0 11 0 1 0 11 1 0 1 1

1 1 01 1

1 Y= QB QC

Experiment No. 23: SEQUENCE GENERATOR

Aim: Design of a sequence Generator using IC 7495


13 12 11 106 14

8 7

9 1 2 3 4 5

Vcc=5V

Clock

Mode

QA QB QC QD

A B C D

Inputs

7495

Serial i/p

XX1X1X0XX1X0X0X1

00 01 11 10

00

01

11

10

QcQD

QAQB


Procedure:

1) Make connections as per the cicuit diagram

2) By keeping the mode=1. Load the input through A,B,C,D as 1111 by giving one

clock pulse

3) For count mode make mode=0

And observe the sequence at QA,QB,QC and QD.

Additional Experiment

A combinational logic circuit has TWO control inputs C1, C2 and Two data inputs A , B and one output Y. the circuit performs one of the logic operations AND,



OR,EQU(equivalence) or XOR(exclusive or) on the two inputs. The function performed depends on the control inputs,

C! C2 Function performedBy circuit

0 0 OR0 1 XOR1 0 AND1 1 EQU

Design the Circuit with minimum number of Gates.

Solution: Procedure to be followed to design the required circuit.

1. Get the truth table.2. Get switching equation from the truth table.3. Simplify the switching equation using K-map.4. Realize the simplified equation using basic gates.



APPENDIX A

PIN DETAILS:







APPENDIX B

VIVA QUESTIONS:



1. What are Analog Systems? Give Examples.

2. What are Digital Systems? Give Examples.

3. Mention the disadvantages of Analog systems over Digital systems?

4. Explain Boolean Algebra?

5. State Principle of Duality?

6. State Demorgans Law?

7. Define Positive Logic and Negative Logic.

8. Define Literal.

9. Define MINTERM, MAX TERM.

10. Define a complementary function

11. Explain Shannon’s reduction theorem

12. Which are the basic gates, universal gates

13. Define combinational network with example

14. Define Sequential Network with example

15. Define Double-Rail and Single -Rail logic

16. When a Boolean Expression is called completely specified?

17. Explain the significance of a Don’t care function

18. Explain the criteria of minimality.

19. Define implies, Subsumes, implicants.

20. What are Prime Implicants?

21. What is irredundant disjunctive normal formula?

22. What is an implicate?

23. What is a MAP?

24. Explain the significance of Map

25. What is a minimal Sum, Minimal product?

26. Explain Quine mccluskey method

27. Explain VEM method of reduction

28. Explain Binary Adder, Subtractor

29. Explain various scales of integration

30. Define carry look ahead Adder

31. Define Comparator

32. Define Decoder

33. Define Encoder



34. Give an example for Min term generator

35. Give an example for Max term generator

36. Define priority encoder

37. Explain Multiplexing action

38. Define PAL, PLA and PROM

39. Differentiate between ROM and RAM

40. What is a Memory?

41. What is internal state and secondary state?

42. What is Flip Flop, Latch

43. Explain Basic Bi stable element

44. What is a meta stable state?

45. Define setting and clearing in terms of flip-flop

46. Explain SR Latch

47. Give an application of SR Latch

48. Explain gated SR Latch, gated D Latch

49. Explain Timing Diagram

50. Explain Propagation Delay in gates

51. Explain set and hold time in latches

52. Explain Master-Slave Flip-Flops

53. Explain the significance of edge-triggering

54. Explain Data Lock Out

55. Give the characteristic equations of JK, D and T Flip Flops.

56. Define Registers with examples

57. Define Counters with example

58. Explain ripple counter, asynchronous , synchronous counter

59. Explain Race around condition

60. List the basic logic series

61. Explain Semiconductor diode behavior.

62. What is saturating Logic?

63. Explain Fan-Out and Fan-in in gates

Question Bank



1. Simplify and realize the given Boolean Expression using Basic Logic gates and verify the truth table ( two expressions to be given)

2. Simplify and realize the given Boolean Expression using Universal Gates and verify the truth table ( two expressions to be given)

3. Realise and verify the truth table of a full adder and half adder using XOR and basic gates

4. Realise and verify the truth table of a full Subtractor and Half Subtarctor using XOR and basic gates

5. Realise and verify the truth table of a full adder and half adder using NAND gates only

6. Realise and verify the truth table of a full subtractor and half subtractor using NAND gates only

7. Conduct a suitable experiment on 7483 IC to realize the following operation on the given 4 bit data a) Addition b) 2’s Complement subtraction

8. Conduct an experiment to convert the given BCD data to excess-3 code using minimum number of basic gates

9. Conduct an experiment to convert the given excess-3 data to BCD using minimum number of basic gates

10. Realise using XOR gates and verify the truth table of11. a) Binary to gray converter b) Gray to Binary Converter (use basic gates)

12. Realise using XOR gates and verify the truth table ofa) Binary to gray converter (use NAND gates only)

13. Realise using XOR gates and verify the truth table of14. a) Gray to Binary Converter (use NAND gates only)

15. Conduct an experiment to verify the TT of IC 74153 Mux and realize a Half/full 16. adder circuit

17. Conduct an experiment to verify the TT of IC 74153 Mux and realize a Half/full subtractor circuit

18. Conduct an experiment to verify the TT of IC 74139 decoder and realize a Binary to gray code converter

19. Realize a two bit comparator using basic gates only

20. Realize a two bit comparator using NAND gates only

21. Realize a 8 Bit comparator using IC 7485



22. Conduct a suitable experiment to display the given data using 7-segment LED Decoder

23. Verify the truth table of a given Priority encoder(IC 74147)

24. Realise and verify the truth Table of Master Slave JK Flip Flop using NAND gates

25. Realise and verify the truth Table of Master Slave D Flip Flop using NAND gates

26. Realise and verify the truth Table of Master Slave T Flip Flop using NAND gates

27. Realise a 3-bit binary asynchronous up counter using IC 7476 (N<=7) and verify its truth table

28. Realise a 3-bit binary asynchronous down counter using IC 7476 (N<=7) and verify its truth table

29. Realise a Mod N binary synchronous counter using 7476 and verify the truth table

30. Realise a Modulo N counter using 7490, Write down the expected functional table and verify its truth table and also display the waveform.

31. Realise a Modulo N counter using 74192 with a given preset value and verify its truth table (N, preset value to be specified N<=10). Display the waveform

32. Realise a Modulo N counter using 74193 with a given preset value and verify its truth table (N, preset value to be specified N<=15). Display the waveform

33. Use IC 7495 Shift registers to display the following operations

34. a) SIPO b) SISO c) PIPO

35. Use IC 7495 Shift registers to display the following operations

36. a) Shift Left b) Right Shift c) Ring Count

37. Design and realize a sequence generator for the sequence……………………….

Documents

LD Lab Manual 2011 Final