LatchesCS370 –Spring 2003

Section 4-2 Mano & Kime

Sequential Logic

• Combinational Logic– Output depends only on current input

• Sequential Logic– Output depends not only on current input but

also on past input values– Need some type of memory to remember the

past input values

Circuits that wehave learnedso far

Information StoringCircuits

Timed “States”

Storing Information

Buffers Inverters

Can’t change the stored value!

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q1

1

0

1 0 1

0 0 10 1 11 0 11 1 0

X Y nand

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q0

1

0

1 0 1

0 0 10 1 11 0 11 1 0

X Y nand

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q0

1

1

1 0 1

0 0 10 1 11 0 11 1 0

X Y nand

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q0

1

1

0 0 1

0 0 10 1 11 0 11 1 0

X Y nand

1 0 Set

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q1

1

1

0 0 1

0 0 10 1 11 0 11 1 0

X Y nand

1 0 Set

1 0 Store

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q1

0

1

0 0 1

0 0 10 1 11 0 11 1 0

X Y nand

1 0 Set

1 0 Store

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q1

0

1

1 0 1

0 0 10 1 11 0 11 1 0

X Y nand

1 0 Set

1 0 Store

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q1

0

0

1 0 1

0 0 10 1 11 0 11 1 0

X Y nand

1 0 Set

1 0 Store

0 1 Reset

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q1

1

0

1 0 1

0 0 10 1 11 0 11 1 0

X Y nand

1 0 Set

1 0 Store

0 1 Reset

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q0

0

1

1 0 1

0 0 10 1 11 0 11 1 0

X Y nand

1 0 Set

1 0 Store

0 1 Reset

1 1 Disallowed

Q0 !Q0

!S-!R Latch

!S

!R

Q

!Q

0 00 11 01 1

!S !R Q !Q1

1

0

1 0 1

0 0 10 1 11 0 11 1 0

X Y nand

1 0 Set

1 0 Store

0 1 Reset

1 1 Disallowed

Q0 !Q0

S-R Latches

S-R Latch Simulation

S - R Latch with a Clock Signal (Sequential)

S-R Latch!S

!R

Q

!Q

S

R

CLK

S R CLK !S !R Q !Q

0 0 1 1 1 Q0 !Q0 Store 0 1 1 1 0 0 1 Reset1 0 1 0 1 1 0 Set1 1 1 0 0 1 1 DisallowedX X 0 1 1 Q0 !Q0 Store

D Latch

Q

!Q

CLK

D !S

!R

S

R S R CLK Q !Q

0 0 1 Q0 !Q0 Store 0 1 1 0 1 Reset1 0 1 1 0 Set1 1 1 1 1 DisallowedX X 0 Q0 !Q0 Store

0 1 0 11 1 1 0X 0 Q0 !Q0

D CLK Q !Q

D Latch

Q

!Q

CLK

D !S

!R

S

R

0 1 0 11 1 1 0X 0 Q0 !Q0

D CLK Q !Q Note that Q follows Dwhen the clock in high,and is latched when theclock goes to zero.

D Latch

CLK

D Q

E

x

y

CLK

z x

y

z

Does NOT latch z = z $ x = 0 $ 1 = 1

Latches on following edge of clock

D Latch

CLK

D Q

E

x

y

CLK

z x

y

z

Does latch z = z $ x = 0 $ 1 = 1

Use narrow pulse

If x remains high, successive clock pulses will toggle z

D Latch with Transmission Gates

D Flip-Flop

0 1 0 11 1 1 0X 0 Q0 !Q0

D NCK Q !Q

Q

!Q

D !S

!R

S

R

CLK

Pulse-narrowingcircuit NCK

0 0 11 1 0X 0 Q0 !Q0

D CLK Q !Q

Pulse-Narrowing CircuitX Y

Z

X

Y

X & Y

Z

D Flip-Flop

CLK

D Q

!Q0 0 11 1 0X 0 Q0 !Q0

D CLK Q !Q

D gets latched to Q on the rising edge of the clock.

Positive edge triggered

D Flip-Flop

CLK

D Q

!Qy

CLK

z

pulse width

setuptime

hold time

propagationdelay

SR Master-Slave Flip-Flop

S R CLK Q !Q

0 0 1 Q0 !Q0 Store 0 1 1 0 1 Reset1 0 1 1 0 Set1 1 1 1 1 DisallowedX X 0 Q0 !Q0 Store

Q

!Q

CLK

J

K

CLK

K

Q

!Q

J

J-K Flip-Flop

J K CLK Q !Q

0 0 Q0 !Q0

0 1 0 11 0 1 01 1 ToggleX X 0 Q0 !Q0