LandTiger V2.0 LPC17XX Development Board - Arm Mbed · PDF fileLandTiger V2.0 User Manual 2 1 Overview The LandTiger V2.0 NXP LPC1768 ARM development board is based on a second-generation

LandTiger V2.0

LPC17XX Development Board

User Manual Version V1.0

www.PowerMCU.com www.PowerAVR.com

Copyright @ 2009, WH 2012

LandTiger V2.0 User Manual 2

1 Overview The LandTiger V2.0 NXP LPC1768 ARM development board is based on a second-generation ARM Cortex-M3 microcontroller, a high-performance, low-power 32-bit microprocessor designed for embedded system applications, suitable for instrumentation, industrial communications, motor control, lighting control, alarm systems, and other fields. The board supports USB2.0 Device and Host, dual CAN interfaces, RS-485 interface and an on-board USB emulator for JLINK. The development board is supported by a rich set of example software and detailed information to facilitate the users to quickly project development. A short feature overview: Powerful LPC1768 MCU Cortex-M3 core:

Clock frequency up to 100MHz. Includes support of eight areas of memory protection unit (MPU). Built-in Nested Vectored Interrupt Controller (NVIC). 512KB on-chip Flash program memory, supports in-system programming (ISP) and In

Application Programming (IAP). 64KB SRAM for high-performance CPU access through the instruction bus, system

bus, data bus access. AHB multi-layer matrix with 8-channel general-purpose DMA controller (GPDMA). Supports SSP, UART, I2C, I2S, ADC, DAC, Timer, PWM, GPIO, etc., can be used

for memory-to-memory transfer. Standard JTAG test / debug interface and a serial wire debugging and serial wire

tracking port option. Simulation trace module supports real-time tracking. 4 low-power modes: sleep, deep sleep, power-down, deep power-down. Single 3.3V power supply (2.4V - 3.6V). Operating temperature: -40° C - 85° C. Non-maskable interrupt (NMI) input. On-chip integrated power-on reset circuit. Built-in systems timer (SysTick), to facilitate operating system migration.

Onboard resources:

2 RS232 serial interfaces (using straight-through serial cable), (RS232 Transceiver: SP3232). One serial port supports ISP download of programs.

2 CAN bus communication interfaces (CAN Transceiver: SN65VHD230). RS485 communication interface (485 Transceiver: SP3485). RJ45-10/100M Ethernet network interface (Ethernet PHY: DP83848). DAC output interface, on-board speaker and speaker output driver (LM386). ADC input interface, on-board adjustable potentiometer input. Color LCD display interface (supports 2.8-inch or 3.2-inch color TFT 320X240).

Touchscreen supported through SPI interface. USB2.0 Interface, USB host and USB Device interface. SD/MMC card (SPI) interface. I2C Interface, connected to onboard 2Kbit EEPROM (24LC02). SPI serial interface connected to onboard 16Mbit Flash (AT45DB161D). 2 user keys, 2 function keys (INT0 and Reset button). 8 LED lights (Digital outputs).


Five-way joystick button (Digital Inputs). Serial ISP download support (COM0). Standard JTAG download, simulation debugging interface. Integrated JLINK compatible emulator (USB): support online simulation and debug

capabilities, support KEIL, IAR and other mainstream development environments. Optional external 5V power supply or USB input to provide 5V power supply. Breakout available for all the IOs, user-friendly connection of external application

development circuits.

Figure 1 Board Overview (Note: Picture shows version 1.0 of the board)


2 Circuit and interface description Due to the limited space in this manual, please use the circuit schematic reference for additional details on ICs and specific functions.

2.1 Power supply The LandTiger development board may be powered by an external 5V power input or by the USB debug interface 5V power input.

5V DC power adapter connected to CN9, power select jumper J3 plugged into 1-2 selects the external 5V power supply.

Connecting the PC USB cable to the USB debug port CN4 and power select jumper J3 plugged into 2-3 will choose USB 5V supply. The board will be powered by the PC USB port (maximum current of 500mA limit).

Tabel 1 Jumper settings for powersupply select

Jumper Description J3 J3 is used to select the external 5V power supply or

USB powersupply. External 5V power supply: Jumper short1-2 USB-powered: Jumper short 2-3

Figuur 2 Powersupply Jumper J3, connector CN9 and main powerswitch

Main powersupply switch SW6 is provided to switch the board on or off. LED LD11 indicates when the board is powered.


Note1: CN9 powerconnector inner pin is positive, outer ring is negative. The input voltage must not exceed 5V ± 5%. Plug dimensions: 5mm outside, 2.5mm inside.

Figuur 3 External 5V powersupply connector CN 9

Note2: The USB Device port (CN12) can not be used to power the LandTiger board. Note3: insert JP1 jumper to connect the onboard battery to the RTC when the board is disconnected from the external powersupply, when JP1 is open the RTC will only run as long as power is supplied and not maintain time when switched off. Tabel 2 Jumper settings for RTC powersupply

Jumper Description J1 J1 is used to connect onboard backup battery to the

RTC. Battery backup: Jumper inserted No battery backup: Jumper removed

Figuur 4 RTC Battery Jumper J1 and batteryholder BT1

2.2 Clock source The development board has four different clock sources: System clock, Realtime Clock (RTC clock), Ethernet clock and Debugger interface clock.

Y1, 12 MHz crystal, is the main system clock source, the internal RC oscillator of the CPU can not be used.

Y2, 32.768 kHz crystal, is the clock source for the RTC. U4, 50MHZ crystal, is the Ethernet PHY chip DP83848 clock. Y3, 8 MHz is the clock for the JLink Debugger interface


Note 1: See section 2.1 on powersupply and onboard battery backup for the RTC.

2.3 Reset Mode The reset signal in the Land Tiger LPC17XX development board is active low reset. The reset modes include the following:

Press Reset button Reset (SW1) Reset signal is input through the JTAG emulator download. Reset signal is input through the ISP COM1 port (DTR control).

2.4 Analog Input (ADC) Adjustable potentiometer VR1 is connected to analog channel P1.31 (AD0.5). JP12 jumper is used to enable the potmeter input. VR1 setting provides input voltages between 0V and 3V3 to the ADC. Tabel 3 Jumper setting for Analog Input

Jumper Description J12 J12 is used to enable the VR1 connection to ADC

input (P1.31 AD0.5). VR1 Connected to AD.05: Jumper short No ADC input: Jumper removed

Figuur 5 ADC Potmeter and Jumper J12


2.5 Digital Analog Conversion Output （DAC) External speaker circuit is connected to DAC output pin P0.26. The DAC output is enabled by JP2 jumper. The speaker is driven by an onboard audio amplifier U2 (LM386). Tabel 4 Jumper setting for DAC output

Jumper Description J2 J2 is used to enable the external speaker.

Speaker connected to P0.26: Jumper short No Speaker output: Jumper removed

Figuur 6 Loudspeaker and Jumper J2

2.6 USB-Host LandTiger LPC17XX development board provides a full-speed USB 2.0 Host port (CN11), through a standard USB-A Type connector. The USB host port may be used to connect USB peripherals, such as: USB disk, USB mouse, USB keyboard and other equipment. Set JP9, JP11 jumpers into 3-4 position for the USB Host interface.

Jumper Description JP9 Select USB-D +.

USB host: JP9 set to 3-4

Jumper Description JP11 Select USB-D -.

USB host: JP11 set to 3-4

Connected devices should be provided with 5V power. This power is activated under controlled of the user program. Note that maximum current is limited.


IO Pin Description P1.19 Activate USB Host power.

LED LD15 is lit when power is activated. USB power control by P1.19: control signal is active low.

Tabel 5 The LPC1768 reserves a number of pins for the USB Host functions.

IO Pin Description P0.29 USB_D+

Connected to either the Host or Device connector by JP9

P0.30 USB D- Connected to either the Host or Device connector by JP11

P1.22 Sense USB Host power state. USB powersense by P1.22: input signal is active high.

P1.19 Activate USB Host power. LED LD15 is lit when power is activated. USB power control by P1.19: control signal is active low.

Tabel 6 CN11 USB AB-type pin functions

Pin Description Typical wire colour 1 VBUS (5V) Red 2 D- White 3 D+ Green 4 GND Black

Note: The figure shows a front view of the socket (left) and the plug is facing you.

Figuur 7 USB AB Host Connector CN11 (left) and Plug (right)


Figuur 8 USB Jumpers and LEDs

2.7 USB-Device The Land Tiger LPC17XX development board provides a full-speed USB 2.0 device port (CN12), through a standard USB-B Type connector. Set JP9, JP11 jumper Plugged into 1-2 position for the USB Device interface.

Jumper Description JP9 Select USB-D +.

USB device: JP9 set to 1-2

Jumper Description JP11 Select USB-D -.

USB device: JP11 set to 1-2

The D+ line may have a pull-up activated to signal high-speed mode. This pull-up may either be permanent or controlled by software.

Jumper Description JP10 Select USB-D + signal pull-up resistor mode.

LED LD14 is lit when the pull-up is activated. USB pull-up control by P2.9: JP10 set to 1-2 (P2.9 control signal is active low).


USB permanent pull-up: JP10 set to 2-3

IO Pin Description P2.9 Activate USB Device pull-up.

LED LD14 is lit when the pull-up is activated. USB pull-up control by P2.9: JP10 set to 1-2 (P2.9 control signal is active low).

Tabel 7 LPC1768 reserved pins for the USB Device functions.

IO Pin Description P0.29 USB_D+

Connected to either the Host or Device connector by JP9

P0.30 USB D- Connected to either the Host or Device connector by JP11

P1.30 Sense VBUS from host in USB- Device mode. VBUS is active high.

P1.18 USB Device is up indicator. LED LD13 is lit when USB is activated. (active low)

P2.9 Activate USB Device pull-up. LED LD14 is lit when the pull-up is activated. USB pull-up control by P2.9: JP10 set to 1-2 (P2.9 control signal is active low).

Tabel 8 CN12 USB B-type pin functions

Pin Description Typical wire color 1 VBUS (5V) Red 2 D- White 3 D+ Green 4 GND Black

The figure below shows a front view of the socket (left), the plug (right) is facing you.


Figuur 9 USB B Device Connector CN12 (left) and Plug (right)

Note1: The USB Device port (CN12) can not be used to power the LandTiger board. Power must be supplied either by the external power connector or by the the USB debug port.

2.8 Databus Interface The ARM LPC1768 does not have a separate data, address and controlbus. The LandTiger board is designed to emulate a simple processorbus by using some of the regular port pins. Port pins P2.0 ... P2.7 represent an 8 bit databus. The datalines are connected to an 8bit - 16bit conversion circuitry provided by U8 and U9. A number of controllines are also available that provide RD*, WR*, CS* and RS*. The main use for the bus is to control an LCD display. However, the design is generic and may be used to control other peripheral hardware also.

2.8.1 LED Interface The 8 data lines P2.0-P2.7 are directly connected to a 74LV244 driver (U11) followed by 8 red LEDs (LD4 ... LD11). The LEDs display the current bitpattern on the databus. The LEDs may be disabled by removing J8.

Jumper Description J8 Enable databus LEDs.

LEDs enabled: JP8 inserted LEDs disabled: JP8 removed

Note that the datalines are shared with the LCD and the LEDs will show any databus activity to the LCD.

Figuur 10 LEDs and Enable Jumper J8


2.8.2 Conversion Circuit 8bit-16bit The datalines are connected to an 8bit - 16bit conversion circuitry provided by U8 (16bit bidirectional buffer, 74ALVC164245) and U9 (8bit latch, 74LV573). The tables below show the steps needed to use the 8-16 bit conversion circuitry for Read and Write operations. There are 3 specific controllines required for the 8-16 bit conversion unit: LCD_DIR, LCD_EN, LCD_LE. Tabel 9 Write operation sequence for 16 bit Databus

Steps Control/datapin IO Pin Set P2.0-P2.7 as Output Set Buffer Direction to WR

LCD_DIR=1 P0.21

Enable buffer outputs LCD_EN=0 P019 Latch D00-D07 Transparant LCD_LE=1 P0.20 Setup D00-D07 Write LSBs P2.0-P2.7 Latch D00-D07 LCD_LE=0 P0.20 Setup D08-D15 Write MSBs P2.0-P2.7 Select Device LCD_CS=0 P0.22 Select Data/Control Reg LCD_RS=X P0.23 Write Data LCD_WR=0, 1 P0.24 Deselect Device LCD_CS=1 P0.22 …

Tabel 10 Read operation sequence for 16 bit Databus

Steps Control/datapin IO Pin Set P2.0-P2.7 as Input Set Buffer Direction to RD

LCD_DIR=0 P0.21

Enable MSB buffer outputs LCD_EN=0 P019 Select Device LCD_CS=0 P0.22 Select Data/Control Reg LCD_RS=X P0.23 Read Data (Start) LCD_WR=0 P0.25 Read D08-D15 Read MSBs P2.0-P2.7 Enable LSB buffer outputs LCD_EN=1 P019 Read D00-D07 Read LSBs P2.0-P2.7 Read Data (End) LCD_WR=1 P0.25 Deselect Device LCD_CS=1 P0.22 …

Tabel 11 Databus interface description

Description IO Pin DB00 P2.0 (latched) DB01 P2.1 (latched) DB02 P2.2 (latched)


DB03 P2.3 (latched) DB04 P2.4 (latched) DB05 P2.5 (latched) DB06 P2.6 (latched) DB07 P2.7 (latched) DB08 P2.0 (buffered) DB09 P2.1 (buffered) DB10 P2.2 (buffered) DB110 P2.3 (buffered) DB12 P2.4 (buffered) DB13 P2.5 (buffered) DB14 P2.6 (buffered) DB15 P2.7 (buffered) /CS P0.22 RS P0.23 /WR P0.24 /RD P0.25 RESET RESET

2.8.3 Display Interface The CN7 interface of the Land Tiger LPC17XX development board can be connected to a 2.8 or 3.2 inch 320X240 TFT color LCD. The datalines are connected to P2.0 ... P2.7 and by 8bit - 16bit conversion circuit connected to the LCD. In addition to the 16 bit databus, the LCD interface also supports a touchschreen controller. This interface is provided as an SPI bus. Depending on the LCD board the LCD backlight may be controlled either as on/off or with variable brightness (PWM control). The LCD connector pinout is defined in table 1: Tabel 12 CN7 Color TFT LCD interface description

Pin Description IO Pin Comment 1 3V3 Power supply 2 GND Ground 3 DB00 P2.0 (latched) Databus 4 DB01 P2.1 (latched) 5 DB02 P2.2 (latched) 6 DB03 P2.3 (latched) 7 DB04 P2.4 (latched) 8 DB05 P2.5 (latched) 9 DB06 P2.6 (latched) 10 DB07 P2.7 (latched) 11 DB08 P2.0 (buffered) 12 DB09 P2.1 (buffered)


13 DB10 P2.2 (buffered) 14 DB110 P2.3 (buffered) 15 DB12 P2.4 (buffered) 16 DB13 P2.5 (buffered) 17 DB14 P2.6 (buffered) 18 DB15 P2.7 (buffered) 19 /CS P0.22 Low active 20 RS P0.23 RS = 1:

Instruction Register RS = 0: Data Register

21 /WR P0.24 Low active WR 22 /RD P0.25 Low active RD 23 RESET RESET Low active 24 NC NC Do not connect 25 BLVCC 5V Backlight VCC 26 BLGND GND Backlight GND 27 BLCNT (Brightn.

PWM) NC Control of the

backlight brightness via PWM

28 TP_INT Touchscreen P2.13 Low level while the touch screen detects pressing

29 TP_CS Touchscreen P0.6 Low active 30 TP_SCK

Touchscreen P0.7 Connects to SPI

SCK 31 TP_MOSI


MOSI 32 TP_MISO


MISO 33 3V3 3V3 34 GND GND

Note: details on the LCD operation may be found in Chapter XXX. Note: problem with 5V-3V3 converter on LCD board interfering with mainboard powersupply !!!!!

2.9 EEPROM LandTiger LPC17XX development board includes a 24LC02 (2 kbit / 256kByte) EEPROM (U6) connected to the LPC1768 I2C_0 port (fast mode supported, upto 1 Mbit/s).

IO Pin Description P0.27 EEPROM SDA P0.28 EEPROM SCL


Note1: The I2C Slaveaddress of the EEPROM is hardcoded at 0xA0 (8 bit address) Note2: The I2C0 SDA and SCL lines have pull-up Rs installed of 4K7 to 3V3. Note3: The Write Protect of the EEPROM is disabled (pull to GND).

Figuur 11 I2C EEPROM 24C02 (U6)

2.10 DataFlash LandTiger LPC17XX development board includes a AT45DB16D (16 Mbit / 2MByte) DataFlash (U7) connected to the LPC1768 SPI_0 port.

IO Pin Description P0.18 DataFlash MOSI P0.17 DataFlash MISO P0.16 DataFlash /CS (active low) P0.15 DataFlash SCK

Note1: The Slaveaddress of the FLASH … Note2: The SPI_CS has a pull-up R installed of 10K to 3V3. Note3: The /WriteProtect of the DataFlash is disabled (pull-up to 3V3).


Figuur 12 SPI Flash 45DB16D (U7)

2.11 CAN The LandTiger LPC17XX development board supports 2 CAN2.0 A/B bus communication interfaces. CAN_1 uses UART XX, CAN_1 uses UART XX. The CAN Transceivers are U12 and U13 (SN65HVD230). The CAN bus screw terminal accepts 5.08mm pitch leads. Tabel 13 CAN interface description CN8

Pin Description IO Pin 1 5V 2 CAN_1 H P0.0/P0.1 3 CAN_1 L P0.0/P0.1 4 CAN_2 H P0.4/P0.5 5 CAN_2 L P0.4/P0.5 6 GND

IO Pin Description Comment P0.0 CAN1_RX CANRX1/TXD3 P0.1 CAN1_TX CANTX1/RXD3 P0.4 CAN2_RX CANRX2 P0.5 CAN2_TX CANTX2


Figuur 13 CAN1 and CAN2 connector CN8; RS485 Connector CN10

Note1: The CAN1 and CAN2 inputs/outputs are terminated by R129 and R128 (120 ohm). This means the LandTiger should be located on either end of the CAN bus rather than somewhere in the middle.

2.12 RS-232 The Land Tiger LPC17XX development board supports two bi-directional RS-232 Communication interfaces COM1, COM2 connected to LPC1768 UART0 and UART2. The RS232 Transceivers is U10 (SP3232). The COM1 RS-232 interface may also be used for automatic ISP programming (serial download program). The port provides two control signals for RESET and ISP activation. The circuitry is compatible with the ISP standard as defined by NXP. Note: JP6, JP7 jumpers must be installed to use serial programming procedures. Tabel 14 COM1 interface description

Pin Description IO Pin 1 NC 2 TXD UART0_TX (P0.2) 3 RXD UART0_RX (P0.3) 4 DTR DTR (Control RESET) 5 GND GND 6 NC 7 RTS RTS (Control ISP) 8 NC 9 NC Shield Shield GND

Tabel 15 COM2 interface description

Pin Description IO Pin 1 NC 2 TXD UART2_TX (P0.10)


3 RXD UART2_RX (P0.11) 4 DTR NC 5 GND GND 6 NC 7 RTS NC 8 NC 9 NC Shield Shield GND

Jumper Description JP6 Enable ISP Select.

Enable ISP Select: JP6 inserted Disable ISP Reset: JP6 removed

Jumper Description JP7 Enable ISP Reset.

Enable ISP Reset: JP1 inserted Disable ISP Reset: JP1 removed

Figuur 14 RS232 connector COM1, COM2 (female, front view)

2.13 RS-485 The LandTiger LPC17XX development board supports a bi-directional RS-485 communication interface via CN10 to UART3. The 485 Transceiver is U14 (SP3485). Tabel 16 RS485 interface description CN10

Pin Description IO Pin 1 485A UART3_TX (P4.28) 2 485B UART3_RX (P4.29)

IO Pin Description Comment P4.28 485_TX P4.29 485_RX P2.8 485_DIR TX/RX Direction


(RX is active low, TX is active high)

Note1: The 458A and 458B inputs/outputs are terminated by R84 (120 ohm). This means the LandTiger should be located on either end of the 485 bus rather than somewhere in the middle. Note2: The 458A and 458B inputs/outputs do not have pull-up/pull-down resistors to provide a defined idle voltage. These resistors may have to be added externally.

Figuur 15 CAN1 and CAN2 connector CN8; RS485 Connector CN10

2.14 SD card The Land Tiger LPC17XX development board supports an SD card interface (CN6). The SD card is accessed through the LPC1768's SSP0 port. A card detection signal is available. The power supply to the SD card is under control of the LPC17XX. Tabel 17 SD Card connector CN9

SD Pin Description IO Pin 1 /SDcard_CS P1.21 (SSEL0)

Active Low 2 SDcard_DIN P1.24 (MOSI0) 3 Vss/GND Vss/GND 4 +3V3 +3V3 (P3.26 controlled) 5 SDcard_CLK P1.20 (SCK0) 6 Vss/GND Vss/GND 7 SDcard_DOUT P1.23 (MISO0) 8 NC NC 9 NC NC 10 /SDcard_detect P3.25, Active Low 11 GND GND 12 NC NC


Tabel 18 SD Card controlsignals

IO Pin Description P1.21 /Card_CS, Active Low P3.26 SD Power, Active Low

LD3 is lit when power in on P3.25 /Card_detect, Active Low

Figuur 16 SD card socket (Power on LED LD3 is located on frontside of board)

2.15 Ethernet The LandTiger LPC17XX development board has onboard support for 10/100 Mbit/s Ethernet communication. The LPC1768 chip supports the RMII interface and links to the DP83848 (U5) Ethernet PHY chip. This device interfaces out via the RJ45 connector (CN5) which has internal magnetics and network filters. The RJ45 connector has integrated LEDs to indicate link connectivity and collisions. A separate LED indicates 10/100 Mbit/s linkspeed (LD2).


Figuur 17 Ethernet PHY and RJ45 connector

Figuur 18 RJ45 connector CN5 (frontview)

Tabel 19 RJ45 interface description

Pin Description 1 TxData+ 2 TxData- 3 RxData+ 4 Shield 5 Shield 6 RxData- 7 Shield 8 Shield


Shield Shield

2.16 Joystick The LandTiger LPC17XX board features a 5 way digital joystick (SW5). The joystick may be used for example to select options in a menu shown on the LCD. Each direction (up, down, left, right) and the Select function are connected to a dedicated digital inputpin on the LPC17XX. Multiple keys can be pressed at the same time (e.g. up and right). Inputpins are active low when a key is pressed. The inputpins are hardware debounced.

Figuur 19 Joystick 5-Way Switch

Tabel 20 Joystick 5-way switchsignals

IO Pin Description P1.25 Select P1.26 Down P1.27 Left P1.28 Right P1.29 Up

2.17 Switches The LandTiger LPC17XX board features 4 switches: Key1 (SW4), Key2 (SW3), INT0 (SW2), RESET (SW1). These switches have several functions. See table below.


Figuur 20 Switches and Alternate functions

Tabel 21 Switch Description

Key type Description Comment Key1 Connected to INT1(P2.1),

Active Low SW4

Key2 Connected to INT2 (P2.12), Active Low

SW3, Secondary function to enter the USB ISP mode.

INT0 Connected to INT0 (P2.10) when JP5 is inserted. Active Low.

SW2, Secondary function to enter the COM1 ISP mode.

Reset Manual Reset SW1

2.18 Reset and Booting The LandTiger LPC17XX development board has several options for Reset and booting. Tabel 22 Reset and Boot options

Reset type Description Comment Power On The board will reset when

power is applied. The LPC17XX will boot by starting the user program stored in internal Flash (512 KBytes).

Manual Reset The board will reset whenever the user presses the Reset key. (SW1) and then behaves just as after Power-On reset.

Manual Reset and enter ISP mode

The device will enter the ISP programming mode when INT0 (SW2) is pressed and held before applying a Reset. The device is then ready to accept and store new user-code in the internal Flash.

SW2 is only connected to INT0 (P2.10) when JP5 is inserted. New program download through COM1 (UART0).


On completion of download, Reset again to activate the new code.

External Reset

The board will reset whenever DTR is activated on COM1 and then behaves just as after Power-On reset.

DTR is only connected to Reset when JP7 is inserted.

External Reset and enter ISP mode

The board will reset and enter the ISP programming mode whenever DTR is activated (Reset) and RTS is activated (ISP) on COM1. The board then behaves just as like manually entering the ISP mode and it is ready to accept and store new user-code in the internal Flash.

DTR is only connected to Reset when JP7 is inserted. RTS is only connected to INT0 (P2.10) when JP6 is inserted. New program download through COM1 (UART0). On completion of download, Reset again to activate the new code.

External Reset and enter ISP mode

The device may be Reset and brought in ISP mode through the JTAG port.

New program download through JTAG.

Manual Reset and enter ISP mode

The device will enter the USB Secondary bootloader programming mode when Key2 (SW3) is pressed and held before applying a Reset. The device is then ready to accept and store new user-code through the USB device port.

Key2 is connected to INT2 (P2.12). The USB Host will detect the LPC17XX as a mass storage device holding one binary file (the current program). Delete that file and download a new one through USB. Reset again to activate the new code. Note: a special USB bootloader must be stored in Flash first. See NXP documentation.

Tabel 23 Reset and Boot Jumper settings

Jumper Description Comment JP5 INT0 (P2.10)

connected to Key2 Insert Jumper to enable manual entering ISP mode

JP7 Reset activated by DTR

Insert Jumper to enable external


Reset JP6 INT0 (P2.10)

activated by RTS Insert Jumper to enable external entering ISP mode

Figuur 21 Jumper settings to enable serial port COM1 ISP

Jumper JP6 ISP mode enable by RTS Jumper JP7 Reset enable by DTR

(Note: Jumper JP5 manual ISP mode enabled by pressing Key2)

Note1: The serial bootloader is a standard feature of NXP processors. Free PC software like Flashmagic may be used to download a compiled application program. Flashmagic is able to control Reset and INT0 to initiate the ISP without need for the user to press any buttons on the board itself. The appropriate jumpers JP6, JP7 must be installed. Note2: SW2/INT0 may be used as normal IO pin during program execution. The special function to enter ISP is only used during reset. Note3: SW3/Key2/INT2 may be used as normal IO pin during program execution. The special function to enter USB bootloader is only used during reset.

2.19 JTAG Debug Function and JLINK emulator LandTiger LPC17XX development board has onboard support for JTAG debugging, downloads and other features. The debugging port (CN4) provides access to the on-board JLINK emulator (U3). JLINK is a JTAG emulator designed for ARM cores. It connects via USB (CN4) to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, Windows Vista or Windows 7. JLink has a built-in 20-pin JTAG connector (CN1), which is compatible with the standard 20-pin connector defined by ARM. The JTAG/SWD interface and JLINK emulator supports KEIL, IAR and other mainstream development environments. The JTAG/SWD interface (CN1) may also be connected to any external general purpose JTAG/SWD debugging device. In this case the on-board JLINK emulator must be disabled by inserting JP4. LED LD1 shows the current status of the JLINK debugger interface.


Figuur 22 JTAG Connector CN1 for External JTAG device

Tabel 24 JTAG Connector CN1

Pin Description Comment 1 VRef 3.3V power 2 VSupply 3.3V power 3 TRST/ 4 GND 5 TDI 6 GND 7 TMS/SWDIO 8 GND 9 TCK/SWDCLK 10 GND 11 RTCK 12 GND 13 TDO/SWO 14 GND 15 SRST/ 16 GND 17 DBGRQ NC 18 GND 19 DBGACK NC 20 GND

Tabel 25 SWD CN3 Connector

Pin Description Comment 1 Power 3.3V power 2 GND 3 SWDIO 4 GND 5 SWDCLK 6 GND

Tabel 26 JTAG Mode Settings


Jumper Description Comment JP4 JTAG_SEL Insert Jumper to

enable external JTAG device. Remove Jumper to enable onboard JLINK emulator

Tabel 27 JLINK Interface Status

LED LD1 Description Comment Flash 10Hz Un-Initialized Flash 1 Hz Error Solid on Initialized/Ready Short Flash Communication

Note1: The board may be powered by the USB JLINK debugging port CN4. Set Jumper JP3 to position 2-3.

Documents

LandTiger V2.0 LPC17XX Development Board - Arm Mbed · PDF fileLandTiger V2.0 User Manual 2 1 Overview The LandTiger V2.0 NXP LPC1768 ARM development board is based on a second-generation