CSE 260M Lab 5: Implementing SPI protocol to communicate with a peripheral gyroscope sensor module

Work in pairs for this assignment

Lab Objectives

Learn how to interact with peripheral modules (Pmods) using XEM6002

Implement SPI protocol to interface with a gyroscope sensor Pmod

Design a FrontPanel profile to display outputs from the gyroscope sensor

1. Introduction The Opal Kelly XEM6002 allows for the attachment of small peripheral modules (Pmods), which hold different kinds of sensors. In this lab exercise, you will use a Pmod with an on-board 3-axis digital gyroscope: the PmodGYRO. It connects to one of the four POD connectors on the XEM6002 as shown in Figure 1. Note the orientation of the PmodGYRO board, including the eight pins facing up. It is very important to connect the Pmod correctly!

Figure 1: Connecting the PmodGYRO to the XEM6002

Gyroscopes measure rotational velocity (i.e. how fast it is spinning, also known as its angular rate). This particular sensor (the chip used on the PmodGYRO is L3G4200D) can measure

rotational velocity about the x, y and z axes. The PmodGYRO sensor also measures temperature. It outputs all of this information as digital data. To communicate with the gyroscope sensor onboard the PmodGYRO board, you will use the SPI communication protocol and read back the device ID, temperature, and X, Y and Z values. The relevant datasheets are provided in the lab supplement. They are:

XEM6002-UM.pdf: User manual for the Opal Kelly XEM6002 board

PmodGYRO_refManual.pdf: Reference manual for the PmodGYRO

L3G4200D_refManual.pdf: Reference manual for the L3G4200D gyroscope chip You will be referring to these datasheets as you work through the lab. Read PmodGYRO_refManual.pdf to get a quick overview about PmodGYRO before you proceed to the next section.

2. SPI communication protocol

The Serial Peripheral Interface (SPI) standard specifies a synchronous serial interface in which

data is shifted in or out from a serial peripheral device one bit at a time. When using SPI to

communicate, devices are either in master or slave mode as shown in Figure 2.

Figure 2: Master/Slave relationship for SPI communication

The devices communicate with one another using the following four wires:

Chip Select (CS): It is the serial port enable and is controlled by the master. It goes low at

the start of transmission and returns high at the end of transmission.

Serial Clock (SPC): It is the serial port clock and is controlled by the master. It provides

the timing of the serial communication.

Serial Data Input (SDI): It transfers data serially into the slave device. Values are latched

on the rising edge of the SPC.

Serial Data Output (SDO): It transfers data serially out of the slave device. Data is shifted

out on the falling edge of the SPC.

The gyroscope supports the SPI protocol for reading and writing its registers, which are used to

control its behavior and to retrieve rotational velocity data.

2.1 SPI read protocol

The SPI read protocol is shown in Figure 3.

Figure 3: SPI read protocol

The SPI read command is performed with 16 clock pulses using the following sequence:

The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS. This

first bit is the read/write select bit. Its value is set to 1 and is shifted into the PmodGYRO

device to indicate a read command.

Register address, which is 7 bits wide, is then shifted into the PmodGYRO device starting

with the most significant bit, MS bit.

The MS bit (bit 1), enables auto increment of register address for multiple byte reading

when it is set to 1, otherwise auto increment is disabled when it is set to 0.

The rest of register address bits AD(5:0), (bits 2 through 7), are shifted into the

PmodGYRO device one bit at a time.

Output data DO(7:0), (bits 8 through 15), are shifted out of the PmodGYRO device one

bit at a time starting with most significant bit.

The last bit (bit 15) starts at the falling edge of SPC just before the rising edge of CS.

2.2 SPI write protocol

The SPI write protocol is shown in Figure 4.

Figure 4: SPI write protocol

The SPI write command is performed with 16 clock pulses using the following sequence:

The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS. This

first bit is the read/write select bit. Its value is set to 0 and is shifted into the PmodGYRO

device to indicate a write command.

Register address, which is 7 bits wide, is then shifted into the PmodGYRO device starting

with the most significant bit, MS bit.

The MS bit (bit 1), enables auto increment of register address for multiple byte writing

when it is set to 1, otherwise auto increment is disabled when it is set to 0.

The rest of register address bits AD(5:0), (bits 2 through 7), are shifted into the

PmodGYRO device one bit at a time.

Input data DI(7:0), bits 8 through 15, are shifted into the PmodGYRO device one bit at a

time starting with most significant bit.

The last bit (bit 15) starts at the falling edge of SPC just before the rising edge of CS.

More information about SPI read and write protocols can be found in section 5.2 of

L3G4200D_refManual.pdf.

2.3 Relevant Registers of L3G4200D

The gyroscope contains a set of registers, which are used to control its behavior and to retrieve

rotational velocity data. The register address, which is 7 bits wide, is used to identify the

register. The gyroscope registers are listed and described in sections 7 and 8 respectively of

L3G4200D_refManual.pdf.

For this lab exercise, you will design an SPI controller module that interacts with the following registers:

WHO_AM_I get device identification

CTRL_REG1 set output data rate, select bandwidth, select power down/normal/sleep mode, enable/disable x, y, and z axes.

OUT_TEMP get temperature data

OUT_X_L get lower byte data of X-axis angular rate

OUT_X_H get higher byte data of X-axis angular rate

OUT_Y_L get lower byte data of Y-axis angular rate

OUT_Y_H get higher byte data of Y-axis angular rate

OUT_Z_L get lower byte data of Z-axis angular rate

OUT_Z_H get higher byte data of Z-axis angular rate

Angular rate data for each of X, Y, and Z axes is described by 16-bit data that is expressed in 2s

complement. The angular rate data for an axis is output in two bytes from two separate

registers. For instance, X-axis angular rate data consists of lower byte data from OUT_X_L

register and higher byte data from OUT_X_H register.

2.2 Timing Constraints

Figure 5 (Table 7 of datasheet L3G4200D_refManual.pdf) shows SPI slave timing constraints.

According to Figure 5, the minimum clock cycle (period) for SPC is 100 ns, which is a maximum

of 10 MHz. For the SPI protocol, it is necessary to satisfy the setup and hold time requirements

for CS, SDI, and SDO signals.

Figure 5: SPI slave timing constraints

3. Design an SPI controller In this lab, you will design an SPI controller module in the form of a finite state machine in VHDL. The SPI controller module in FPGA (master) will communicate with PmodGYRO device (slave). The master/slave relationship between SPI controller module and PmodGYRO device is shown in Figure 6.

Figure 6: Master/slave relationship between SPI controller module and PmodGYRO device

The SPI controller module should contain the following input signals:

clk clock signal to drive state machine

reset signal that resets state machine to idle state

EN signal to start execution of state machine from the idle state

RdWr signal to indicate read command (RdWr=1) or write command (RdWr=0)

regAddress address of the register that will be accessed (8 bits)

writeData input data that will be shifted into the PmodGYRO device (8 bits)

SDO signal to hold output data serially shifted from the PmodGYRO device

The SPI controller module should contain the following output signals:

readData - output data shifted out of the PmodGYRO device (8 bits)

dataReady signal to indicate that a byte of data shifted from the device is ready for use

CS chip select signal to enable serial port of PmodGYRO device

SPC serial port clock that provides timing of SPI communication

SDI signal to hold data that will be serially shifted into the PmodGYRO device

3.1 State Diagram of SPI Controller Module

We can derive a state diagram of SPI protocol from the timing diagram shown in Figure 7. The timing diagram has been annotated to show different states that need to be implemented in the SPI controller module.

Figure 7: Annotated timing diagram of read and write protocol

The state diagram starts with state 0 (idle), where output CS is high and thus SPI communication is inactive. State machine of SPI controller module would transition from state 0 to state 1 when EN signal is high, otherwise the state machine would remain in state 0. At state 1, CS goes low to enable the serial port, which marks the start of transmission. At state 2, RW bit is provided to the SDI wire on the falling edge of SPC At state 3, RW bit is latched into the PmodGYRO device on the rising edge of the SPC At state 4, MS bit is provided to the SDI wire on the falling edge of SPC At state 5, MS bit is latched into the PmodGYRO device on the rising edge of the SPC Similarly, AD(5:0) bits are provided to the SDI wire on the falling edge of the SPC and latched into the device on the rising edge of the SPC during states 6 through 17. State machine of SPI controller module would transition from state 17 to state 18 to perform a read command when RdWr signal is high, otherwise the state machine would transition from state 17 to state 35 to perform a write command when RdWr signal is low. If writing to a register, DI(7:0) bits are provided to the SDI wire on the falling edge of the SPC and latched into the PmodGYRO device on the rising edge of the SPC during states 18 through 33. At state 34, CS goes high to disable the serial port, which marks the end of transmission. The state machine then goes into idle state, state 0, where SPI communication is inactive. If reading from a register, DO(7:0) bits are shifted out of the PmodGYRO device on the falling edge of the SPC and read from the SDO wire on the rising edge of the SPC during states 35 through 50. At state 51, CS goes high to disable the serial port, which marks the end of

transmission. The state machine then goes into idle state, state 0, where SPI communication is inactive. The first three states of the state diagram are shown in Figure 8. The state diagram is

represented as a Moore machine, where state and outputs are indicated in a circle, while a

directed arc indicates state transition from present state to next state. Inputs are indicated next

to the directed arc. In Figure 8, an x indicates value of input or output as a dont care.

Figure 8: Partial state diagram for SPI controller state machine

4. Exercises

4.1 Designing and simulating the SPI controller module

1. Complete the state diagram to include all 51 states as shown in the annotated timing

diagram in Figure 7.

2. Write VHDL code that implements an SPI controller module. The module should read and write data to registers on the PmodGYRO device. It should include a state machine based on the state diagram in (1). Use the following entity for your SPI controller module:

entity spi_controller is

port (

clk: IN STD_LOGIC;

reset: IN STD_LOGIC;

EN: IN STD_LOGIC;

RdWr: IN STD_LOGIC;

CS: OUT STD_LOGIC;

SPC: OUT STD_LOGIC;

SDI: OUT STD_LOGIC;

SDO: IN STD_LOGIC;

regAddress: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

writeData: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

readData: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

dataReady: OUT STD_LOGIC);

end spi_controller;

Refer to Section 3 of this manual for pin description.

3. Simulate the SPI controller module in ModelSim for a 1 MHz clock. Generate SDO input

signal using a continuously incrementing counter in your testbench. Make sure that your ModelSim waveform matches the timing diagram shown in Figure 7.

4. Simplify the state machine of your SPI controller module to use less than 10 states.

Hint: Use a counter and/or shifting mechanism to iterate through register address, SDI data, and SDO data. The following webpage provides information on shift and other operators in VHDL: http://www.csee.umbc.edu/portal/help/VHDL/operator.html

5. Make a new state diagram for the simplified SPI controller and code the state machine

in VHDL.

6. Simulate your simplified SPI controller module to verify its correct operation. You will be graded on this simulation.

4.2 Generate 5MHZ clock

This exercise will guide you on how to generate a 5MHZ clock based on the 100MHZ system

clock (clk1) using the IP Clocking Wizard tool provided by Xilinx. An IP (intellectual property)

core is a block of HDL code that other engineers have already written to perform a specific

function. The IP Clocking Wizard core makes it easy to create HDL source code for clock circuits

customized to your clocking requirements.

1. Add a new IP CORE to the project by right clicking on the FPGA (XC6SLX9-2FTG256) in the

Hierarchy panel of Design window and choosing New Source. Alternatively, you can go to

the menu bar and choose Project > New Source.

The New Source wizard will open as shown in Figure 9. Select IP(CORE Generator &

Architecture Wizard), and give it a reasonable file name and location.

Figure 9: New source wizard

2. Click Next. Select IP window will appear as shown in Figure 10. Select FPGA Features and

Design > Clocking > Clocking Wizard.

Figure 10: Selecting clocking wizard for IP Core generator

3. Click Next and Finish. A Clocking Wizard will pop up as shown in Figure 11. The wizard will

guide you in selecting settings of your IP Core.

Figure 11: Clocking wizard

4. Page 1 of the clocking wizard will allow you to select clocking features and input clocks.

Confirm that frequency of the input clock matches frequency of the system clock, which is

100MHz. Set clock manager type to auto selection, which will allow the wizard to

automatically select the appropriate primitive block for your IP Core. Click Next to proceed

to page 2.

5. Page 2 of the clocking wizard will allow you to select output clock settings. Set parameters

of output clock as follows: 5MHz output frequency, 0 degrees phase, and 50% duty cycle.

Click Next to proceed to page 3.

6. Page 3 of the clocking wizard will allow you to select I/O and feedback settings. Deselect

reset and locked settings. Select Automatic control on-chip as the clock feedback source.

Click Next to proceed to page 4.

7. Page 4 summarizes settings of your IP Core based on your input from previous steps. Click

Next to proceed to page 5.

8. Page 5 allows you to select port names of input and output clocks. You may use default

names or change names of the ports. Click Next to proceed to page 6.

9. Page 6 provides summary of your IP Core. It lists and briefly describes all the generated files.

10. Click Generate to complete IP Core generation. Wait for the IP Core generation process to

complete. A .xco file will be added to your project.

11. To view component declaration and instantiation template of your IP Core, click on the

.xco file in the Hierarchy window, expand the CORE Generator in processes window,

and double click on View HDL instantiation Template as shown in Figure 12.

Figure 12: View component declaration and instantiation template of the IP Core

4.3 Read device ID, X, Y, Z and temperature data using SPI controller module

1. Make a new module, called top_level. This will be your top-level design. Instantiate the SPI controller module in the top_level module.

2. In the top-level design, instantiate an IP Core that takes 100MHz system clock as the input, and generates 5MHz clock as the output. Use the 5MHz clock to drive the SPI controller state machine. Follow the guide in section 4.2 of this manual to generate the IP Core.

3. In the top-level design, have a second state machine that sends a read request to the SPI controller for the device ID of the PmodGYRO device. See Section 2.3 of this manual for the appropriate register address (WHO_AM_I).

4. You will also need to include the appropriate FrontPanel USB communication module(s) in the top-level design. For more information, consult previous labs.

5. The J1 connector of the PmodGYRO connects to any one of the four POD connectors on the XEM6002 board. The J1 connector has the pinout shown in Figure 13 (from page 2 of PmodGYRO_refManual.pdf datasheet).

Figure 13: J1 connector pinout.

Each POD has an associated pinout, as shown in Figure 14. This was taken from page 13 of XEM6002-UM.pdf. Note that there are power (+3.3VDD) and ground (DGND) pins in addition to I/O pins on each POD.

Figure 14: POD connections to FPGA pins

Scroll down the UCF file to see where the POD pins are shown. Only the I/O pin connections are modifiable. # POD1

#######################################################################

#NET "POD1_P1" LOC="M1" | IOSTANDARD="LVCMOS33";

#NET "POD1_P2" LOC="L1" | IOSTANDARD="LVCMOS33";

#NET "POD1_P3" LOC="K1" | IOSTANDARD="LVCMOS33";

#NET "POD1_P4" LOC="J1" | IOSTANDARD="LVCMOS33";

#NET "POD1_P7" LOC="E1" | IOSTANDARD="LVCMOS33";

#NET "POD1_P8" LOC="E2" | IOSTANDARD="LVCMOS33";

#NET "POD1_P9" LOC="F1" | IOSTANDARD="LVCMOS33";

#NET "POD1_P10" LOC="G1" | IOSTANDARD="LVCMOS33";

Depending on which POD you are using to connect your Pmod, uncomment the lines for the POD*_P1 to POD*_P4 pins. These will be connected to the CS, SDI, SDO and SPC ports on the SPI_controller respectively. It is very important that you connect the pins in the right order!

6. Design a FrontPanel profile to display the device ID. If successful, you will see the value 11010011(0xD3).

7. Next, expand the top-level state machine to send a sequence of requests. The sequence of requests starts with initializing the control register CTRL_REG1*, then looping through the following requests: read device ID, temperature and X, Y, Z data. This sequence is looped so all the information updates every few clock cycles. *CTRL_REG1: This is a control register that needs to be set up before the X, Y, Z and temperature information from the sensor can be output. Information on CTRL_REG1 is given in section 7.2. Set the parameters as follows:

a. Output Data Rate of 400 Hz, b. Bandwidth cut-off of 25 Hz, c. Power-down mode set to normal mode, d. X axis, Y axis and Z axis all enabled.

8. Expand the FrontPanel profile to observe all the outputs from the gyroscope: device ID,

temperature, X, Y and Z data.

Lab 5 Demonstration Rubric

Student Name & ID #:

Student Name & ID#:

Demo date:

Requirement Points

Show drawings of state diagrams: long and simplified /2

Show ModelSim simulation for simplified SPI controller state machine /3

Reading the correct device ID /2

CTRL_REG1 set up with the correct value /2

Reading temperature, X, Y and Z correctly /3

Reading all the values in a loop: ID, temperature, X, Y and Z /3

Total /15

Student Survey:

How much did you learn on this lab? (Nothing) 1 2 3 4 5 (Brain Hurts)

How much did you enjoy this lab? (Unpleasant) 1 2 3 4 5 (Very much)

How many hours outside of scheduled time did you work on this lab? ________

Please write any comments you may have about the lab below:

Lab Objectives1. Introduction2. SPI communication protocol2.1 SPI read protocol2.2 SPI write protocol2.3 Relevant Registers of L3G4200D2.2 Timing Constraints

3. Design an SPI controller3.1 State Diagram of SPI Controller Module

4. Exercises4.1 Designing and simulating the SPI controller module4.2 Generate 5MHZ clock4.3 Read device ID, X, Y, Z and temperature data using SPI controller module

Lab 5 Demonstration Rubric