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Ibrahim Hazmi | CENG 450 LAB
CENG450 Project 16-bit Pipelined MIPS Processor
Ibrahim Hazmi - 2018
LAB 3
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Ibrahim Hazmi | CENG 450 LAB
Register File & ALU8 16-bit registers: r0, r1, r2, r3, r4,
r5, r6, r7
Read operation: the register file gets rd_index1 and rd_index2
to deliver the corresponding rd_data1 and rd_data2.
Write operation: the register file writes the value on wr_data
to the register determined by wr_index, when wr_en is one.
alu_mode ALU operation0 Nop1 Add2 SUB - Subtract3 MUL- Multiply4
NAND5 SHL - Shift Left Logical6 SHR - Shift Right Logical7 TEST
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Ibrahim Hazmi | CENG 450 LAB
Some notes about ALU➡ ALU components can be built behaviourally
or
structurally. ➡ Signed data type is recommended for (+/-/*)
operations, using “ieee.std_logic_arith.all”. ➡ Multiplication
(*) results in 32-bit output. The
decision on the higher 16-bit should be made. ➡ SHL & SHR
can be performed using Barrel
Shifter or by a simple LOOP of a single shift, e.g, for i in 1
to 16 loop if i
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Ibrahim Hazmi | CENG 450 LAB
Simple CPU
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Ibrahim Hazmi | CENG 450 LAB
Simple CPU➡ CPU entity here has 8-inputs and 3-outputs Ports. ➡
RF & ALU are defined as components, and
rd_data1/rd_data2 as signals, in the CPU body. ➡ Wr_data is
required to feed the targeted Registers
with external data before reading from them. ➡ RF & ALU have
the same clk & rst signals ➡ Testbench input samples should
fall into 4 parts:
➡ Registers filling via (wr_data) ➡ Registers reading ➡ ALU
operation select via (alu_mode) ➡ Register write back (result to
wr_data of RF)
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Ibrahim Hazmi | CENG 450 LAB
Pipelined CPU (Conceptual Format A)
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Ibrahim Hazmi | CENG 450 LAB
Some notes about the CPU
➡ CPU entity here can have 3-inputs (clk, rst, IN) and 1-output
(OUT) Ports.
➡ PC, ROM, RF, ALU, & ROM, and the Stages Registers are
defined as components, and each internal connection as signals, in
the CPU body.
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Ibrahim Hazmi | CENG 450 LAB
Implemented through use of sequential logic units as a finite
state machine (FSM)
Organized as a sequence of micro-instructions with a control
memory.
Control Unit (CU) approachesHardwired CU (FSM) Microprogrammed
CU
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Ibrahim Hazmi | CENG 450 LAB
library IEEE;use IEEE.STD_LOGIC_1164.ALL; --Sequence detector
for detecting the sequence "1011".entity seq_det
isport( clk : in
std_logic; --clock
signal reset : in
std_logic; --reset
signal S_in : in
std_logic; --serial bit Input
sequence
S_out : out
std_logic); --
Output end
seq_det;architecture Behavioral of seq_det is --Defines the type
for states in the state machinetype state_type is (S0,S1,S2,S3,S4);
signal Current_State, Next_State : state_type; begin process(clk)
-- Synchronous Processbegin if( reset = '1' )
then --Synchronous
Reset Current_State
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Ibrahim Hazmi | CENG 450 LAB
library IEEE;use IEEE.STD_LOGIC_1164.ALL; entity Mult is
port(CLK, St, K, M: in std_logic; Load, Sh, Ad, Done: out
std_logic);end Mult;architecture SMbehave of Mult issignal State,
Nextstate: integer range 0 to 3;begin process(St, K, M, State)
begin Load
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Ibrahim Hazmi | CENG 450 LAB
library IEEE;use ieee.std_logic_1164.all;use
ieee.std_logic_unsigned.all;entity mult4X4_micro is port(Clk, St:
in std_logic; Mplier, Mcand: in std_logic_vector(3 downto 0);
Product: out std_logic_vector(7 downto 0); Done: out std_logic);end
mult4X4_micro;architecture microprogram of mult4X4_micro istype ROM
is array(0 to 5) of
std_logic_vector(11 downto 0);constant
control_store: ROM := (X"010", X"D28", X"630", X"E44", X"952",
X"C01");signal ACC: std_logic_vector(8 downto 0); alias M:
std_logic is ACC(0);signal TMUX, Load, Ad, Sh, K: std_logic;signal
counter: std_logic_vector(1 downto 0) := “00";signal uAR:
std_logic_vector(2 downto 0) := "000";signal uIR:
std_logic_vector(11 downto 0) := X”000”;alias TEST:
std_logic_vector(1 downto 0) is uIR(11 downto 10);alias NSF:
std_logic_vector(2 downto 0) is uIR(9 downto 7);alias NST:
std_logic_vector(2 downto 0) is uIR(6 downto 4);begin Load
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Ibrahim Hazmi | CENG 450 LAB
library IEEE;use ieee.std_logic_1164.all;use
ieee.std_logic_unsigned.all;entity Parity_Gen is port(OT: in
std_logic; X: in std_logic_vector(3 downto 0); Y: out
std_logic_vector(4 downto 0));end Parity_Gen;architecture Table of
Parity_Gen is type OutTable is array(0 to 15) of std_logic; signal
ParityBit: std_logic; constant OT: OutTable :=
('1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1');begin ParityBit
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Ibrahim Hazmi | CENG 450 LAB
References
https://en.wikipedia.org/wiki/Control_unit
https://voer.edu.vn/file/7173
http://people.uncw.edu/tagliarinig/Courses/242/RegisterTransfer/BasicControlUnit.gif
http://www.slideshare.net/mekind/basic-computer-organization-and-design-30538899
http://www.vlsiencyclopedia.com/2011/12/finite-state-machine-coding-in-vhdl.html
http://faculty.weber.edu/snaik/ECE3610/09Lec9.pdf
ece.citadel.edu/hayne/elec418/418_05.ppt
https://en.wikipedia.org/wiki/Control_unithttps://voer.edu.vn/file/7173http://people.uncw.edu/tagliarinig/Courses/242/RegisterTransfer/BasicControlUnit.gifhttp://people.uncw.edu/tagliarinig/Courses/242/RegisterTransfer/BasicControlUnit.gifhttp://www.slideshare.net/mekind/basic-computer-organization-and-design-30538899http://www.slideshare.net/mekind/basic-computer-organization-and-design-30538899http://www.vlsiencyclopedia.com/2011/12/finite-state-machine-coding-in-vhdl.htmlhttp://www.vlsiencyclopedia.com/2011/12/finite-state-machine-coding-in-vhdl.htmlhttp://faculty.weber.edu/snaik/ECE3610/09Lec9.pdfhttp://ece.citadel.edu/hayne/elec418/418_05.ppt
