LAB MANUAL - WordPress.com...LAB MANUAL PREPARED BY : VIDYA SAGAR.P 2020-2021 Associate Professor 1 | P a g e PREPARED BYpotharajuvidyasagar.wordpress.com VIDYA SAGAR.P Tick mark on

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Aushapur, Ghatkesar, Medchal.Dist – 501 301.

VLSI & E-CAD

LABORATORY

IV B.Tech I Sem Course Code: EC703PC Department of Electronics &

Communication Engineering

LAB MANUAL

PREPARED BY : VIDYA SAGAR.P

2020-2021

Associate Professor

1 | P a g e potharajuvidyasagar.wordpress.com PREPARED BY VIDYA SAGAR.P

Tick mark on the LEFT column for the relevant PSOs & POs of the subject:

Programme Outcomes (POs):

1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering problems

2

Problem analysis: Identify, formulate, review research literature, and analyze complex

engineering problems reaching substantiated conclusions using first principles of mathematics,

natural sciences, and engineering sciences

3

Design/development of solutions: Design solutions for complex engineering problems and

design system components or processes that meet the specified needs with appropriate

consideration for the public health and safety, and the cultural, societal, and environmental

considerations

4

Conduct investigations of complex problems: Use research-based knowledge and research

methods including design of experiments, analysis and interpretation of data, and synthesis of the

information to provide valid conclusions

5

Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern

engineering and IT tools including prediction and modeling to complex engineering activities

with an understanding of the limitations

6

The engineer and society: Apply reasoning informed by the contextual knowledge to assess

societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to

the professional engineering practice

7

Environment and sustainability: Understand the impact of the professional engineering

solutions in societal and environmental contexts, and demonstrate the knowledge of, and need

for sustainable development

8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms

of the engineering practice.

9 Individual and team work: Function effectively as an individual, and as a member or leader in

diverse teams, and in multidisciplinary settings

10

Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write

effective reports and design documentation, make effective presentations, and give and receive

clear instructions.

11

Project management and finance: Demonstrate knowledge and understanding of the

engineering and management principles and apply these to one’s own work, as a member and

leader in a team, to manage projects and in multidisciplinary environments

12 Life-long learning: Recognize the need for, and have the preparation and ability to engage in

independent and life-long learning in the broadest context of technological change


LEARNING OUTCOMES:

➢ Students will be able to design digital circuits/systems through a Hardware descriptive

language.

➢ Students will able to use CAD tools (IDE) to design and analyse digital systems.

➢ Students will be familiar with the Logic synthesis, Simulation and verification of digital circuits

and implementation of FPGA Device.

➢ Students will be familiar Scaling of CMOS Inverter for different technologies, study of

secondary effects

➢ Students will understand the Circuit optimization with respect to area, performance and/or

power, Layout, Extraction of parasitic and back annotation, modifications in circuit parameters

and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS)

DO'S AND DON’T:

Check the system before start doing programme and close the project before shutting down the

systems.

Do not touch the FPGA at any cost and don’t turn on the FPGA board before connecting to the system

with the JTAG Port.


INSTRUCTIONS TO STUDENTS:

➢ Students are expected to attend the lab sessions well dressed in formals.

➢ Write records neatly and legibly and maintain the same updated.

➢ Observation books should be submitted to the faculty concerned in the same lab session for

verification and signature.

➢ Observations should be posted in the records and the same should be brought for correction as

soon as the lab experiment is done, generally for the next lab session.

➢ Students should ensure that they sign the attendance register available in the lab.

➢ Cooperate with the teachers and the lab faculty.

➢ Any sort of indiscipline shall not be entertained.

Failure in doing so, no student is allowed into the lab.


SOFTWARE REQUIREMENTS:

1. Xilinx Vivado System edition IDE 2018.1 version Synthesis and Simulation Tools.

2. Mentor Graphics HEP1 (Layout Editor) Software.

HARDWARE REQUIREMENTS: 1. Nexys 4 A7 FPGA board

2. Zynq Zed development board

3. Electronic explorer kit

4. Personal Computer.

5. Power Supply.

6. JTAG cable.

VLSI & E-CAD LAB


B.Tech. IV Year I Sem. L T P C Course Code: EC703PC 0 0 3 2

List of Experiments: Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor

Graphics / Synopsys /Equivalent CAD tools. The design shall include Gate-level design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects ( temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitics and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS) E-CAD programs: Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools. 1. HDL code to realize all the logic gates 2. Design of 2-to-4 decoder 3. Design of 8-to-3 encoder (without and with priority) 4. Design of 8-to-1 multiplexer and 1-to-8 demultiplexer 5. Design of 4 bit binary to gray code converter 6. Design of 4 bit comparator 7. Design of Full adder using 3 modeling styles 8. Design of flip flops: SR, D, JK, T 9. Design of 4-bit binary, BCD counters (synchronous/ asynchronous reset) or any sequence counter 10. Finite State Machine Design VLSI programs: ➢ Introduction to layout design rules. Layout, physical verification, placement & route for

complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following:

1. Basic logic gates 2. CMOS inverter 3. CMOS NOR/ NAND gates 4. CMOS XOR and MUX gates 5. Static / Dynamic logic circuit (register cell) 6. Latch 7. Pass transistor 8. Layout of any combinational circuit (complex CMOS logic gate). 9. Analog Circuit simulation (AC analysis) – CS & CD amplifier.

Note: Any SIX of the above experiments from each part are to be conducted (Total 12)

CONTENTS


S.NO EXPERIMENT NAME (CYCLE-I) PAGE NO

1 XILINX SOFTWARE PROCEDURE

2 EXP 1: HDL CODE TO REALIZE ALL THE LOGIC GATES

3 EXP 2: DESIGN OF 2-TO-4 DECODER

4 EXP 3: DESIGN OF 8-TO-3 ENCODER (WITHOUT AND WITH PRIORITY)

5 EXP 4: DESIGN OF 8-TO-1 MULTIPLEXER AND 1X8 DEMULTIPLEXER

6 EXP 5: DESIGN OF 4 BIT BINARY TO GRAY CODE CONVERTER

7 EXP 6: DESIGN OF 4 BIT COMPARATOR

8 EXP 7: DESIGN OF FULL ADDER USING 3 MODELLING STYLES

9 EXP 8: DESIGN OF FLIP FLOPS: SR, JK, T

10 (ADDITIONAL EXPERIMENTS BEYOND JNTU SYLLABUS)

11 EXP 1:LEFT SHIFT REGISTER

12 EXP 2: DESIGN OF SEVEN SEGMENT DISPLAY

13 OPEN ENDED EXPERIMENTS

14

15

16

17

18

19

20

21

22

23


COMMON PROCEDURE:

1. Create New project and type the project name and check the top level source type as HDL

2. Enter the device properties and click Next

3. Click New Source And Select the Verilog Module and then give the file name

4. Give the Input and Output port names and click finish.

5. Type the Verilog program check syntax and save it

6. Double click the synthesize and generate report

7. Generate a test bench file and observe the waveform by simulation run behavioral

simulation

8. For implementation Select XDC design constraints and give input and output port pin

number

9. Click Implement design for Translate, map and place & route

10. Generate .bit file using programming file

11. Implement in FPGA through parallel-JTAG cable

12. Check the behavior of design in FPGA by giving inputs


EXP 1: HDL CODE TO REALIZE ALL THE LOGIC GATES.

AIM:

To develop the source code for logic gates by using VERILOG and obtain the simulation.

SOFTWARE & HARDWARE:

1. XILINX VIVADO 2018.1 VERSION.

2. FPGA-ZYNQ BOARD XC7Z020CLG484-1.

3. JUMPER CABLE WITH POWER SUPPLY.

GATE LOGIC DIAGRAM: TRUTH TABLE:

AND GATE:

A B Y=AB 0 0 0 0 1 0 1 0 0 1 1 1

NOT GATE:

A Y=~A

0 1 1 0

OR GATE:

A B Y=A+B 0 0 0 0 1 1 1 0 1 1 1 1

NAND GATE:

A B Y=~(AB) 0 0 1 0 1 1 1 0 1 1 1 0

NOR GATE:

A B Y=~(A+B) 0 0 1 0 1 0 1 0 0 1 1 0

XOR GATE:

A B

0 0 0 0 1 1 1 0 1 1 1 0

XNOR GATE:

A B Y=A⊙B 0 0 0 0 1 1 1 0 1 1 1 0


Black Box :

C[0]

a C[1] C[2] C[3]

b C[4] C[5] C[6]

Truth table Basic gates:

VERILOG SOURCE CODE: //Data flow model //Gate level model

module logicgates1(a, b, c); input a;

input b; output [6:0] c;

assign c[0]= a & b;

assign c[1]= a | b;

assign c[2]= ~(a & b);

assign c[3]= ~(a | b);

assign c[4]= a ^ b;

assign c[5]= ~(a ^ b);

assign c[6]= ~ a;

endmodule

module basicgates(Y,A,B);

input A,B;

output [6:0] Y;

and g1(Y[0],A,B);

or g2(Y[1],A,B);

nand g3(Y[2],A,B);

nor g4(Y[3],A,B);

xor g5(Y[4],A,B);

xnor g6(Y[5],A,B);

not g7(Y[6],A);

endmodule

Verilog Behavioral Programs for logic gates implementation

AND GATE :

module andgate(a,b);

input [1:0] a;

output reg b;

always@(a)

begin

case(a)

2'b11:b=1'b1;

default:b=1'b0;

endcase

end

endmodule

OR GATE :

module orgate(a,b);

input [1:0] a;

output reg b;

always@(a)

begin

case(a)

2'b00:b=1'b0;

default:b=1'b1;

endcase

end

endmodule

a b C[0] = a & b C[1]= a | b C[2]=~(a & b) C[3]=~(a | b) C[4]= a ^ b C[5]= ~(a ^ b) C[6]=~ a

0 0 0 0 1 1 0 1 1

0 1 0 1 1 0 1 0 1

1 0 0 1 1 0 1 0 0

1 1 1 1 0 0 0 1 0

LOGIC

GATES


NOT GATE :

module notgate(a,b);

input a;

output reg b;

always@(a)

begin

case(a)

1'b0:b=1'b1;

default:b=1'b0;

endcase

end

endmodule

NAND GATE :

module nandgate(a,b);

input [1:0] a;

output reg b;

always@(a)

begin

case(a)

2'b00:b=1'b1;

default:b=1'b0;

endcase

end

endmodule

NOT GATE :

module notgate(a,b);

input a;

output reg b;

always@(a)

begin

case(a)

1'b0:b=1'b1;

default:b=1'b0;

endcase

end

endmodule

NAND GATE :


input [1:0] a;

output reg b;

always@(a)

begin

case(a)

2'b00:b=1'b1;

default:b=1'b0;

endcase

end

endmodule

NOR GATE :

module norgate(a,b);

input [1:0] a;

output reg b;

always@(a)

begin

case(a)

2'b00:b=1'b1;

default:b=1'b0;

endcase

end

endmodule

NAND GATE :


input [1:0] a;

output reg b;

always@(a)

begin

case(a)

2'b00:b=1'b1;

default:b=1'b0;

endcase

end

endmodule

XOR GATE :

module xorgate(a,b);

input [1:0] a;

output reg b;

always@(a)

begin

case(a)

2'b00:b=1'b0;

2'b11:b=1'b0;

default:b=1'b1;

endcase

end

endmodule

XNOR GATE :

module xnorgate(a,b);

input [1:0] a;

output reg b;

always@(a)

begin

case(a)

2'b00:b=1'b1;

2'b11:b=1'b1;

default:b=1'b0;

endcase

end

endmodule


Testbench Code:

module gates_tb;

wire [6:0]c;

reg a, b;

logicgates1 dut(.c(c), .a(a), .b(b));

initial

begin

a = 1'b0;

b = 1'b0;

#100;

a = 1'b0;

b = 1'b1;

#100;

a = 1'b1;

b = 1'b0;

#100;

a = 1'b1;

b = 1'b1;

end

endmodule

Simulation output: Waveform window: Displays output waveform for verification.

RESULT:

Thus the OUTPUT’s of all logic gates are verified by simulating the VERILOG code.


Pre lab Questions

1. What is truth table?

2. Which gates are called universal gates?

3. What is the difference b/w HDL and software language?

4. Define identifiers.

5. A basic 2-input logic circuit has a HIGH on one input and a LOW on the other input,

and the output is HIGH. What type of logic circuit is it?

6. A logic circuit requires HIGH on all its inputs to make the output HIGH. What type of

logic circuit is it?

7. Develop the truth table for a 3-input AND gate and also determine the total number of

possible combinations for a 4-input AND gate.

Post lab Questions

1. What is meant by ports?

2. Write the different types of port modes.

3. What are different types of operators?

4. What is difference b/w <= and: = operators?

5. What is meant by simulation?

6. How to give the inputs in Xilinx Vivado IDE software.

7. What is meant by synthesis?


EXP 2: DESIGN OF 2-TO-4 DECODER

AIM: To develop the source code for 2-to-4 decoder by using VERILOG and obtain the

simulation.





2:4 Decoder Block diagram: 2:4 Decoder logic Diagram:

Truth Table of 2 to 4 decoder


VERILOG CODE :

DATA FLOW MODELING DATA FLOW MODELING

module dec2_4 (output [3:0] y,

input [1:0] a, input en);

assign y[0]= (~a[0]) & (~a[1]) & en;

assign y[1]= (~a[0]) & a[1] & en;

assign y[2]= a[0] & (~ a[1]) & en;

assign y[3]= a[0] & a[1] & en;

endmodule

module dec24_dat(

output [3:0] y,

input [1:0] a, input en);

assign y = en ? (4’b0001 << a) : 0;

endmodule

BEHAVIORAL MODELING BEHAVIORAL MODELING

module dec24_beh(

output reg [3:0] y,

input [1:0] a,

input en);

always @(*)

if(en) /* only if en = 1, case

statement will execute */

case(a)

0: y = 4’b0001;

1: y = 4’b0010;

2: y = 4’b0100;

3: y = 4’b1000;

default: y = 0;

endcase

else y = 0; /* if en = 0, all bits of

y will remain zero */

endmodule

module decoder_2to4(Y3, Y2, Y1, Y0, A, B, en);

output Y3, Y2, Y1, Y0; input A, B; input en;

reg Y3, Y2, Y1, Y0;

always @(A or B or en)

begin

if (en == 1'b1)

case ( {A,B} )

2'b00: {Y3,Y2,Y1,Y0} = 4'b1110;

2'b01: {Y3,Y2,Y1,Y0} = 4'b1101;

2'b10: {Y3,Y2,Y1,Y0} = 4'b1011;

2'b11: {Y3,Y2,Y1,Y0} = 4'b0111;

default: {Y3,Y2,Y1,Y0} = 4'bxxxx;

endcase

if (en == 0) {Y3,Y2,Y1,Y0} = 4'b1111;

end

endmodule

GATE LEVEL MODELING GATE LEVEL MODELING

module dec24_str(

output [3:0] y,

input [1:0] a,

input en);

and (y[0], ~a[1], ~a[0], en);

/* 3-input AND gates */

and (y[1], ~a[1], a[0], en);

and (y[2], a[1], ~a[0], en);

and (y[3], a[1], a[0], en);

endmodule

module decoder24(c,a,b,e);

output [3:0]c; input a,b,e;

wire x,y; wire [3:0]c1;

inv u1(x,a);

inv u2(y,b);

and1 u3(c1[0],x,y);

and1 u4(c1[1],x,b);

and1 u5(c1[2],a,y);

and1 u6(c1[3],a,b);

and1 u7(c[0],c1[0],e);

and1 u8(c[1],c1[1],e);

and1 u9(c[2],c1[2],e);

and1 u10(c[3],c1[3],e);

endmodule


Test bench Code:

module Test_decoder_2to4;

wire Y3, Y2, Y1, Y0;

reg A, B;

reg en;

// Instantiate the Decoder (named DUT {device under test})

decoder_2to4 DUT(Y3, Y2, Y1, Y0, A, B, en);

initial begin

#1;

A = 1'b0; // time = 0

B = 1'b0;

en = 1'b0;

#9;

en = 1'b1; // time = 10

#10;

A = 1'b0;

B = 1'b1; // time = 20

#10;

A = 1'b1;

B = 1'b0; // time = 30

#10;

A = 1'b1;

B = 1'b1; // time = 40

#5;

en = 1'b0; // time = 45

#5;

end

always @(A or B or en)

#1 $display("t=%t",$time," en=%b",en," A=%b",A," B=%b",B,"

Y=%b%b%b%b",Y3,Y2,Y1,Y0);

endmodule


RESULT:

Thus the OUTPUT of 2 to 4 decoder is verified by simulating the VERILOG HDL code.


EXP 3: DESIGN OF 8-TO-3 ENCODER (WITHOUT AND WITH PRIORITY)

AIM: To develop the source code for 8-to-3 encoder (without and with priority) by using

VERILOG and obtain the simulation.





8:3 encoder Block diagram: 8:3 encoder logic Diagram :

Digital Inputs Binary Output

D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Truth Table of 8:3 encoder


VERILOG CODE :

Structural Model Data Flow Model

module encoder (din, dout);

input [7:0] din;

output [2:0] dout;

reg [2:0] dout;

Or g1(dout[0],din[1],din[3],din[5],din[7]);

Or g2(dout[1],din[2],din[3],din[6],din[7]);

Or g3(dout[2],din[4]4,din[5],din[6],din[7]);

endmodule


input [7:0] din;

output [2:0] dout;

reg [2:0] dout;

assign dout[0]=din[1]|din[3]|din[5]|din[7;

assign dout[1]=din[2]|din[3]|din[6]|din[7];

assign dout[2]=din[4]|din[5]|din[6]|din[7];

endmodule

BehaviouralModel BehaviouralModel with Enable


input [7:0] din;

output [2:0] dout;

reg [2:0] dout;

always @(din)

begin

if (din ==8'b00000001) dout=3'b000;

else if (din==8'b00000010) dout=3'b001;




else if (din ==8'b00100000) dout=3'b101;



else dout=3'bX;

end

endmodule

module encwtoutprio(a,en,y);

input [7:0] a;

input en;

output reg [2:0] y;

always@(a or en)

begin

if(!en)

y<=1'b0;

else

case(a)

8'b00000001:y<=3'b000;

8'b00000010:y<=3'b001;

8'b00000100:y<=3'b010;

8'b00001000:y<=3'b011;

8'b00010000:y<=3'b100;

8'b00100000:y<=3'b101;

8'b01000000:y<=3'b110;

8'b10000000:y<=3'b111;

endcase

end

endmodule


TEST BENCH

module encodert_b;

reg [0:7] d;

wire a;

wire b;

wire c;

encodermod uut (.d(d), .a(a), .b(b),.c(c) );

initial begin

#10 d=8’b10000000;

#10 d=8’b01000000;

#10 d=8’b00100000;

#10 d=8’b00010000;

#10 d=8’b00001000;

#10 d=8’b00000100;

#10 d=8’b00000010;

#10 d=8’b00000001;

#10 $stop;

end

endmodule



8:3 Priority encoder Block diagram: 8:3 Priority encoder logic Diagram :

Digital Inputs Binary Output

D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 X 0 0 1

0 0 0 0 0 1 X X 0 1 0

0 0 0 0 1 X X X 0 1 1

0 0 0 1 X X X X 1 0 0

0 0 1 X X X X X 1 0 1

0 1 X X X X X X 1 1 0

1 X X X X X X X 1 1 1

Truth Table of 8:3 encoder

VERILOG CODE:

Structural Model Data Flow Model

module prior_otb_enco(DOUT, D);

output [2:0] DOUT;

input [7:0] din;

wire din7_not, din6_not, din5_not,

din4_not, din2_not;

wire wa0, wa1, wa2, wa3, wa4;;

//instantiate gates

not g0 (din7_not, din[7]),

g1 (din6_not, din[6]),



g4 (din2_not, din[2]);

module prio_enco_8x3(dout, din);

output [2:0] dout;

input [7:0] din ;

assign dout = (din[7] ==1'b1 ) ? 3'b111:

(din[6] ==1'b1 ) ? 3'b110:

(din[5] ==1'b1 ) ? 3'b101:

(din[4] ==1'b1) ? 3'b100:

(din[3] ==1'b1) ? 3'b011:

(din[2] ==1'b1) ? 3'b010:

(din[1] ==1'b1) ? 3'b001:

(din[0] ==1'b1) ? 3'b000: 3'bxxx;

endmodule


and g5 (wa0, din6_not, din4_not, din[3]),

g6 (wa1, din5_not, din4_not, din[3]),

g7 (wa2, din5_not, din4_not, din[2]),

g8 (wa3, din6_not, din[5]),

g9 (wa4,din6_not,din4_not,din2_not,din[1]);

or g11(dout[2], din[7], din[6], din[5], din[4]),

g12(dout[1], din[7], din[6], wa1, wa2),

g13(dout[0], din[7], wa0, wa3, wa4),

g14(V, din[0], din[1], din[2], din[3], din[4], din[5], din[6], din[7]);

endmodule

BehaviouralModel BehaviouralModel with Enable


input [7:0] din;

output [2:0] dout;

reg [2:0] dout;

always @(din)

begin

if (din ==8'b00000001) dout=3'b000;

else if (din==8'b0000001 X) dout=3'b001;

else if (din==8'b000001 XX) dout=3'b010;

else if (din==8'b00001XXX) dout=3'b011;

else if (din==8'b0001XXXX) dout=3'b100;

else if (din ==8'b001XXXXX) dout=3'b101;

else if (din==8'b01XXXXXX) dout=3'b110;

else if (din==8'b1XXXXXXX) dout=3'b111;

else dout=3'bX;

end

endmodule

module priori (en,din,dout);

input en;

input [ 7 : 0 ] din;

output [ 2 : 0 ] dout;

reg [ 2 : 0 ] dout;

always@(en,din)

begin

if(en == 1) // Active high enable

begin

dout = 3'bZZZ; // Initializing dout to

high Impedance

end

else

begin

casex(din)

8'b00000001 :dout = 3'b000;

8'b0000001X :dout = 3'b001;

8'b000001XX :dout = 3'b010;

8'b00001XXX :dout = 3'b011;

8'b0001XXXX :dout = 3'b100;

8'b001XXXXX :dout = 3'b101;

8'b01XXXXXX :dout = 3'b110;

8'b1XXXXXXX :dout = 3'b111;

endcase

end

end

endmodule


Test Bench Code:

module prio_enco_8x3_tst;

reg [7:0] d_in;

wire[2:0] d_out;

prio_enco_8x3 u1 (.d_out(d_out), .d_in(d_in) );

initial

begin

d_in=8'b11001100; #10;

d_in=8'b01100110; #10;

d_in=8'b00110011; #10;

d_in=8'b00010010; #10;

d_in=8'b00001001; #10;

d_in=8'b00000100; #10;

d_in=8'b00000011; #10;

d_in=8'b00000001; #10;

d_in=8'b00000000; # 10;

$stop;

end // initial begin

endmodule


RESULT:

Thus the OUTPUT of 8 to 3 decoder (without and with priority) is verified by simulating

the VERILOG HDL code.


EXP 4: DESIGN OF 8-to-1MULTIPLEXER AND 1X8 DEMULTIPLEXER

AIM:

To develop the source code for 8x1 multiplexer and demultiplexer by using VERILOG and

obtain the simulation.





8-to-1 MULTIPLEXER Block diagram: 8-to-1 MULTIPLEXER logic Diagram:

TRUTH TABLE:

Selection Inputs Output

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7


VERILOG SOURCE CODE:

Structural Model Dataflow Model Behavioral Model

modulemux81str(i0,i1,i2,i3,i4

,i5,i6,i7,s0,s1,s2,y);

input

i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2;

wire a,b,c,d,e,f,g,h;

output y;

and g1(a,i7,s0,s1,s2);

and g2(b,i6,(~s0),s1,s2);

and g3(c,i5,s0,(~s1),s2);

and g4(d,i4,(~s0),(~s1),s2);

and g5(e,i3,s0,s1,(~s2));

and g6(f,i2,(~s0),s1,(~s2));

and g7(g,i1,s0,(~s1),(s2));

and g8(h,i0,(~s0),(~s1),(~s2));

or g9(y,a,b,c,d,e,f,g,h);

endmodule

modulemux81df(y,i,s);

output y;

input [7:0] i;

input [2:0] s;

wire se1;

assign

se1=(s[2]*4)|(s[1]*2)|(s[0]);

assign y=i[se1];

endmodule

modulemux81beh(s,i0,i1,i2,i3,i4,

i5,i6,i7,y);

input [2:0] s;

input i0,i1,i2,i3,i4,i5,i6,i7;

output reg y;

always@(i0,i1,i2,i3,i4,i5,i6,i7,s)

begin

case(s)

begin

3'd0:mux_out=i0;

3'd1:mux_out=i1;

3'd2:mux_out=i2;

3'd3:mux_out=i3;

3'd4:mux_out=i4;

3'd5:mux_out=i5;

3'd6:mux_out=i6;

3'd7:mux_out=i7; endcase

end

endmodule

Test Bench Code:

module mux_3x8_tb;

wire out;

reg [2:0]sel;

reg [7:0]in;

mux_3x8 mux( .out(out), .in(in), .sel(sel) );

initial begin

$monitor(sel,in,out);

sel=3'b000;

in=8'b10111011;

end

always #20 sel=sel+3'b001;

endmodule

Simulation output Waveform window: Displays output waveform for verification:


DEMULTIPLEXER:

Block diagram logic Diagram Truth table:


Dataflow Model BehaviouralModel Structural Model

module demux18df(in,s,y);

input in; input [2:0] s;

output reg [7 :0] y;

assign y[0] = in & s[0] & s[1] & s[2];

assign y[1] = in & (~s[0]) & s[1] &

s[2];

assign y[2] = in & s[0] & (~s[1]) &

s[2];

assign y[3] = in & (~s[0]) &( ~s[1]) &

s[2];

assign y[4] = in & s[0] & s[1] &

(~s[2]);

assign y[5] = in & (~s[0]) & s[1] &

(~s[2]);

assign y[6] = in & s[0] & (~s[1]) &

(~s[2]);

assign y[7] = in & (~s[0]) & (~s[1]) &

(~s[2]);

endmodule

module

demux18beh(in, s, y);


output reg [7 :0] y ;

always@(in,s)

begin

y=8'd0;

case(s)

3'd0:y[0]=in;

3'd1:y[1]=in;

3'd2:y[2]=in;

3'd3:y[3]=in;

3'd4:y[4]=in;

3'd5:y[5]=in;

3'd6:y[6]=in;

default:y[7]=in;

endcase

end

endmodule

module demux18str(in,s,y);


output reg [7 :0] y;

and g1(y[0],in,s[0],s[1],s[2]);

and g2(y[1],in,(~s[0]),s[1],s[2]);

and g3(y[2],in,s[0],(~s[1]),s[2]);

and

g4(y[3],in,(~s[0]),(~s[1]),s[2]);

and g5(y[4],in,s[0],s[1],(~s[2]));

and

g6(y[5],in,(~s[0]),s[1],(~s[2]));

and

g7(y[6],in,s[0],(~s[1]),(~s[2]));

and

g8(y[7],in,(~s[0]),(~s[1]),(~s[2]));

endmodule


Test Bench Code:

module testmodule;

// Inputs

reg in;

reg s;

// Outputs

wire y;

// Instantiate the Unit Under Test (UUT)

Demultiplexer uut (.in(in),.s(s),.y(y));

initial begin

// Initialize Inputs

in = 0; s = 3’b0;

// Wait 100 ns for global reset to finish

#100;

in = 1; s = 3’b110;


#100;

// Add stimulus here

end

endmodule

Simulation output Waveform window: Displays output waveform for verification.

RESULT:

Thus the OUTPUT’s of Multiplexers and Demultiplexers are verified by simulating the

VERILOG code.


EXP: 5-DESIGN OF 4-BIT BINARY TO GRAY CONVERTER

AIM:

To develop the source code for binary to gray converter by using VERILOG and obtained

the simulation.





CODE CONVERTER TRUTH TABLE:

(BINARY TO GRAY): (GRAY TO BINARY):

Decimal Binary input Gray output

0 0000 0000

1 0001 0001

2 0010 0011

3 0011 0010

4 0100 0110

5 0101 0111

6 0110 0101

7 0111 0100

8 1000 1100

9 1001 1101

10 1010 1111

11 1011 1110

12 1100 1010

13 1101 1011

14 1110 1001

15 1111 1000

Decimal Gray input Binary output

0 0000 0000

1 0001 0001

2 0010 0011

3 0010 0011

4 0110 0100

5 0111 0101

6 0101 0110

7 0100 0111

8 1100 1000

9 1101 1001

10 1111 1010

11 1110 1011

12 1010 1100

13 1011 1101

14 1001 1110

15 1000 1111


LOGIC DIAGRAM BINARY TO GRAY:

LOGIC DIAGRAM GRAY TO BINARY:

Verilog Code for Binary to Gray code conversion:


module b2g(bin,gray);

input [3:0] bin;

output [3:0] gray;

xor (gray[0],bin[0],bin[1]),

(gray[1],bin[1],bin[2]),

(gray[2],bin[2],bin[3]);

assign gray[3]=bin[3];

end module

module bin2gray

(input [3:0] bin,

output [3:0] gray);

//xor gates.

assign gray[3] = bin[3];

assign gray[2] = bin[3] ^ bin[2];



endmodule

module

binarytogray(bin,gray);

input[3:0]bin;

output reg [3:0]gray;

always@(bin)

begin

gray[3]<=bin[3];

gray[2]<=bin[3]^bin[2];



end

endmodule


Behavioral Model Behavioral Model

module binary_to_gray ( bin ,gray );

output [3:0] gray ;

reg [3:0] gray ;

input [3:0] bin ;

wire [3:0] bin ;

always @ (bin) begin

if (bin==0)

gray = 0;

else if (bin==1) gray = 1;














else

gray = 8;

end

endmodule

module Binary_to_Gray ( bin ,gray );

output [3:0] gray ;

reg [3:0] gray ;

input [3:0] bin ;

wire [3:0] bin ;

always @ (bin) begin

case (bin)

0 : gray = 0;

1 : gray = 1;

2 : gray = 3;

3 : gray = 2;

4 : gray = 6;

5 : gray = 7;

6 : gray = 5;

7 : gray = 4;

8 : gray = 12;

9 : gray = 13;

10 : gray = 15;

11 : gray = 14;

12 : gray = 10;

13 : gray = 11;

14 : gray = 9;

default : gray = 8;

endcase

end

endmodule

Verilog Code for Gray code to Binary conversion:


module

GTBmod(gray, bin);

input [3:0]gray;

output [3:0]bin;

assign bin[3]=gray[3];

xor(bin[2],bin[3],gray[2]);

xor(bin[1],bin[2],gray[1]);

xor (bin[0],bin[1],gray[0]);

endmodule

module gray2bin

(input [3:0] gray,output [3:0] bin);

assign bin[3] = gray[3];

assign bin[2] = gray[3] ^ gray[2];

assign bin[1] = gray[3] ^ gray[2] ^ gray[1];

assign bin[0] = gray[3] ^ gray[2] ^ gray[1]

^ gray[0];

module

graytobinary(gray,bin);

input [3:0] gray;

output reg [3:0] bin;

always@(gray)

begin

bin[3]<=gray[3];

bin[2]<=bin[3]^gray[2];



end

end module


Behavioral Model Behavioral Model

module Gray_to_binary ( gray ,bin );

output [3:0] bin ;

reg [3:0] bin ;

input [3:0] gray ;

wire [3:0] gray ;

always @ (gray) begin

case (gray)

0 : bin = 0;

1 : bin = 1;

2 : bin = 3;

3 : bin = 2;

4 : bin = 7;

5 : bin = 6;

6 : bin = 4;

7 : bin = 5;

8 : bin = 15;

9 : bin = 14;

10 : bin = 12;

11 : bin = 13;

12 : bin = 8;

13 : bin = 9;

14 : bin = 11;

default : bin = 10;

endcase

end

endmodule

module GRAY_to_Binary ( gray ,bin );

output [3:0] bin ;

reg [3:0] bin ;

input [3:0] gray ;

wire [3:0] gray ;

always @ (gray) begin

if (gray==0) bin = 0;

else if (gray==1) bin = 1;














else

bin = 10;

end


Test Bench Code:

module tb();

reg [3:0] bin;

wire [3:0] gray,bin_out;

// instantiate the unit under test's (uut)

bin2gray uut1(bin,gray);

gray2bin uut2(gray,bin_out);

// stimulus

always

begin

bin <= 0; #10;

bin <= 1; #10;

bin <= 2; #10;

bin <= 3; #10;

bin <= 4; #10;

bin <= 5; #10;

bin <= 6; #10;

bin <= 7; #10;

bin <= 8; #10;

bin <= 9; #10;

bin <= 10; #10;

bin <= 11; #10;

bin <= 12; #10;

bin <= 13; #10;

bin <= 14; #10;

bin <= 15; #10;

#100;

$stop;

end

endmodule

Simulation output Waveform window: Displays output waveform for verification.

RESULT:

Thus the OUTPUT’s of binary to gray converter are verified by simulating the VERILOG

code.


EXP 6:4-BIT COMPARATOR

AIM:

To develop the source code for 4-Bit comparator by using VERILOG and obtained the

simulation.





4-bit comparator Block diagram:

4-bit comparator logic Diagram:


4-bit comparator Truth table:

COMPARING INPUTS OUTPUT

A3, B3 A2, B2 A1, B1 A0, B0 A > B A < B A = B

A3 > B3 X X X H L L

A3 < B3 X X X L H L

A3 = B3 A2 >B2 X X H L L

A3 = B3 A2 < B2 X X L H L

A3 = B3 A2 = B2 A1 > B1 X H L L

A3 = B3 A2 = B2 A1 < B1 X L H L

A3 = B3 A2 = B2 A1 = B1 A0 > B0 H L L

A3 = B3 A2 = B2 A1 = B1 A0 < B0 L H L

A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L L

A3 = B3 A2 = B2 A1 = B1 A0 = B0 L H L

A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L H

H = High Voltage Level, L = Low Voltage, Level, X = Don’t Care



module comparator_4bit ( a ,b

,equal ,greater ,lower );

output equal ;

output greater ;

output lower ;

input [3:0] a ;

input [3:0] b ;

module comparator_4bit ( a ,b


output equal ;

output greater ;

output lower ;

input [3:0] a ;

input [3:0] b ;

assign equal = (a==b) ? 1 : 0;

assign greater = (a>b) ? 1 : 0;

assign lower = (a<b) ? 1 : 0;

endmodule

or

module Compare1 (( a ,b


output equal ;

output greater ;

output lower ;

input [3:0] a ;

input [3:0] b ;

assign Equal=(A&B)|(~A&~B);

assign greater = (A & ~B);

assign lower = (~A & B);

endmodule

module comparator ( a ,b


output reg equal ;

output reg greater ;

output reg lower ;

input [3:0] a ;

input [3:0] b ;

always @ (a or b) begin

if (a<b) begin

equal = 0;

lower = 1;

greater = 0;

end

else if (a==b) begin

equal = 1;

lower = 0;

greater = 0;

end else begin

equal = 0;

lower = 0;

greater = 1;

end

end

endmodule


Test Bench Code:

module comparator_tst;

reg [3:0] a,b;

wire eq,lt,gt;

comparator DUT (a,b,eq,gt,lt);

initial

begin

a = 4'b1100;

b = 4'b1100;

#10;

a = 4'b0100;

b = 4'b1100;

#10;

a = 4'b1111;

b = 4'b1100;

#10;

a = 4'b0000;

b = 4'b0000;

#10;

$stop;

end

endmodule


RESULT:

Thus the OUTPUT’s of 4-bit comparator is verified by simulating the VERILOG code.


EXP 7 : DESIGN OF FULL ADDER USING THREE MODELING STYLES

AIM:

To develop the source code for full adder using three modeling styles by using VERILOG

and obtained the simulation.





FULL ADDER:

BLOCK DIAGRAM: LOGIC DIAGRAM: TRUTH TABLE:

full adder using half adder :

module full_adder_join(fsum, fcarry_out, a, b, c);

input a, b, c;

output fsum, fcarry_out;

wire half_sum_1, half_carry_1, half_carry_2;

half_adder HA1(half_sum_1, half_carry_1, a, b);

half_adder HA2(fsum, half_carry_2, half_sum_1, c);

or or1(fcarry_out, half_carry_2, half_carry_1);

endmodule

A B C Carry SUM

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1




module fa(s,co,a,b,ci);

output s,co;

input a,b,ci;

xor1 u1(s,a,b,ci);

and1 u2(n1,a,b);

and1 u3(n2,b,ci);

and1 u4(n3,a,ci);

or1 u5(co,n1,n2,n3);

endmodule

module fulladder

(input A,input B,input cin,

output sum,output carry);

assign {cout,A} = cin + b + a;

endmodule

or

module fulladder(a_in, b_in,

c_in, sum, carry);

input a_in, b_in,c_in;

output sum, carry;

assign sum = a_in^b_in^c_in;

assign carry = (a_in & b_in) |

(b_in & c_in) | (a_in & c_in);

endmodule

module fulladder(abc, sum,

carry);

input [2:0] abc;

output sum,carry;

reg sum,carry;

always@(abc)

begin

case (abc)

3’b000:begin sum=1’b0;

carry=1’b0;end


carry=1’b0;end


carry=1’b0;end


carry=1’b1;end


carry=1’b0end


carry=1’b1;end


carry=1’b1;end


carry=1’b1;end

endcase

end

endmodule


Test Bench Code:

module fullAdder_tb;

reg In1;

reg In2;

reg Cin;

wire Sum;

wire Cout;

reg [2:0] i = 3'd0; //Temporary looping variable

fullAdder uut ( .In1(In1), .In2(In2), .Cin(Cin), .Sum(Sum), .Cout(Cout) );

initial begin

In1 = 1'b0; In2 = 1'b0; Cin = 1'b0;


#100;

for = 0; i < 8; i = i + 1'b1)begin

{In1,In2,Cin} = {In1,In2,Cin} + 1'b1;

#20;

end

end

endmodule


RESULT:

Thus the OUTPUT’s of full adder using three modeling styles are verified by simulating

the VERILOG code.


EXP 8 : DESIGN OF FLIP FLOPS (SR,JK,D,T).

AIM:

To develop the source code for FLIP FLOPS by using VERILOG and obtained the

simulation.





SR FLIPFLOP:




module sr_st(s,r,q,q_n);

module sr_beh(s,r,q,q_n);

input s, r;

output q, q_n;

or g1(q_n,~s,~q); regq, q_n;

or g2(q,~r,~q_n);

endmodule

modulesr_df (s, r, q, q_n);

input s, r;

output q, q_n;

assignq_n = ~(s | q);

or g1(q_n,~s,~q);

assign q = ~(r | q_n); or endmodule

module sr_beh(s,r,q,q_n);

input s, r;

output q, q_n;

regq, q_n;

always@(s,r)

begin

q,n = ~(s|q);

assign q = ~(r | q_n);

endmodule


Verilog testbench program for SR-flip flop :

module srff_tb;

reg s,r,clk,rst;

wire q,qb;

srff srflipflop(.s(s),.r(r),.clk(clk),.rst(rst),.q(q),.qb(qb));

initial

begin

clk=0;

s = 0; r = 0;

#5 rst = 1; #30 rst = 0;

$monitor($time, "\tclk=%b\t ,rst=%b\t, s=%b\t,r=%b\t, q=%b\t,

qb=%b",clk,rst,s,r,q,qb);

#100 $finish;

end

always #5 clk = ~clk;

always #30 s = ~s;

always #40

endmodule


JK FLIPFLOP:




Behavioral Modelling Dataflow Modelling Structural Modelling

module jk(q,q1,j,k,c); output

q,q1; input j,k,c; reg q,q1;

initial begin q=1'b0; q1=1'b1;

end always @ (posedge c)

begin case({j,k})

{1'b0,1'b0}:begin q=q; q1=q1;

end{1'b0,1'b1}: begin q=1'b0;

q1=1'b1; end {1'b1,1'b0}:begin

q=1'b1; q1=1'b0; end

{1'b1,1'b1}: begin q=~q;

q1=~q1; end endcase end

endmodule

module jkflip_df (j,k,q,qn);

input j,k,q;

output qn;

wire w1,w2;

assign w1=~q;

assign w2=~k;

assign qn=(j & w1 | w2 &

q);

endmodule

module jkflip_st(j,k,q,qn);

input j,k,q;

output qn;

and g1(w1,j,~q);

and g2(w2,~k,q);

or g3(qn,w1,w2);

endmodule

Verilog testbench program for JK-flip flop :

module JKFF_tb;

reg J,K,clk,rst;

wire Q;

JKFF JKflipflop(.J(J),.K(K),.clk(clk),.rst(rst),.Q(Q));

initial

begin

clk=0; J = 0; K = 0;

#5 rst = 1;

#30 rst = 0;

$monitor($time, "\tclk=%b\t ,rst=%b\t, J=%b\t,K=%b\t, Q=%b",clk,rst,J,K,Q);

#100 $finish;

end


always #30 J = ~J;

always #40 K = ~K;

endmodule



D FLIPFLOP:



Behavioral Modelling Dataflow Modelling Structural Modelling

Module dff_async_reset( data, clk, reset ,q );

input data, clk, reset ; output q; reg q; always @ ( posedgeclk or negedge reset)

if (~reset) begin q <= 1'b0;

end else begin

q <= data; end

endmodule

module

dff_df(d,c,q,q1); input d,c;

output q,q1; assign w1=d&c;

assign w2=~d&c; q=~(w1|q1);

q1=~(w2|q); endmodule

module

dff_df(d,c,q,q1); input d,c;

output q,q1; and g1(w1,d,c);

and g2(w2,~d,c); nor g3(q,w1,q1);

nor g4(q1,w2,q); endmodule

Verilog testbench program for D-flip flop :

module Stimulus_v;

reg Reset; reg Clock; reg d;

wire q;

DFF uut (.Clock(Clock),.Reset(Reset),.d(d),.q(q));

always

#1 Clock=~Clock;

initial begin

Clock=0; Reset=0;d=0;

#2 Reset=0;d=1; #2 d=0;

#2 Reset=1; d=1; #2 d=0; #2 d=1;

#2 Reset=0; d=0; #1;

#2 $stop; end

endmodule



T FLIPFLOP:




module t_st(q,q1,t,c);

output q,q1;

input t,c;

wire w1,w2;

and g1(w1,t,c,q);

and g2(w2,t,c,q1);

nor g3(q,w1,q1);

nor g4(q1,w2,q);

endmodule

module t_df(q,q,1,t,c);

output q,q1;

input t,c;

wire w1,w2;

assign w1=t&c&q;

assign w2=t&c&q1;

assign q=~(w1|q1);

assign q1=~(w2|q);

endmodule

module t_beh(q,q1,t,c);

output q,q1;

input t,c;

reg q,q1;

initial begin

q=1'b1;

q1=1'b0;

end

always @ (c)

begin

if(c)

begin

if (t==1'b0) begin q=q;

q1=q1; end

else begin q=~q; q1=~q1;

end

end

end

endmodule


Verilog testbench program for D-flip flop :

module Stimulus_v;

reg Clock, Reset, t;

wire q;

TFF uut (.Clock(Clock),.Reset(Reset),.t(t),.q(q));

always

#1 Clock=~Clock;

initial begin

Clock=0;

Reset=0;

t=0;

#2 Reset=0; t=1;

#2 t=0;

#2 Reset=1; t=1;

#2 t=0;

#2 t=1;

#2 Reset=0; t=0;

#1;

#2 $stop; end

endmodule


RESULT:

Thus the OUTPUT’s of Flip Flops are verified by simulating the VERILOG code.


EXP 9 : DESIGN OF 4-BIT BINARY COUNTER AND BCD COUNTER

AIM:

To develop the source code for 4-bit binary counter and BCD counter by using VERILOG

and obtained the simulation.





4-bit Binary counter diagram:

Verilog program for 4 bit binary counter:

module counter (out, enable, clk,reset);

output [3:0] out;//----------Output Ports------

input enable, clk, reset; ////--- Input Ports----

reg [3:0] out;//---Internal Variables--------

always @(posedge clk)

if (reset) begin

out <= 4'b0 ;

end else if (enable) begin

out <= out + 1’b1;

end

endmodule


Verilog testbench program for 4 bit binary counter

module counter_tb;

reg clk, reset, enable;

wire [3:0] out;

counter U0 ( .clk (clk), .reset (reset), .enable (enable),.out (out));

initial begin

clk = 0; enable = 0;

reset = 1;

#5 enable = 1;

#5 reset = 0;

#100 $finish;

end

always #5 clk = !clk;

initial begin

$display("\t\ttime,\tclk,\treset,\tenable,\tout");

$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,enable,out);

end

endmodule


BCD COUNTER LOGIC DIAGRAM:


Verilog program BCD counter :

module counter10 (out , enable , clk , reset);

output [3:0] out;

input enable, clk, reset;

reg [3:0] out;


if (reset) begin

out <= 4'b0 ;

end else if (enable) begin

out <= (out + 1)%10;

end

endmodule

Verilog testbench program BCD counter :

module counter10_tb;

reg clk, reset, enable;

wire [3:0] out;

counter10 U0 (.clk(clk), .reset (reset), .enable (enable), .out (out) );

initial begin

clk = 0;

reset = 1;

enable = 0;

#5 enable = 1;

#5 reset = 0;

#1000 $finish;

end

always #5 clk = !clk;

initial begin

end

endmodule


RESULT:

Thus the OUTPUT’s of 4-bit counter and BCD COUNTER using three modeling styles are

verified by synthesizing and simulating the VERILOG code


EXP 10: FINITE STATE MACHINE DESIGN

AIM:

To develop the source code for finite state machine design by using VERILOG and

obtained the simulation





FSM DESIGN:

Fig. 1: Moore State Machine

Fig. 2: Mealy State Machine


Sequence detector 1011:

VERILOG SOURCE CODE: Moore FSM Verilog code:

module m1011( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;

always @( posedge clk, rst )

begin

if( rst )

state <= 2'b00;

else

begin

case( {state,inp} )

3'b000: begin

state <= 2'b00;

outp <= 0;

end

3'b001: begin

state <= 2'b01;

outp <= 0;

end

3'b010: begin

state <= 2'b10;

outp <= 0;

end

3'b011: begin

state <= 2'b01;

outp <= 0;

end

3'b100: begin

state <= 2'b00;

outp <= 0;

end

3'b101: begin

state <= 2'b11;

outp <= 0;

end

3'b110: begin

state <= 2'b10;

outp <= 0;

end

3'b111: begin

state <= 2'b01;

outp <= 1;

end

endcase

end

end

endmodule


Mealy FSM Verilog Code:

module mealy1011(clk,rst,inp,outp);

input clk,rst,inp;

output reg outp;

reg [1:0]state;

parameter S0=0, S1=1, S2=2, S3=3;

always @(posedge clk or posedge rst)

if(rst)

state<=S0;

else

case(state)

S0: if(inp)

state<=S1;

else

state<=S0;

S1: if(inp)

state<=S1;

else

state<=S2;

S2: if(inp)

state<=S3;

else

state<=S0;

S3: if(inp)

state<=S1;

else

state<=S2;

endcase

always @(state,inp)

case(state)

S0: if(inp)

outp<=0;

else

outp<=0;

S1: if(inp)

outp<=0;

else

outp<=0;

S2: if(inp)

outp<=0;

else

outp<=0;

S3: if(inp)

outp<=1;

else

outp<=0;

endcase

endmodule

Verilog test bench program :

module

tb_Sequence_Detector_Moore_FSM_Verilog;

reg clk, rst, inp;

wire outp;

// Instantiate using Moore FSM

module m1011 uut ( .inp(inp), .clk(clk),

.rst(rst), .outp(outp) );

initial begin

clk = 0;

forever #5 clk = ~clk;

end

initial begin

// Initialize Inputs

inp = 0; rst = 1;

// Wait 100 ns for global rst to finish

#30; rst = 0; #40;

inp = 1; #10;

inp = 0; #10;

inp = 1; #20;

inp = 0; #20;

inp = 1; #20;

inp = 0;

// Add stimulus here

end

endmodule



RESULT: Thus the OUTPUT’s of finite state machine design is verified by simulating the

VERILOG code.


ADDITIONAL EXPERIMENTS BEYOND JNTU SYLLABUS

Exp 1. Left Shift Register

AIM: To Implement Left Shift Register using Verilog HDL and download on to the FPGA

kit.





Shift Register LOGIC DIAGRAM

Verilog HDL CODE:

module leftshift (clk, si, so);

input clk,si;

output so;

reg [3:0] tmp;


begin

tmp <= tmp << 1;

tmp[0] <= si;

end

assign so = tmp[3];

endmodule

Truth Table

Shift

Pulse D C B A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 1

3 0 1 1 1

4 1 1 1 1


TEST BENCH:

module stimulus;

reg clk ;

reg si;

wire so;

leftshift s1 (.clk(clk),.s_in(si),.so(so) );

initial begin

clk = 0;si = 0;

#10 si=1’b1;

#10 si=1’b0;

#10 si=1’b0;

#10 si=1’b1;

#10 si=1’b0;

#10 si=1’bx;

end


initial #150 $stop;

endmodule

WAVE FORMS:

RESULT: Hence Left shift register is implemented usig VHDL & downloaded on to the

FPGA kit.


Exp 2 . Design of Seven Segment Display

AIM: To Design and implement seven segment led display usig VHDL.





DESIGN:

Logic Symbol :


Truth Table:

Binary inputs Seven Segment Display Output

b3 b2 b1 b0 d6 d5 d4 d3 d2 d1 d0

0 0 0 0 0 1 1 1 1 1 1

0 0 0 1 0 0 0 0 1 1 0

0 0 1 0 1 0 1 1 0 1 1

0 0 1 1 1 0 0 1 1 1 1

0 1 0 0 1 1 0 0 1 1 0

0 1 0 1 1 1 0 1 1 0 1

0 1 1 0 1 1 1 1 1 0 1

0 1 1 1 0 0 0 0 1 1 1

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 0 0 1 1 1

1 0 1 0 1 1 1 0 1 1 1

1 0 1 1 1 1 1 1 1 0 0

1 1 0 0 0 1 1 1 0 0 1

1 1 0 1 1 0 1 1 1 1 0

1 1 1 0 1 1 1 1 0 0 1

1 1 1 1 1 1 1 0 0 0 1

X X X X 0 0 0 0 0 0 0

VHDL CODE:

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_unsigned.all;

Use ieee.std_logic_arith.all;

entity sevenseg is

port(bin : in std_logic_vector(3 downto 0); ---Input binary value from 0 to 15---

dispcom : out std_logic;

disp : out std_logic_vector(6 downto 0)); ---Seven segment display for displaying the hex

value---

end sevenseg;


architecture Behavioral of sevenseg is

begin

dispcom <= '0'; --for common cathode seven segment display

-------------------- SEVEN SEGMENT DISPLAY MODULE --------------------

process(bin)

begin

case bin is

when "0000" =>disp <= "0111111"; --0--

when "0001" =>disp <= "0000110"; --1--

when "0010" =>disp <= "1011011"; --2--

when "0011" =>disp <= "1001111"; --3--

when "0100" =>disp <= "1100110"; --4--

when "0101" =>disp <= "1101101"; --5--

when "0110" =>disp <= "1111101"; --6--

when "0111" =>disp <= "0000111"; --7--

when "1000" =>disp <= "1111111"; --8--

when "1001" =>disp <= "1100111"; --9--

when "1010" =>disp <= "1110111"; --a--

when "1011" =>disp <= "1111100"; --b--

when "1100" =>disp <= "0111001"; --c--

when "1101" =>disp <= "1011110"; --d--

when "1110" =>disp <= "1111001"; --e--

when "1111" =>disp <= "1110001"; --f--

when others =>disp <= "0000000";

end case;

end process;

end Behavioral;


WAVE FORMS:

RESULT: Hence Seven Segment display is designed.

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