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TITLE

- Basic Logic Design and I/O Interface with DE2 Board

OBJECTIVE

1. To familiarize with schematic-based design flow for FPGA implementation by using logicgates and hierarchical modelling.

EQUIPMENT REQUIRED

1. Personal computer running Windows XP/ Windows Vista/ Windows 7 with minimum of1GB RAM with USB ports and installed with Altera Quartus II software.

2. Altera DE2 Development and Education Board, with 9V DC power supply and USB cable.

INTRODUCTION

The introduction to Altera Quartus II lab will introduce the design implementing in FPGAusing Altera DE2 Board by using schematic entry method to create designs. The design must be

compiled to make sure that the functionality of the design by simulation and timing. Once the

design conforms to the requirements, it can be implementing in the FPGA on the Altera DE2

board.

Once the lab was completed student should able to:

1.

Navigate comfortably through the Alteras schematic design-entry environment.2. Compile, debug, test and simulate the design.3. Download and run the design on a DE2 board

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PROCEDURES

Part A: Creating New Project

1. Create the New Project Wizard, name the project and top-level entity as adder4_de2.2. In page 3 of New Project Wizard, at the Family list, Cyclone II was selected and make

sure the Target device was follows the following list:

a. Package FBGAb. Pin Count 672c. Speed Grade 6

3. Click the button Finish if the flows in order to create the New Project Wizard. Then,create the new BDF called adder4_de2.bdf.

Part B: Enter an adder4 symbol that generated by Mega Wizard Plug-In Manager

1. Double click on empty space in Block editor window.2. Then, Mega Wizard Plug-In Manager was clicked. At the first page, create the new

megafunction. After that, finish the step and the new symbol of adder were appears.

Part C: Create HDL Design File and Symbol File

1. Select the Block Tool at schematic window and place at the empty space. Then, renamethe block to seven_seg block.

2. The properties of the block was changed by insert the input and output that representas seg_in and seg_out.

3. Select the Verilog HDL as the type of the block created. And the design was saved byusing the adder4_de2.v filename. Then creating block was finished.

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Part D: Connecting the Adder to the Seven-Segment Decoder

1. The adder was connected as figure below.

Figure 1.1: Adder Schematic

Part E: Pin Assignment

1. Invoke Start Analysis and Synthesis from the toolbars to generate the project database.The design file must be compiling to detect the semantic error, synthesis the logic and

generate a project database.

2. The Pin Planner was invoked by select the Assignment>Pin on the schematic windows.3. The figure below shows the all pin that has been assign.

Figure 1.2: Wire bond

VCCpin_name INPUT

VCCpin_name2 INPUT

VCCpin_name3 INPUT

pin_name4OUTPUT

pin_name5OUTPUT

A

B

A+B

dataa[3..0]

datab[3..0]

cin

result[3..0]

cout

adder4

inst

seven_seg

inst1

seg_in[3..0] INPUT

seg_out[6..0] OUTPUT

I/O Type

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Figure 1.3: Pin Assignment

4. Perform pin assignment to assign the two 4-bit input and 1-bit carry in to the toggleswitches on the DE2 board.

5. For the each connected directly to a pin on the Cyclone II FPGA.

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RESULT AND ANALYSIS

1. Coding for adder4_de2

// Module Declaration

module seven_seg

(

// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!

seg_in, seg_out

// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!

);

// Port Declaration

// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!

input [3:0] seg_in;

output [6:0] seg_out;

// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

reg [6:0] seg_out;

always@*

case (seg_in)

0: seg_out = 7'b1000000;

1: seg_out = 7'b1111001;

2: seg_out = 7'b0100100;

3: seg_out = 7'b0110000;

4: seg_out = 7'b0011001;

5: seg_out = 7'b0010010;

6: seg_out = 7'b0000010;

7: seg_out = 7'b1111000;

8: seg_out = 7'b0000000;

9: seg_out = 7'b0010000;

10: seg_out = 7'b0001000;

11: seg_out = 7'b0000011;

12: seg_out = 7'b1000110;

13: seg_out = 7'b0100001;

14: seg_out = 7'b0000110;

15: seg_out = 7'b0001110;

default: seg_out = 7'b1111111;

endcase

endmodule

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2. Block Diagram for the adder

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3. Coding for Blinking LED

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4. Block Diagram for Blinking LED

DISCUSSION

1. Based on the laboratory ECAD, student was able to familiarize with the Altera Quartus IIsoftware in how to create a new megafunction, use and download to the DE2 Board.

2. This is the tools that able to prove the theory of carry out which produce by summationof two (2) 4-bit input adders. The design that has been created by using the Quartus

Software was easier by generated by the MegaWizard Plug-In Manager.

3. A design was successfully created to make an LED to blink at a certain visible rate. Thishas been achieved by implementing a binary counter, which can be used as a frequency

divider. One of the ways to obtain a counter is by using the MegaWizard Plug-In

Manager. The most significant bit of the counter has been connected to the LED output.

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CONCLUSION

Overall of the laboratory simulation, the ECAD experiment was successfully achieves the

objectives that to make sure the student able to familiarize using the Altera Quartus II software.

The experiment basically needs the understanding of logic functionality. This is very

important to ensure the output displayed by the Altera DE2 Board was correct. Hence, it had

made the comparing result process between the theoretical and experimental easier.

Therefore, conclusions of result can be made. A few mistakes which had helped in understand

the details of Quartus II design process.

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REFERENCES

Books

Laboratory Manual Digital System Design ( Second Edition, Frank Vahid ) Fundamental of Electric Circuits ( Fourth Edition, Chapter 14, Alexander Sadiku )

Lecturer

Pn. Noorlina Bt. Mohd Zainuddin

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