Lab 2 Phase Detector(1)

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Stony Brook University ESE 324 Electronics Laboratory CDepartment of Electrical and Computer Engineering Spring 2012

Lab 2: XOR Based Phase Detector DesignObjectives

1) Design a simple XOR based phase detector.2) Understand the fundamental design constraints of a phase detector such as maximum

operating speed, and dead zone.3) Design two different implementations of a phase detector.4) Understand the differences between a transmission gate based phase detector and static

CMOS based phase detector.

Background

Phase detector is a circuit that produces an output signal whose average value is linearlyproportional to the phase difference between the two inputs. Referring to the following figure,the slope of the line is referred to as the gain of the phase detector. The output is voltage andinput is a phase difference so the gain is measured in V/rad.

A phase detector is a highly important circuit block for a variety of applications including motorcontrol and telecommunication systems. A simple phase detector can be implemented as an XORgate. As shown in the figure below, the width of the output pulse varies as the phase differencebetween the inputs varies. The average DC value of the output signal is proportional to the phasedifference of the input signals.


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Preliminary Lab

Read the laboratory document carefully before coming to the lab. Understand the requirementsof each step. It will save you time if you setup the first schematic before coming to the lab.

Parts:

Two/three CD 4007s100 pF capacitor10 pF capacitor


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Laboratory Experiment

Part 1

Figure 1

1) Build an XOR based phase detector using transmission gates, as shown in Figure 1. Youwill use four NMOS and four PMOS transistors. To build this circuit, you will need twoCD 4007s. Remember to connect pin 14 to V DD and pin 7 to V SS for both ICs. Note thatVDD = 5V and V SS = 0 V. Obtain the truth table of the XOR gate by filling the tablebelow and verify that the gate functions correctly. If the circuit does not initially work asexpected, debug your circuit by probing different nodes and find the node that has anunexpected voltage.

A B V out

VSS VSS VDD VSS

VSS VDD

VDD VDD


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Part 2

In this part, you will measure several different propagation delays in your phase detector. Startwith both inputs set to V SS. The output should also be at V SS. Then, provide a 1 kHz square waveto input A from 0 to 5 volts, as shown below:

1) Record the output waveform. Then, measure low-to-high propagation delay (t LH )A of theoutput when the input A changes from V SS to V DD . Also, measure the high-to-low

propagation delay (t HL )A of the output when the input A changes from V DD to V SS.

2) In the second step, set input A to zero and provide a 1 kHz square wave from 0 to 5 voltsto input B. Then, measure low-to-high propagation delay (t LH )B of the output when theinput B changes from V SS to V DD . Also measure the high-to-low propagation delay (t HL )Bof the output when the input B changes from V DD to V SS.

Remember to measure the propagation delay between the two points that correspond to 50%transition of the signal (check background section).

Insert the values into the table below.

3) By looking at the schematic and considering the voltage transitions, describe why thedelays are different. Explain why (t LH )B is relatively higher than (t LH )A.

Delay(t LH )A (t HL )A (t LH )B (t HL )B

Part 3

1) Connect input A to V DD . Provide a square wave (from 0 to 5 volts) to input B with fourdifferent frequencies as follows:

f 1 = 50 kHz, f 2 = 500 kHz, f 3 = 800 kHz, f 4 = 3 MHz.


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Record output waveform for each frequency and measure the current drawn from theprimary power supply for each frequency. Fill in the table below and plot a graph showing therelationship between frequency versus current.

Signal frequency at input B Total current drawn from V DD

50 kHz500 kHz800 kHz3 MHz

Remember that when one of the inputs is connected to V DD, the phase difference between thetwo signals is equal to the inverse of the second input. Comment on the behavior of the outputsignal as the frequency is increased.

2) Typically, every phase detector has a highest operating frequency beyond which thephase detector fails to reliably detect the phase. The condition to determine the maximum

operating frequency may vary depending upon the application. Considering the conditiondescribed in the background section, determine the maximum operating frequency fortwo cases (remember that the input A is connected to V DD):

Case 1: Duty cycle of the square wave at input B is 50%

Case 2: Duty cycle of the square wave at input B is 80%

For both cases, record your output waveform. Determine the maximum frequency and fill inthe table below. Note that you can adjust the duty cycle of the signal by using functiongenerator. Explain why the maximum frequency is reduced when the duty cycle increases.

Duty cycle of the square wave at input B Maximum frequency50%80%

Part 4

1) In this part, change the load capacitor from 100 pF to 10 pF and fill in the tables below byrepeating the same steps as above

Delay(t LH )A (t HL )A (t LH )B (t HL )B


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Signal frequency at input B Total current drawn from V DD 50 kHz

500 kHz800 kHz3 Mhz


2) Explain how the capacitor affects the delay, maximum operating speed, and overallcurrent drawn from the power supply.

Part 5

Figure 2

In this part, you will design another XOR based phase detector. However, instead of usingtransmission gates, you will adopt a static CMOS implementation. Build the circuit shown inFigure 2 using CD4007 ICs.

1) Obtain the truth table of the XOR gate by filling the table below and verify that the gatefunctions correctly. If the circuit does not initially work as expected, debug your circuitby probing different nodes and find the node that has an unexpected voltage.


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A B V out

VSS VSS

VDD VSS

VSS VDD

VDD VDD

Following the similar steps as you did for the transmission gate based XOR, fill in the tablesbelow.

2) Measure different propagation delays

Delay(t LH )A (t HL )A

(t LH )B (t HL )B

3) Vary the frequency and record output waveform for each frequency. Measure the currentdrawn from the primary power supply for each frequency. Plot a graph showing therelationship between frequency versus current.

Signal frequency at input B Total current drawn from V DD 50 kHz

500 kHz800 kHz

3 MHz

4) Determine the maximum operating frequency at two different duty cycles. Record theoutput waveform for both values. Remember the condition described in the backgroundsection.


Part 6:

1) Change the output capacitor from 100 pF to 10 pF and repeat the same steps and fill intables below:

Delay(t LH )A (t HL )A (t LH )B


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(t HL )B

Signal frequency at input B Total current drawn from Vdd

50 kHz500 kHz800 kHz3 MHz


1) Explain how the capacitor affects the delay, maximum operating speed, and overallcurrent drawn from the power supply when XOR is implemented utilizing CMOS staticlogic.

Part 7

Looking at all of your results, compare the overall performance of transmission gate based phasedetector with static CMOS based phase detector. Compare the number of transistors, speed, andpower consumption.

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Lab 2 Phase Detector(1)