L2-3 Basic digital devices

Embed Size (px)

Citation preview

  • 8/8/2019 L2-3 Basic digital devices

    1/35

    Microprocessors Programming and

    Interfacing

    ES C 263

    Basic digital devices

    Murti KCS

  • 8/8/2019 L2-3 Basic digital devices

    2/35

    Objective

    Review digital electronics needed for MPhardware design.

    Scope

    Gates

    Tri-state logic

    Open collector

    Fan out

    Multiplexers/demultiplexers

  • 8/8/2019 L2-3 Basic digital devices

    3/35

    +5

    V

    5

    1 0 1

    Time

    +5

    V

    5

    Time

    Analog and Digital..

  • 8/8/2019 L2-3 Basic digital devices

    4/35

    Binary Logic

  • 8/8/2019 L2-3 Basic digital devices

    5/35

    Binary variables

    Binary valuesHigh and Low

    True and False

    1 and 0

    Yes or No

    Basic binaryoperations

    AND

    OR

    NOT

  • 8/8/2019 L2-3 Basic digital devices

    6/35

    Register

    1 1X

    1

    0

    1

    1

    1X

    0X

    1X

    1X

    Z=11

    MSB

    LSB

    Z11 XX11

  • 8/8/2019 L2-3 Basic digital devices

    7/35

    AND

    x y z

    0 0 0

    0 1 0

    1 0 0

    1 1 1

    Z=x.y

  • 8/8/2019 L2-3 Basic digital devices

    8/35

    And as gate

    1

  • 8/8/2019 L2-3 Basic digital devices

    9/35

    Masking

    0 0 1 1 1 1 0 0

    0 1 1 0 1 0 1 1

    0 0 1 0 1 0 0 0

    0 0 1 0 0

  • 8/8/2019 L2-3 Basic digital devices

    10/35

    NAND

    x y z

    0 0 1

    0 1 1

    1 0 1

    1 1 0

    YXZ .!

  • 8/8/2019 L2-3 Basic digital devices

    11/35

    OR

    x y z

    0 0 0

    0 1 1

    1 0 1

    1 1 1

    Z=x+y

  • 8/8/2019 L2-3 Basic digital devices

    12/35

    Concatenate data

    0 0 1 1

    1 0 1 1

    0 0 0 0

    0 0 0 0

    1 0 1 10 0 1 1

    1 0 1 1

    0 0 1 1

    0 0 1 1 1 01 1

  • 8/8/2019 L2-3 Basic digital devices

    13/35

    XOR

    x y z

    0 0 0

    0 1 1

    1 0 1

    1 1 0

    YY ..

  • 8/8/2019 L2-3 Basic digital devices

    14/35

    Comparator

    Comparator

    1 0 1 1

    0 0 1 1

    1 0 0 0

  • 8/8/2019 L2-3 Basic digital devices

    15/35

    Inverter

    x z

    0 1

    1 0

  • 8/8/2019 L2-3 Basic digital devices

    16/35

    An inverter circuit

  • 8/8/2019 L2-3 Basic digital devices

    17/35

    TTL gate

  • 8/8/2019 L2-3 Basic digital devices

    18/35

    Inverter

    Ones

    Complement

    01001011 10110100

  • 8/8/2019 L2-3 Basic digital devices

    19/35

    Timing diagram

  • 8/8/2019 L2-3 Basic digital devices

    20/35

  • 8/8/2019 L2-3 Basic digital devices

    21/35

    NAND implementation

    F=AB+CD

  • 8/8/2019 L2-3 Basic digital devices

    22/35

    Wired logic

  • 8/8/2019 L2-3 Basic digital devices

    23/35

    Wired AND

    F=(AB+CD)

    AND or Invert gateAB CD F

    11 X 0

    X 11 0

  • 8/8/2019 L2-3 Basic digital devices

    24/35

    Open collector

    Physical connection

    Wired

    AND logic

    Opencollector gates

    forming a bus

  • 8/8/2019 L2-3 Basic digital devices

    25/35

    Three-state gate

    ENB

    X XY Y

    ENB X Y

    0 X High

    imp (Z)

    1 0 0

    1 1 1

  • 8/8/2019 L2-3 Basic digital devices

    26/35

    Tristate bus

    Active low Activehigh

  • 8/8/2019 L2-3 Basic digital devices

    27/35

    Fan out

    IOH=High level output current

    (max)

    IIH=high level input current

    IOH

    = 400QA

    IIH

    = 40QA

  • 8/8/2019 L2-3 Basic digital devices

    28/35

    Fan out..

    IOL=Low level output current

    (max)

    IIL=Low level input current

    IOL = -16QAIIL

    = -1.6QA

  • 8/8/2019 L2-3 Basic digital devices

    29/35

    Fan out

    )fanoutoutputLLogicfanout,outputHLogicmax(

    ,max_

    !

    !

    IL

    OL

    IH

    OH

    I

    I

    I

    IoutFan

  • 8/8/2019 L2-3 Basic digital devices

    30/35

    Fan out..

    This means that each gate can drive 10 other gates in thesame family without getting out of its guaranteed range ofoperation.

    In cases where more than 10 gates are connected to theoutput of a single gate of this family, the output voltage

    levels will degrade and the gate will slow down.

    Modern MOS logic families have a fan-out of about 50,since each gate must source or sink a current only duringthe transition from H to L or L to H.

  • 8/8/2019 L2-3 Basic digital devices

    31/35

    Multiplexer (2 to 1 line)

  • 8/8/2019 L2-3 Basic digital devices

    32/35

    Multiplexer (4 to 1 line)

  • 8/8/2019 L2-3 Basic digital devices

    33/35

    Multiplexer (8 to 1)

    Note the

    Enableinput

    This isActiveLow

    Output

  • 8/8/2019 L2-3 Basic digital devices

    34/35

    De-multiplexer

  • 8/8/2019 L2-3 Basic digital devices

    35/35

    1 to 8 de multiplexer