L01: Intro, Combinational LogicL21: Virtual Memory II ......Miss Penalty (latency) 33x Miss Penalty (latency) 10,000x SRAM Static Random Access Memory DRAM Dynamic Random Access Memory

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CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II

VirtualMemoryIICSE351Winter2017

https://xkcd.com/1495/


Administrivia

v Lab4dueFriday,howisitgoing?v HW3graded,posted.

v Planforrestofquarter:§ HW4outtoday,dueMon,Mar6.§ Lab5outFridayMar3,dueMonMar13(cut-offMar15).§ Final:Wed,Mar15th,8:30-10:20,here.

• Materialforthewholequarter.Moredetailsnextweek.

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IndirectioninVirtualMemory

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v Eachprocessgetsitsownprivatevirtualaddressspacev Solves:dealingwithsmallphysicalmemory,memory

management,protection,sharing.

Physical memory

Virtual memory

Virtual memory

Process 1

Process n

mapping


VMandtheMemoryHierarchyv Thinkof virtualmemory asarrayofN = 2n contiguousbytesv Pages ofvirtualmemoryareusuallystoredinphysical

memory,butsometimesspilltodisk§ Pagesareanotherunitofalignedmemory(sizeisP = 2p bytes)§ Eachvirtualpagecanbestoredinany physicalpage(nofragmentation!)

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VP0VP1

VP2n-p-1

Virtualmemory

Unallocated

Unallocated

0

2n-1

PP2m-p-1

PhysicalmemoryEmpty

Empty

PP0PP1

Empty

2m-1

0

Virtualpages(V

P's)

Disk

Physicalpages(PP's)

“SwapSpace”

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MemoryHierarchy:Core2Duo

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DiskMainMemory

L2unifiedcache

L1I-cache

L1D-cache

CPU Reg

2B/cycle8B/cycle16B/cycle 1B/30cyclesThroughput:Latency: 100cycles14cycles3cycles millions

~4MB

32KB

~8GB ~500GB

Notdrawntoscale

MissPenalty(latency)

33x

MissPenalty(latency)10,000x

SRAMStaticRandomAccessMemory

DRAMDynamicRandomAccessMemory


VirtualMemory(VM)

v Overviewandmotivationv VMasatoolforcachingv Addresstranslationv VMasatoolformemorymanagementv VMasatoolformemoryprotection

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AddressTranslation

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0:1:

M-1:

Mainmemory

MMU

2:3:4:5:6:7:

Physicaladdress(PA)

Data(int/float)

8: ...

CPU

Virtualaddress(VA)

CPUChip

0x40x4100

MemoryManagementUnit

Howdoweperformthevirtual→ physicaladdresstranslation?


AddressTranslation:PageTables

v CPU-generatedaddresscanbesplitinto:

§ RequestisVirtualAddress(VA),wantPhysicalAddress(PA)§ NotethatPhysicalOffset=VirtualOffset(page-aligned)

v Uselookuptablethatwecallthepagetable (PT)§ ReplaceVirtualPageNumber(VPN)forPhysicalPageNumber(PPN)togeneratePhysicalAddress

§ IndexPTusingVPN:pagetableentry(PTE)storesthePPNplusmanagementbits(e.g.Valid,Dirty,accessrights)

§ Hasanentryforevery virtualpage– why?

VirtualPageNumber PageOffset𝑛-bitaddress:

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v Pagetablesstoredinphysicalmemory§ Toobigtofitelsewhere– managedbyMMU&OS

v Howmanypagetablesinthesystem?§ Oneperprocess

PageTableDiagram

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PageTable(DRAM)

null

null

01

0

01101

Valid PPN/DiskAddrPTE0:0

PTE7:7

PTE1:1PTE2:2PTE3:3PTE4:4PTE5:5PTE6:6

......

Virtualmemory(disk)

VP6

VP3

Virtualpage#

Physicalmemory(DRAM)

PP0

PP3

PP2

PP1

VP1

VP2

VP7

VP4


CPU

PageTableAddressTranslation

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Virtualpagenumber(VPN) Virtualpageoffset(VPO)

Physicalpagenumber(PPN) Physicalpageoffset(PPO)

Virtualaddress(VA)

Physicaladdress(PA)

Valid PPN

Pagetablebaseregister

(PTBR)

PagetablePagetableaddressforprocess

Validbit=0:pagenotinmemory

(pagefault)

Inmostcases,theMMUcanperformthistranslation

withoutsoftwareassistance

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PageHit

v Pagehit: VMreferenceisinphysicalmemory

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PageTable(DRAM)

null

null

01

0

01101

Valid PPN/DiskAddrPTE0

PTE7......

Virtualaddress

Example: Pagesize=4KiB

0x00740bVirtualAddr:

VPN: PPN:

PhysicalAddr:


PP0

PP3

VP1VP2VP7VP4

Virtualmemory(disk)

VP6

VP3


PageFault

v Pagefault: VMreferenceisNOT inphysicalmemory

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PageTable(DRAM)

null

null

01

0

01101


PTE7......


PP0

PP3

VP1VP2VP7VP4

Virtualmemory(disk)

VP6

VP3

Virtualaddress

Example: Pagesize=4KiBProvideavirtualaddressrequest(inhex)thatresultsin thisparticularpagefault:

VirtualAddr:

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v Userwritestomemorylocationv Thatportion(page)ofuser’smemory

iscurrentlyondisk

v Pagefaulthandlermustloadpageintophysicalmemoryv Returnstofaultinginstruction:mov isexecutedagain!

§ Successfulonsecondtry

int a[1000];int main (){

a[500] = 13;}

80483b7: c7 05 10 9d 04 08 0d movl $0xd,0x8049d10

Usercode OSKernelcode

exception:pagefaultCreatepageandloadintomemoryreturns

movl

PageFaultException

handle_page_fault:

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HandlingaPageFaultv Pagemisscausespagefault(anexception)

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PageTable(DRAM)

null

null

01

0

01101


PTE7......


PP0

PP3

VP1VP2VP7VP4

Virtualmemory(disk)

VP6

VP3

Virtualaddress

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HandlingaPageFaultv Pagemisscausespagefault(anexception)v Pagefaulthandlerselectsavictim tobeevicted(hereVP4)

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PageTable(DRAM)

null

null

01

0

01101


PTE7......


PP0

PP3

VP1VP2VP7VP4

Virtualmemory(disk)

VP6

VP3

Virtualaddress


HandlingaPageFaultv Pagemisscausespagefault(anexception)v Pagefaulthandlerselectsavictim tobeevicted(hereVP4)

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PageTable(DRAM)

null

null

01

0

01110


PTE7......


PP0

PP3

VP1VP2VP7VP3

Virtualmemory(disk)

VP4VP6

Virtualaddress

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HandlingaPageFaultv Pagemisscausespagefault(anexception)v Pagefaulthandlerselectsavictim tobeevicted(hereVP4)v Offendinginstructionisrestarted:pagehit!

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PageTable(DRAM)

null

null

01

0

01110


PTE7......


PP0

PP3

VP1VP2VP7VP3

Virtualmemory(disk)

VP4VP6

Virtualaddress


PeerInstructionQuestion

v Howmanybitswidearethefollowingfields?§ 16KiBpages§ 48-bitvirtualaddresses§ 16GiB physicalmemory

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34 24(A)32 18(B)30 20(C)34 20(D)

VPN PPN

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Summary

v Virtualmemoryprovides:§ Abilitytouselimitedmemory(RAM)acrossmultipleprocesses

§ Illusionofcontiguousvirtualaddressspaceforeachprocess§ Protectionandsharingamongstprocesses

v Indirectionviaaddressmappingbypagetables§ Partofmemorymanagementunitandstoredinmemory§ Usevirtualpagenumberasindexintolookuptablethatholdsphysicalpagenumber,diskaddress,orNULL(unallocatedpage)

§ Onpagefault,throwexceptionandmovepagefromswapspace(disk)tomainmemory

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VirtualMemory(VM)

v Overviewandmotivationv VMasatoolforcachingv Addresstranslationv VMasatoolformemorymanagementv VMasatoolformemoryprotection

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Review:Terminology

v Contextswitch§ SwitchbetweenprocessesonthesameCPU

v Pagein§ Movepagesofvirtualmemoryfromdisktophysicalmemory

v Pageout§ Movepagesofvirtualmemoryfromphysicalmemorytodisk

v Thrashing§ Totalworkingsetsizeofprocessesislargerthanphysicalmemoryandcausesexcessivepaginginandoutinsteadofdoingusefulcomputation

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VMforManagingMultipleProcessesv Keyabstraction:eachprocesshasitsownvirtualaddressspace

§ Itcanviewmemoryasasimplelineararray

v Withvirtualmemory,thissimplelinearvirtualaddressspaceneednotbecontiguousinphysicalmemory§ ProcessneedstostoredatainanotherVP?Justmapittoany PP!

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VirtualAddress

SpaceforProcess1:

PhysicalAddressSpace(DRAM)

0

N-1(e.g.,read-onlylibrarycode)

VirtualAddress

SpaceforProcess2:

VP1VP2...

0

N-1

VP1VP2...

PP2

PP6

PP8

...

0

M-1

Addresstranslation

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SimplifyingLinkingandLoadingv Linking

§ Eachprogramhassimilarvirtualaddressspace

§ Code,Data,andHeapalwaysstartatthesameaddresses

v Loading§ execve allocatesvirtualpages

for.text and.data sections&createsPTEsmarkedasinvalid

§ The.text and.data sectionsarecopied,pagebypage,ondemandbythevirtualmemorysystem

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Kernelvirtualmemory

Memory-mappedregionforsharedlibraries

Run-timeheap(createdbymalloc)

Userstack(createdatruntime)

Unused0

%rsp(stackpointer)

Memoryinvisibletousercode

brk

0x400000

Read/writesegment(.data,.bss)

Read-onlysegment(.init,.text,.rodata)

Loadedfromtheexecutablefile


VMforProtectionandSharingv ThemappingofVPstoPPsprovidesasimplemechanismto

protectmemoryandtosharememorybetweenprocesses§ Sharing: mapvirtualpagesinseparateaddressspacestothesame

physicalpage(here:PP6)§ Protection: processcan’taccessphysicalpagestowhichnoneofits

virtualpagesaremapped(here:Process2can’taccessPP2)

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VirtualAddress

SpaceforProcess1:

PhysicalAddressSpace(DRAM)

0

N-1(e.g.,read-onlylibrarycode)

VirtualAddress

SpaceforProcess2:

VP1VP2...

0

N-1

VP1VP2...

PP2

PP6

PP8

...

0

M-1

Addresstranslation

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MemoryProtectionWithinProcess

v VMimplementsread/write/executepermissions§ Extendpagetableentrieswithpermissionbits§ MMUchecksthesepermissionbitsoneverymemoryaccess

• Ifviolated,raisesexceptionandOSsendsSIGSEGVsignaltoprocess(segmentationfault)

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•••

PhysicalAddressSpace

PP2

PP4

PP6

PP8PP9

PP11

Processi: PPNWRITE EXECPP6No NoPP4No YesPP2Yes No

READYesYesYes

VP0:VP1:VP2:

YesYesYes

Valid

Processj: WRITE EXECPP9Yes NoPP6No NoPP11Yes No

READYesYesYes

VP0:VP1:VP2:

YesYesYes

Valid PPN


AddressTranslation:PageHit

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1) ProcessorsendsvirtualaddresstoMMU(memorymanagementunit)

2-3)MMUfetchesPTEfrompagetableincache/memory(UsesPTBRtofindbeginningofpagetableforcurrentprocess)

4) MMUsendsphysicaladdress tocache/memoryrequestingdata

5) Cache/memorysendsdatatoprocessor

MMU Cache/MemoryPA

Data

CPU VA

CPUChip PTEA

PTE1

2

3

4

5

VA=VirtualAddress PTEA=PageTableEntryAddress PTE=PageTableEntryPA=PhysicalAddress Data=ContentsofmemorystoredatVAoriginallyrequestedbyCPU

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AddressTranslation:PageFault

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1) ProcessorsendsvirtualaddresstoMMU2-3) MMUfetchesPTEfrompagetableincache/memory4) Validbitiszero,soMMUtriggerspagefaultexception5) Handleridentifiesvictim(and,ifdirty,pagesitouttodisk)6) HandlerpagesinnewpageandupdatesPTEinmemory7) Handlerreturnstooriginalprocess,restartingfaultinginstruction

MMU Cache/Memory

CPU VA

CPUChip PTEA

PTE1

2

3

4

5

Disk

Pagefaulthandler

Victimpage

Newpage

Exception

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Hmm…TranslationSoundsSlow

v TheMMUaccessesmemorytwice:oncetogetthePTEfortranslation,andthenagainfortheactualmemoryrequest§ ThePTEsmay becachedinL1likeanyothermemoryword

• Buttheymaybeevictedbyotherdatareferences

• AndahitintheL1cachestillrequires1-3cycles

v Whatcanwedotomakethisfaster?§ Solution:addanothercache!🎉

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SpeedingupTranslationwithaTLB

v TranslationLookasideBuffer (TLB):§ SmallhardwarecacheinMMU§ Mapsvirtualpagenumberstophysicalpagenumbers§ Containscompletepagetableentries forsmallnumberofpages• ModernIntelprocessorshave128or256entriesinTLB

§ Muchfasterthanapagetablelookupincache/memory

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TLB

PTEVPN →

PTEVPN →

PTEVPN →


TLBHit

v ATLBhiteliminatesamemoryaccess!

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MMU Cache/Memory

PA

Data

CPU VA

CPU Chip

PTE

1

2

4

5

TLB

VPN 3

TLBPTEVPN →

PTEVPN →

PTEVPN →

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TLBMiss

v ATLBmissincursanadditionalmemoryaccess(thePTE)§ Fortunately,TLBmissesarerare

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MMU Cache/MemoryPA

Data

CPU VA

CPU Chip

PTE

1

2

5

6

TLB

VPN

4

PTEA3

TLBPTEVPN →

PTEVPN →

PTEVPN →


FetchingDataonaMemoryRead

1) CheckTLB§ Input:VPN,Output:PPN§ TLBHit: Fetchtranslation,returnPPN§ TLBMiss: Checkpagetable(inmemory)

• PageTableHit: LoadpagetableentryintoTLB• PageFault: Fetchpagefromdisktomemory,updatecorrespondingpagetableentry,thenloadentryintoTLB

2) Checkcache§ Input:physicaladdress,Output:data§ CacheHit: Returndatavaluetoprocessor§ CacheMiss: Fetchdatavaluefrommemory,storeitincache,returnittoprocessor

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AddressTranslationVirtualAddress

TLBLookup

PageTable“Walk”

UpdateTLB

PageFault(OSloadspage)

ProtectionCheck

PhysicalAddress

TLBMiss TLBHit

PagenotinMem

AccessDenied

AccessPermitted

ProtectionFault

SIGSEGV

PageinMem

CheckcacheFindinDisk FindinMem

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SummaryofAddressTranslationSymbols

v BasicParameters§ N = 2) Numberofaddressesinvirtualaddressspace§ M = 2+ Numberofaddressesinphysicaladdressspace§ P = 2, Pagesize(bytes)

v Componentsofthevirtualaddress(VA)§ VPO Virtualpageoffset§ VPN Virtualpagenumber§ TLBI TLBindex§ TLBT TLBtag

v Componentsofthephysicaladdress(PA)§ PPO Physicalpageoffset(sameasVPO)§ PPN Physicalpagenumber

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SimpleMemorySystemExample(small)

v Addressing§ 14-bitvirtualaddresses§ 12-bitphysicaladdress§ Pagesize=64bytes

13 12 11 10 9 8 7 6 5 4 3 2 1 0

VPOVPNVirtualPageNumber VirtualPageOffset

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPNPhysicalPageNumber PhysicalPageOffset

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SimpleMemorySystem:PageTable

v Onlyshowingfirst16entries(outof_____)§ Note:showing2hexdigitsforPPNeventhoughonly6bits

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VPN PPN Valid0 28 11 – 02 33 13 02 14 – 05 16 16 – 07 – 0

VPN PPN Valid8 13 19 17 1A 09 1B – 0C – 0D 2D 1E – 0F 0D 1

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SimpleMemorySystem:TLB

v 16entriestotalv 4-waysetassociative

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13 12 11 10 9 8 7 6 5 4 3 2 1 0

virtualpageoffsetvirtualpagenumber

TLBindexTLBtag

0–021340A10D030–0730–030–060–080–0220–0A0–040–0212D031102070–0010D090–030

ValidPPNTagValidPPNTagValidPPNTagValidPPNTagSet

WhydoestheTLBignorethepageoffset?


SimpleMemorySystem:Cache

v Direct-mappedwithK =4B,C/K =16v Physicallyaddressed

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11 10 9 8 7 6 5 4 3 2 1 0

physicalpageoffsetphysicalpagenumber

cacheoffsetcacheindexcachetag

Note: ItisjustcoincidencethatthePPNisthesamewidth

asthecacheTag

Index Tag Valid B0 B1 B2 B30 19 1 99 11 23 111 15 0 – – – –2 1B 1 00 02 04 083 36 0 – – – –4 32 1 43 6D 8F 095 0D 1 36 72 F0 1D6 31 0 – – – –7 16 1 11 C2 DF 03

Index Tag Valid B0 B1 B2 B38 24 1 3A 00 51 899 2D 0 – – – –A 2D 1 93 15 DA 3BB 0B 0 – – – –C 12 0 – – – –D 16 1 04 96 34 15E 13 1 83 77 1B D3F 14 0 – – – –

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CurrentStateofMemorySystem

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Cache:

TLB:Pagetable(partial):

Index Tag V B0 B1 B2 B30 19 1 99 11 23 111 15 0 – – – –2 1B 1 00 02 04 083 36 0 – – – –4 32 1 43 6D 8F 095 0D 1 36 72 F0 1D6 31 0 – – – –7 16 1 11 C2 DF 03

Index Tag V B0 B1 B2 B38 24 1 3A 00 51 899 2D 0 – – – –A 2D 1 93 15 DA 3BB 0B 0 – – – –C 12 0 – – – –D 16 1 04 96 34 15E 13 1 83 77 1B D3F 14 0 – – – –

Set Tag PPN V Tag PPN V Tag PPN V Tag PPN V0 03 – 0 09 0D 1 00 – 0 07 02 11 03 2D 1 02 – 0 04 – 0 0A – 02 02 – 0 08 – 0 06 – 0 03 – 03 07 – 0 03 0D 1 0A 34 1 02 – 0

VPN PPN V0 28 11 – 02 33 13 02 14 – 05 16 16 – 07 – 0

VPN PPN V8 13 19 17 1A 09 1B – 0C – 0D 2D 1E – 0F 0D 1


MemoryRequestExample#1

v VirtualAddress:0x03D4

v PhysicalAddress:

TLBITLBT

013

012

011

010

19

18

17

16

05

14

03

12

01

00

VPOVPN

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

COCICT

VPN______ TLBT_____ TLBI_____ TLBHit?___ PageFault?___ PPN _____

CT______ CI_____ CO_____ CacheHit?___ Data(byte)_______


asthecacheTag

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v VirtualAddress:0x038F

v PhysicalAddress:

TLBITLBT

013

012

011

010

19

18

17

06

05

04

13

12

11

10

VPOVPN

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

COCICT




asthecacheTag

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v VirtualAddress:0x0020

v PhysicalAddress:

TLBITLBT

013

012

011

010

09

08

07

06

15

04

03

02

01

00

VPOVPN

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

COCICT




asthecacheTag

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v VirtualAddress:0x036B

v PhysicalAddress:

TLBITLBT

013

012

011

010

19

18

07

16

15

04

13

02

11

10

VPOVPN

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

COCICT




asthecacheTag

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VirtualMemorySummary

v Programmer’sviewofvirtualmemory§ Eachprocesshasitsownprivatelinearaddressspace§ Cannotbecorruptedbyotherprocesses

v Systemviewofvirtualmemory§ Usesmemoryefficientlybycachingvirtualmemorypages

• Efficientonlybecauseoflocality

§ Simplifiesmemorymanagementandsharing§ Simplifiesprotectionbyprovidingpermissionschecking

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MemorySystemSummaryv MemoryCaches(L1/L2/L3)

§ Purelyaspeed-uptechnique§ Behaviorinvisibletoapplicationprogrammerand(mostly)OS§ Implementedtotallyinhardware

v VirtualMemory§ SupportsmanyOS-relatedfunctions

• Processcreation,taskswitching,protection§ OperatingSystem(software)

• Allocates/sharesphysicalmemoryamongprocesses• Maintainshigh-leveltablestrackingmemorytype,source,sharing• Handlesexceptions,fillsinhardware-definedmappingtables

§ Hardware• Translatesvirtualaddressesviamappingtables,enforcingpermissions• Acceleratesmappingviatranslationcache(TLB)

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MemorySystem– Whocontrolswhat?

v MemoryCaches(L1/L2/L3)§ Controlledbyhardware§ Programmercannotcontrolit§ Programmercan writecodetotakeadvantageofit

v VirtualMemory§ ControlledbyOSandhardware§ Programmercannotcontrolmappingtophysicalmemory§ Programmercancontrolsharingandsomeprotection

• viaOSfunctions(notinCSE351)

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Documents

L01: Intro, Combinational LogicL21: Virtual Memory II ......Miss Penalty (latency) 33x Miss Penalty (latency) 10,000x SRAM Static Random Access Memory DRAM Dynamic Random Access Memory