Upload
others
View
1
Download
0
Embed Size (px)
Citation preview
Guardian provides interactive and batch mode verification of analog, mixed signal and RF IC designs, and is integrated with Silvaco’s schematic capture and layout editor. Guardian efficiently performs design rule checks (DRC), layout netlist extraction, and layout vs. schematic (LVS) comparisons.
Key Features
Productivity and Versatility
GuardianDRC/LVS/NET Physical Verification
• IntegrationwithExpertLayoutandGatewaySchematicEditorsprovidesacompleteentry-to-verificationdesignflowforanalog,mixed-signalandRFdesigns
• Broadsupportofsemiconductorprocesstechnologiesthroughfoundry-provenprocessdesignkits(PDKs)
• Fast,intuitiveandhierarchicalLVSdebuggingwithcross-probing to layout and schematic views
• GuardianNETsupportsstresseffectsandwellproximityparameter extraction
• Silvaco’sstrongencryptionisavailabletoprotectvaluablecustomer and third party intellectual property
• Performslayoutvslayoutcomparison(LVL)
• Supports waivers of DRC grouped errors for higher productivitiy
• FullDRCcommandsetfitseverydesignenvironment–localDRCforinteractiveusageandfull-chipDRCinbatchmode
• Optimizedlayeroperationsbasedonefficientmemorymanagement and advanced algorithms get the most performance from Windows and Linux platforms
• Connectivity-basedDRCoperationsincludingantennarulechecking
• OptimizedexecutionofDRCcommandsusinggraph-basedtask processing
• CompatibilitywithmanyleadingDRCtools
Accuracy, Speed, and Capacity• Supports90degree,45degree,andall-angleobjectswith
nocompromiseinaccuracycriticalforanalogandmixed-signal design layout
• InteractiveDRCrunswithinExpertLayoutEditortoprovidefast DRC of a local area with errors stored in the same error database at chip level to maintain consistency
• HierarchicalDRCreportdatabasetracksDRCrunhistory
• HierarchicalDRCerrorreportingmaximizesefficiencyoflayout debugging
• Multi-threadingDRCoffersdramaticincreaseinperformance and capacity
• SmartArrayFilteringforhighperformanceonarray-baseddesigns
Productive - Intuitive graphical DRC error debugging in Expert Layout Editor.
Guardian DRC
Guardian LVS/NET
Ease of Use and Adoption• IntuitivehierarchicalLVSdiscrepancyreportsignificantly
decreases time for error debugging
• DirectdatabaselinksbetweenGatewaySchematicandExpertLayoutEditorsthatenablesreviewsofdiscrepancyreports via crossprobing
• Black-boxoptionsforsubcircuitsprovidesforincrementalLVS comparison in hierarchical mode and easy inclusion of IPblocksintotheverifieddesignattoplevel
GuardianInputs/Outputs
DRC/LVS/LPE Rule Files
GDSII, OASIS
Hierarchical DRC/LVS/NET Error Report
Extracted Layout SPICE Netlist
SPICE Netlist - Flat or Hierarchical
HEADQUARTERS 2811 Mission College Blvd., 6th Floor Santa Clara, CA 95054
WWW.SILVACO.COMRev040920_29
JAPAN [email protected] KOREA [email protected] TAIWAN [email protected] SINGAPORE [email protected] CHINA [email protected]
CALIFORNIA [email protected] [email protected] TEXAS [email protected] EUROPE [email protected] FRANCE [email protected]
Productivity and Versatility• Hierarchicaldesigndatabasesupportsoperationsforflat
and hierarchical LVS netlist comparison
• Handlesanyarbitraryshapedpolygongeometryusedindevice formation
• Maximumpreservationoforiginalhierarchyforeasydebuggingduringpost-layoutcircuitsimulation
• Hierarchicalcross-probingofschematicnetlist,extractedlayout netlist, schematic design, and physical layout
• DetectsERCviolations(shorts,opens,dangles,andimproperlyconnected devices) with convenient filtering options
• SupportsMOSFET,BJT,JFET,MESFET,diode,resistor,capacitor,andparameterizeduser-defineddevices
• AnnotateslayoutwithnodalinformationenablingsuchadvancedfeaturesasNodeProbing,NodeSearch,andShortLocatorwithinExpertICdesignenvironment
• Multi-threadingforhierarchicalnetlistcomparison
Accuracy, Speed, and Capacity• Accuratecalculationofgeometry-dependentSPICE
parameters important for analog design with default or user-definedequations
• Preciseidentificationofgenericdevices(transistors,diodes,resistors,capacitors,etc.),user-defineddevices,and/orblack-boxsubcircuitsduringLVStrace
• Efficientfull-chiplayoutnetlistextractionforanysemiconductor process with unmatched performance
Cross-Probing: Interactive hierarchical cross-probing of LVS discrepancy is clearly displayed.
Node Search highlights nets, devices and instances by schematic and layout names.