KAIAM introduction�March  2015  

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Who is Kaiam?�

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2 main product lines �•  40G and 100G transceivers for modern datacenters�•  PLC chips and modules for transport and broadband networks ��

Technology differentiation�•  Multi-lane single-mode (WDM 4x10 Gbps, 4x25 Gbps) �•  High-density and athermalized PLC �

Vertically integrated volume manufacturing�•  PLCs into Tier 1 OEMS for over a decade�•  40G and 100G to leading OEM and large datacenter customers�

Private Silicon Valley company �•  5 years old �•  Latest funding September 2014 $35M from strategic investors �

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Vertically integrated & volume�

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§  2 locations: §  HQ in Silicon Valley: corporate, R&D, transceiver production

§  Manufacturing in Scotland: Chips (PLC, MEMS), actives subassembly

§  originally Kymata, owned by Alcatel and Gemfire, acquired by Kaiam in 2013

§  57 k sq ft total; 33 k sq. ft manufacturing; 10 k sq ft fab Class 100 silicon fab, 20 k sq ft Class 10,000 assembly and test

Technology is based on Silicon ecosystem�

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4.   In  volume  production  with  this  approach  

§  QSFP+  40G  LR4    

1.    Start  with  a  “PCB”  •  In  this  case,  silicon  MEMS  breadboard  •  Simple  low-­‐cost  process,  can  be  done  at    

many  foundries    2.  Die-­‐bond  components  onto  the  “PCB”  

•  Standard  die-­‐bonding  tools  used  for  electronics  

3.    Additional  connections  by  wirebonding  •  Optical  Wirebond    is  quick  process  with  cheap  

tools,  because  tolerant  of    mechanical  positioning  errors  and  shifts  

100 Gb/s Silicon version �§  Target  is  to  make  a  4  channel  TOSA  in  Silicon      §  Decided  to  use  MPW  run  for  initial  trials  

CH1 CH2 CH3 CH4 Layout in maskengineer

Functional diagram

Following IMEC technology handbook and use of IMEC-PDK�

IMEC process Modules pre-defined in Layout software

Standard cells and components can be included from IMEC-PDK Advanced cells, like bright AWG, from design houses can readily be included

Fab foundry: IMEC support �

§  Transfer  of  modulator  design&technology  from  1550  nm  to  1310  nm  

§  Transfer  of  grating  coupler  designs  from  1550  nm  to  1310  nm  telecom  window.    

§  Photonic  Design  Kit  made  available  through  Phoenix  BV.    

§  Design  rule  checking  done  by  IMEC,  this  includes  the  check  on  acute-­‐angles  which  can  delay  design  significantly  when  not  taken  into  account  early!  

§  Fabrication  of  chips  on  MPW  run  

Packaging foundry: Tyndall �

§  Testing  of  grating  couplers  

§  Testing  of  AWG  in  Silicon  

§  Packaging  of  modulators  

Lessons learned�

§  Think  about  testing  configuration  

§  Plan  on  using  packaging  (foundry)  and  involve  back-­‐end  early  on  in  design  stage  

§  Check  for  and  eliminate  acute  angles  in  design    

§  Packaging  and  fabrication  foundries  as  well  as  the    software  supplier  were  happy  to  help  with  custom  requests  outside  the  standard  set  of  cells  available.  

Aligned to your vision�

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