JSS ACADEMY OF TECHNICAL EDUCATION, BENGALURU …jssateb.ac.in/wp-content/uploads/2018/03/EIE-2017-18.pdf · 2018-10-29 · 6. The purpose of the clock input to a flip-flop c. Clear

JSS MAHAVIDYAPEETHA

JSS ACADEMY OF TECHNICAL EDUCATION, BENGALURU

DEPARTMENT OF ELECTRONICS & INSTRUMENTATION ENGG.

PEDAGOGICAL PRACTICES IN AY: 2017 – 2018

Various Pedagogical Initiatives Practiced No. of Activities

PPTs 2

Videos 3

E-Learning 2

Practical 6

Quiz 12

Collaborative Learning 3

Animations 1

Fig: Statistics on various Pedagogical tools Practiced

PPTs 7%

Videos 10%

E-Learning 7%

Practical 21%

Quiz 41%

Collaborative Learning 10%

Animations 4%

Various Pedagogical Initiatives Practiced

JSS MAHAVIDYAPEETHA



INNOVATION IN TEACHING-LEARNING ---------------------------------------------------------------------------------------------------------------------------------------------------

Course Name : Analog Electronic Circuits Date: 07/11/2017, 14/11/2017 and 16/11/2017

Course Code : 15EI33 Course Year: Aug-Dec 2017

Semester : 3rd

Subject Faculty Name: Mrs. Neela A G

GROUP ACTIVITY TO SIMULATE THE ELECTRONIC CIRCUITS USING

WORKBENCH/EVERY CIRCUIT SOFTWARES

Design and simulate the following analog circuits.

1. Design voltage divider bias circuit for the following configuration : Vcc = 22 V, IcMax = 3mA, SL=100,

hfe=100.

2. Design emitter follower amplifier for the following configuration : Vcc = 12 V, IE = 2mA, SL=100,

hfe=100, VCE=VRE=50% of Vcc.

3. Design full wave rectifier for an output DC voltage of 7.5V, RL =1 KΩ.

4. Design the RC phase shift oscillator for frequency of 1KHz given VCC=12V, ICmax=2mA. For SL100

hfe = 100.

5. Design Bridge rectifier for an output DC voltage of 16V, RL =2.2 KΩ.

6. Design the common collector for the following configuration : Vcc = 22 V, IcMax = 3mA, SL=100,

hfe=100.

7. Design the RC coupled Amplifier.

8. Design the circuit to analyze the characteristics of JFET.

9. Design the circuit to analyze the BJT amplifier.

NOTE to STUDENTS:

1. Form groups of four/five in a team and report to the subject faculty.

2. Simulate the above circuits using the mentioned software’s as per the given guidelines.

3. Prepare a brief report and submit to the subject faculty.

4. Evaluation rubrics are as follows-

a. Simulation (03 marks)

b. Report (02 marks)

JSS MAHAVIDYAPEETHA



INNOVATION IN TEACHING-LEARNING --------------------------------------------------------------------------------------------------------------------------------------------------

Quiz – I

USN:

Course Name : DD&HDL Date: 15.09.2017 Course Code : 15EI34 Time: 02.30-03.30 PM

Course Year : Aug-Dec 2017 Max. Marks: 05

Semester : 3rd

Subject Faculty Name: Mrs. Anu H

Note: Answer all the questions. Write the correct answers in column provided. Each question carries 0.5

marks. COURSE OUTCOME

COs Statements (Students will be able to) Blooms

Level

CO1 Simplify Boolean Expressions. L4

CO2 Build combinational circuits. L3

1. A 3 variable K-map has

a. Eight cells c. sixteen cells

b. Three cells d. four cells

2. In a 4-variable K Map, a two variable product term is produced by

a. A 2-cell group of 1s c. an 8-cell group of 1s

b. A 4 cell group of 1s d.a 4-cell group of 0s

3. On a K map, grouping the 0s produces

a. A product of sums expressions c. a sum-of-products expressions

b. A don’t-care condition d. AND-OR logic

4. The complement of a variable is always

a. 0 b. 1 c. equal to the variable d. the inverse of the variable

5. The Boolean expression A+B’+C is

a. A sum term b. a product term c. a literal term d. a complemented term

6. A half adder is characterized by

a. Two inputs and two outputs c. three inputs and two outputs

b. Two inputs and three outputs d. two inputs and one output

7. A full-adder is characterized by

a. Two inputs and two outputs c. three inputs and two outputs

b. Two inputs and three outputs d. two inputs and one output

8. The inputs to full adder are A=1, B=1, Cin=0. The outputs are

a. ∑=1, Cout=1 c. ∑=1, Cout=0

b. ∑=0, Cout=1 d. ∑=0, Cout=0

9. A 4- bit parallel adder can add

a. Two 4-bit binary number c. two 2-bit binary numbers

b. Four bit at a time d. four bits in sequence

10. Data selectors are basically the same as

a. Decoders c. demultiplexers

b. Multiplxers d. encoders

Answers:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Q7.

Q8.

Q9.

Q10.

Faculty In-charge HOD, E&IE

JSS MAHAVIDYAPEETHA




Quiz – II

USN:

Course Name : DD&HDL Date: 03.11.2017 Course Code : 15EI34 Time: 02.30-03.30 PM


Semester : 3rd

Subject Faculty Name: Mrs. Anu H


marks. COURSE OUTCOMES


Level

CO3 Design code converters, encoders and decoders. L3

CO4 Analyze sequential circuits. L4

1. If a 1:16 decoder with active Low on the decimal 12 output, what are the inputs?

c. A3A2A1A0=1010 c. A3A2A1A0=1110

d. A3A2A1A0=1100 d. A3A2A1A0=0100

2. BCD to Seven Segment decoder has 0100 on its inputs. The active outputs are

c. a,c,f,g b. d,c,f,g, c. b,c,g,f d. b,d,e,g

3. If an SR latch has a 1 on the S input and a ) on the R input and then the S input goes to 0, the latch will be

c. set b. reset c. invalid d. clear

4. The invalid state of an S-R latch occurs when

b. S=1,R=0 b. S=0,R=1 c. S=1,R=1 d. S=0,R=0

5. For a gated D latch, the Q output always equals the D input

b. Before the enable pulse b. during the enable pulse

c. immediately after the enable pulse d. answers b. and c.

6. The purpose of the clock input to a flip-flop

c. Clear the device c. always cause the output to change states

d. Set the device d. cause the output to assume a state dependent on the controlling input.

7. A feature that distinguishes JK flip flop from SR flip flop is the

c. Toggle condition c. preset input

d. Type of clock d. clear input

8. In PISO register data move from

c. Shift right c. shift left

d. Both Directions d. None of the above

9. Which flip flop is usually used for Shift Registers

c. JK Flip Flop c. SR Flip Flop

d. T Flip Flop d. D Flip flop

10. Universal Shift Registers has

c. Left shift and right shift only c. Left shift only

d. Left shift only d. Left shift and right shift and parallel load

Answers:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Q7.

Q8.

Q9.

Q10.


JSS MAHAVIDYAPEETHA




Course Name : Network Analysis Date: 25.11.2017

Course Code : 15EI36 Course Year : Aug-Dec 2017

Semester : 3rd

Subject Faculty Name : Mrs. K S Bhanumathi

SIMULATION OF ELECTRICAL NETWORKS USING S/W TOOL (ANY CIRCUIT S/W)

A. Solve the electrical networks (Any ten circuits of students’ choice) to,

1. Find currents and voltages.

2. Find loop current.

3. Find branch currents using node analysis method.

4. Prove Thevenin’s theorem.

5. Use the s/w tool for simulation.

B. Use the s/w tool for simulation (Preferably ANY CIRCUIT S/W).

C. Analyze the circuits operation.

NOTE to STUDENTS:

5. Form groups of two to five in a team and report to the subject faculty.

6. Implement the above exercise and demonstrate the results to the subject faculty.



a. Implementation and demonstration (03 marks)


JSS MAHAVIDYAPEETHA



INNOVATION IN TEACHING-LEARNING -------------------------------------------------------------------------------------------------------------------------------

Quiz – I

USN:

Course Name : Fundamentals of signals & DSP Date: 15.09.2017 Course Code : 15EI52 Time: 02.30-03.30 PM

Course Year : Aug-Dec 2017 Max. Marks : 05

Semester : 5th Subject Faculty Name : Ms. Harshitha S

Note: Answer all the questions. Write the correct answers in column provided. Each question carries mark.

COURSE OUTCOME

COs Statements (Students will be able to) Blooms Level

CO1 Analyze time domain representation for discrete time signals and LTI systems L 4

1. Define a Signal.

2. Define a System.

3. List any two advantages of Digital processing over Analog processing.

4. State Sampling Theorem.

5. Define Nyquist Rate.

6. Define a unit ramp signal.

7. The energy E of a signal x (n) is defined as _________________.

8. The z-transform of is _____________________.

9. State Initial Value Theorem.

10. The z-transform of an unit sample sequence is_________________.

Answers:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Q7.

Q8.

Q9.

Q10.


JSS MAHAVIDYAPEETHA




Quiz – II

USN:





COURSE OUTCOMES


Level

CO1 Analyze time domain representation for discrete time signals and LTI systems L 4

CO2 Compute Discrete Fourier Transform of time domain sequences using its definition, properties and FFT algorithms L3

1. Inverse Z transform of

a.

b.

c.

d.

2. The system H(z) is stable if the poles of the system lie

a. Inside the unit circle of the z plane b. Inside the unit circle of the z plane

c. Inside the unit circle of the z plane d. Inside the unit circle of the z plane

3. If x(n) = 1, 2, 3, 4, then ROC of X(z)

a. Converges everywhere in the z plane except at Z=0 and at Z= ∞

b. Converges everywhere in the z plane except at Z=0

c. Converges everywhere in the z plane except at Z= ∞

d. Converges everywhere in the z plane

4. Inverse Z-transform of H(z) = Z+5+Z-1

is

a. b.

c. d.

5. In direct Form II, the number of unit delays compared with direct form I are reduced to

a. One Third b. Half

c. Not reduced d. One quarter

6. Find the wrong statement-

a. Direct forms I and II requires same number of additions and multiplications

b. Direct form II requires less number of additions compared to direct form I

c. Direct form II requires less number of multiplications compared to direct form I

d. Direct form II requires less number of multiplications and additions compared to direct form I

7. Circular Convolution of two sequences both of length N in time domain is equivalent to

a. Convolution of their spectra in frequency domain

b. Multiplication of their spectra in frequency domain

c. Circular Convolution of their spectra in frequency domain

d. Exponential product of their spectra in frequency domain

8. N-point DFT requires…………………….. number of multiplications

a. b.

c.

d.

9. DFT of is-

a.

b.

c.

d.

10. Number of multiplications and additions required in the calculation of FFT algorithm is

a.

and b.

and

c. and

d. and

Answers:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Q7.

Q8.

Q9.

Q10.


JSS MAHAVIDYAPEETHA




Quiz – III

USN:





COURSE OUTCOMES


Level

CO3 Design Finite Impulse Response and Infinite Impulse Response filters L 3

CO4 Discuss Multirate Digital Signal Processing & Adaptive Filters L6

1. FIR filters are

a. Non Recursive Type b. Recursive Type

c. Neither (a) nor (b) d. Both (a) and (b)

2. In FIR filter design using Hamming and Hanning window, we assume

a. Pass band and stop band ripple are equal b. Only pass band contains ripple

c. Only stop band contains ripple d. Pass band and stop band ripple are not equal

3. Sampling rate conversion process is used for

a. Changing the sampling frequency of a signal

b. Changing the amplitude of a signal

c. Changing the phase of a signal

d. None of these

4. In impulse invariance transformation method, relationship between ω and Ω is given by

a. Ω b. Ω

c. Ω

d. Ω

5. Non linearity in the relationship between ω and Ω is known as

a. Frequency warping b. Frequency non warping

c. Frequency mixing d. Aliasing

6. Analysis filter banks are used

a. To decompose signal x(n) into a set of M sub band signals

b. To combine M sub band signals to get y(n)

c. To remove noise in the signal

d. To remove image frequencies in the signal

7. Analysis filter banks are used

a. To decompose signal x(n) into a set of M sub band signals

b. To combine M sub band signals to get y(n)

c. To remove noise in the signal

d. To remove image frequencies in the signal

8. In bilinear transformation method, relationship between ω and Ω is given by

a. Ω

b. Ω

c. Ω

d. Ω

9. Butterworth filter have

a. Wideband transition region b. Sharp transition region

c. Oscillation in the transition region d. None of these

10. Chebyshev filter have

a. Wideband transition region b. Sharp transition region

c. Oscillation in the transition region d. None of these

Answers:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Q7.

Q8.

Q9.

Q10.


JSS MAHAVIDYAPEETHA




Quiz – 1

Course Name : VLSI Design Date:13.09.2017

Course Code : 15EI551 Semester : 5th

Course Year : Aug-Nov 2017 Subject Faculty: Mrs. Sowmya M S

COURSE OUTCOME

COs Statements (Students will be able to) Blooms Level

CO1 Describe the MOS process technology. L3

CO2 Analyze the basic electrical properties of MOS &BiCMOS circuits. L4

Answer the following questions

1. The condition for non saturated region is 0.5m

a) Vds = Vgs – Vt b) Vgs < Vt

c) Vds > Vgs – Vt d) Vds < Vgs – Vt

2. Enhancement mode MOSFETs are more commonly used as 0.5m a) switches b) resistors c) buffers d) capacitors

3. What is the disadvantage of MOS device? 0.5m a) limited current sourcing b) limited voltage sinking

c) limited voltage sourcing d) unlimited current sinking

4. Mobility of proton or hole at room temperature is 0.5m a) 650 c

m2/V sec b) 260 c

m2/V sec c) 240 c

m2/V sec d) 500 c

m2/V sec

5. MOSFET is used as 0.5m a) current source b) voltage source c) buffer d) divider

6. Transconductance gives the relationship between 0.5m a) input current and output voltage b) output current and input voltage

c) input current and input voltage d) output current and output voltage

7. How is nMOS inverter represented? 0.5m

a) b) c) d)

8. In latch-up condition, parasitic component gives rise to __________ conducting path 0.5m a) low resistance b) high resistance c) low capacitance d) high capacitance

9.

0.5m

In the above diagram of BiCMOS, the labels a,b,c,d denote: a) A = Collector, B = Base, C = Source, D = Drain

b) A = Emitter, B = Base, C = Drain, D = Source

c) A = Emitter, B = Collector, C = Source, D = Drain

d) A = Collector, B = Emitter , C = Drain, D = Source

10. For 5 µm technology, the RS value for a metal is 0.5m a) 0.03 b) 0.04 c) 0.02 d) 0.01

Answers:

Q. No Answer

1.

2.

3.

4.

5.

http://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-nmos-inverter-q6a.png

http://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-nmos-inverter-q6b.png

http://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-nmos-inverter-q6c.png

http://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-nmos-inverter-q6d.png

http://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-bicmos-logic-gates-q11.png

6.

7.

8.

9.

10.

Faculty in-charge HOD, E&IE

JSS MAHAVIDYAPEETHA




Course Name : Operating systems Dates: 22/08/17, 05/09/18, 06/10/17

Course Year : Aug – Nov 2017 Course Code : 15EI563

Semester : 5TH

Subject Faculty Name : Nagesha

GROUP ACTIVITY TO IMPLEMENT OPERATING SYSTEMS CONCEPTS

Develop and execute the programs for the following

1. Using system calls

Students have to develop programs using system calls of windows / Linux operating systems.

2. Multithreading

Implementation of two or more threads and assign separate job to each one.

3. Implementation of deadlocks

Simulate the situation of occurrence of deadlocks in operating system.

NOTE to STUDENTS:

9. Form groups of FIVE in a team and report to the subject faculty.

10. Students can implement these concepts in lab or using their own laptop.



a. Implementation in the lab (03 marks)


JSS MAHAVIDYAPEETHA




Course Name : VLSI Design Date: 17/10/2017, 28/11/2017 & 20/11/2017


Semester : 7th Subject Faculty Name : Mrs. Sowmya M S

GROUP ACTIVITY TO IMPLEMENT MOS CIRCUITS THROUGH SOFTWARE USING LAMBDA

BASED DESIGN RULES

Design and implement the following circuits using Microwind and DSCH3 Software.

1. CMOS Inverter for 1:1 and 4:1 ratio.

2. NAND and NOR gate.

3. Boolean expression Y=A+BC

4. Boolean expression Y= A(B+C) +D

NOTE to STUDENTS:

13. Design and Implement the above MOS circuits in the computer lab.


JSS MAHAVIDYAPEETHA




Quiz – I

USN:

Course Name : Power & Industrial Electronics Date: 12.10.2017 Course Code : 10EI72 Time: 9.00-10.00 AM


Semester : 7th Subject Faculty Name: Mrs. Anu H


marks. COURSE OUTCOME


Level

CO1 Explain the principles of operation of power electronic converters, Power BJT and IGBT. L2

CO2 Apply the knowledge of thyristors to know about their protection, different types, operations

and firing circuits. L3

CO3 Make use of thyristors for commutation techniques. L3

11. Power electronics combines

e. Power, mathematics, controls c. Power, electronics, controls

f. Physics, chemistry, controls d. Power, electronics, DSP

12. Control deals with

d. Steady state and dynamics characteristics of closed loop

e. Steady state and dynamics characteristics of opened loop

f. Unsteady and dynamics characteristics of closed loop

g. Unsteady and dynamics characteristics of opened loop

13. Electronics deals with

d. Signal Processing c. Imaging Processing

e. Solid state devices and circuits for signal processing d. switching speed

14. Thyristor has three terminals

c. Anode, cathode and drain c. Anode, cathode and gate

d. Drain, source and gate d. collector, emitter and base

15. Controllered rectifier

c. Ac-dc converter b. dc-dc converter c. ac-ac converter d. dc-ac converter

16. Second breakdown is

e. Building phenomenon c. assertive phenomenon

f. Power derating d. destructive phenomenon

17. Thyristor has ……………. Layers

e. Three c. two

f. Four d. five

18. Thyristor has

e. 3 transistors c. 2 transistors

f. 4 transistors d. 1 transistor

19. Thyristors are connected in series to produce

e. Current rating c. power rating

f. Time rating d. voltage rating

20. DC choppers convert

a. Ac-dc converter b. dc-dc converter c. ac-ac converter d. dc-ac converter

Answers:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Q7.

Q8.

Q9.

Q10.


JSS MAHAVIDYAPEETHA



INNOVATION IN TEACHING-LEARNING ------------------------------------------------------------------------------------------------------------------------------------------------

Quiz – II

USN:

Course Name : Power & Industrial Electronics Date: 02.11.2017 Course Code : 10EI72 Time: 02.30-03.30 PM






Level

CO4 Examine thyristors as ac voltage controllers and Controller rectifiers. L4

CO5 Analyze thyristors as DC Choppers, DC drives and Inverters. L4

1. Power flow is controlled by varying ……………….value of ac voltage applied to the load.

g. rms c. normalized

h. peak d. dc

2. Power flow to the load is controlled by delaying …………………….of thyristors.

h. Acute angle b. Obtuse angle c. firing angle d. Right angle

3. In bidirectional controllers with resistive loads, T1 and T2 are kept ………………………..

f. 180 c. 90

g. 270 d. 0

4. Cycloconverters converts

e. Ac voltage to variable ac voltage c. power at one frequency to power at another frequency

f. Ac voltage to dc voltage d. Dc to ac voltage

5. The delay angles in cycloconverters are such that output voltage of one converter is……………………………

to that of another.

d. Equal and opposite b. Unequal and opposite c. Equal and similar d. Unequal and dissimilar

6. Semi converters in controlled rectifiers is an

g. One quadrant c. two quadrants

h. Three quadrants d. four quadrants

7. In full converter in controlled rectifiers can be

g. Positive c. negative

h. Positive or negative d. Positive and negative

8. In Dc Converter the switch is called as

g. chopper c. transistor

h. switch d. gate

9. Inversion mode is

g. Voltage and current is positive c. Voltage is negative and current is positive

h. Voltage and current is negative d. Voltage is positive and current is negative

10. DC choppers convert

a. Ac-dc converter b. dc-dc converter c. ac-ac converter d. dc-ac converter

Answers:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Q7.

Q8.

Q9.

Q10.


JSS MAHAVIDYAPEETHA




Quiz – III

USN:

Course Name : Power & Industrial Electronics Date: 23.11.2017 Course Code : 10EI72 Time: 02.30-03.30 PM






Level

CO5 Analyze thyristors as DC Choppers, DC drives and Inverters. L4

1. Dc-dc converters provide a variable dc voltage from a.

i. Fixed dc voltage c. variable dc voltage

j. Mixed voltage d. no voltage

2. In motoring, both armature and field currents are.

i. Positive b. negative c. zero d. none of the above

3. In regenerative braking armature current is ……….. and field current is …………………..

h. Positive and negative c. negative and Positive

i. Infinity. d. 0

4. Plugging is a type of

g. Braking c. speed

h. torque d. pressure

5. Dynamic braking is different from regenerative braking except

e. Series resistance b. Parallel resistance c. Braking resistance d. none of the above

6. Ac-dc converters are used to improve the

i. Power factor c. cos factor

j. Voltage d. Current

7. Which is a measure of individual harmonic contribution

i. THD c. DF

j. LOH d. Harmonic factor

8. Which is measure of Closeness in shape between waveform and its fundamental component

a. THD c. DF

b. LOH d. Harmonic factor

9. Harmonic component whose frequency is closet to fundamental one

a. THD c. DF


10. ……………. is a measure of effectiveness in reducing unwanted harmonics without having to specify the values

of filter

a. THD c. DF


Answers:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Q7.

Q8.

Q9.

Q10.


JSS MAHAVIDYAPEETHA




Course Name : Digital Image Processing Date: 30/10/2017, 09/11/2017, 11/11/2017 & 25/11/2017



GROUP ACTIVITY TO IMPLEMENT DIGITAL IMAGE PROCESSING

TECHNIQUES IN MATLAB

Develop and execute MATLAB programs to perform the following.

10. Design of discrete cosine transform (DCT) for

a. 2-d signal (using DCT expression)

b. 70%, 50%, 30%, 10% compression of an image

11. Design a filter for the noisy image using the following.

a. Frequency domain (Gaussian Filter)

b. Spatial domain (Averaging filter)

c. Spatial domain (Median filter)

12. Implement the following image processing operations.

a. Contrast Stretching

b. Edge Detection

13. Implement the following image processing operations.

a. Thresholding

b. Histogram Equalization

14. Image compression using JPEG

15. Design of discrete wavelet transform (DWT)

a. 1-dimensional sequence

b. 2-dimensional signal (Image)

NOTE to STUDENTS:

15. Form groups of two in a team and report to the subject faculty.

16. Implement the above exercise in the computer lab as per the given schedule.





JSS MAHAVIDYAPEETHA




Course Name : ARM processor Date: 12/09/17

Course Year : Aug – Nov 2017 Course Code : 10EI754

Semester : 7TH

Subject Faculty Name : Nagesha

GROUP ACTIVITY TO INSTALL ARM PROCESSOR IDEs AND ARM ASSEMBLY

LANGAUAGE PROGRAMS

1. Installation of ARM processor IDE.

Students have to install openly and freely available ARM processor IDE’s in their laptop.

2. Execute ARM assembly programs on the installed IDE.

NOTE to STUDENTS:

19. Form groups of FIVE in a team and report to the subject faculty.

20. Students can implement these in lab or using their own laptop.





Documents

JSS ACADEMY OF TECHNICAL EDUCATION, BENGALURU …jssateb.ac.in/wp-content/uploads/2018/03/EIE-2017-18.pdf · 2018-10-29 · 6. The purpose of the clock input to a flip-flop c. Clear