Journal of Power Electronics, Vol. 18, No. 1, pp. 11-22, January 2018 11

https://doi.org/10.6113/JPE.2018.18.1.11

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

JPE 18-1-2

© 2018 KIPE

Analysis and Implementation of a New Single

Switch, High Voltage Gain DC-DC Converter with

a Wide CCM Operation Range and Reduced

Components Voltage Stress

Babak Honarjoo*, Seyed M. Madani†, Mehdi Niroomand*, and Ehsan Adib**

*,†Department of Electrical Engineering, University of Isfahan, Isfahan, Iran

**Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran

Abstract

This paper presents a single switch, high step-up, non-isolated dc-dc converter suitable for renewable energy applications. The

proposed converter is composed of a coupled inductor, a passive clamp circuit, a switched capacitor and voltage lift circuits. The

passive clamp recovers the leakage inductance energy of the coupled inductor and limits the voltage spike on the switch. The

configuration of the passive clamp and switched capacitor circuit increases the voltage gain. A wide continuous conduction mode

(CCM) operation range, a low turn ratio for the coupled inductor, low voltage stress on the switch, switch turn on under almost

zero current switching (ZCS), low voltage stress on the diodes, leakage inductance energy recovery, high efficiency and a high

voltage gain without a large duty cycle are the benefits of this converter. The steady state operation of the converter in the

continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is discussed and analyzed. A 200W prototype

converter with a 28V input and a 380V output voltage is implemented and tested to verify the theoretical analysis.

Key words: Coupled inductor, High step-up voltage gain, Single switch, Switched capacitor, Low voltage stress

I. INTRODUCTION

Environment pollution and the depletion of fossil fuels

have pushed researchers to work on renewable energy

sources, especially solar energy. The output voltage of solar

panels is usually less than 50 volts. However, in order to

inject power to the grid, the DC level must be stepped up to

380-400V DC for a full bridge inverter and 750-800V DC for

a half bridge inverter. The series connection of photovoltaic

(PV) panels is a solution to produce such high voltages.

However, due to shading and panel mismatch, maximum

power point tracking (MPPT) is not achieved which reduces

the system efficiency. Moreover, in the case of panel failure,

the entire panel set fails. For these reasons, paralleling PV

panels is a better choice. On the other hand, in low power

applications, it is possible to use only one panel. In such

cases, a DC-DC boost converter is needed to increase the DC

voltage of the PV panel. DC-DC boost converters are

categorized into isolated and non-isolated types. The efficiency

of isolated converters is less than that of non-isolated

converters, since all of the input power is transmitted via

magnetic coupling. Moreover, a large winding turn ratio of

the transformer in an isolated converter increases the winding

parasitic capacitors and transformer leakage inductance,

which results in oscillations and increased losses and

electromagnetic interference (EMI) noise.

The conventional boost converter is the simplest topology

of this type of converter. However, the gain and efficiency of

this converter is limited because of its high conduction and

switching losses due to the reverse-recovery of the output

diodes and the larger conduction losses due to the applied

high voltage switch.

To increase the voltage gain of a boost converter various

techniques have been introduced. The voltage gain of a

three-level boost converter is almost same as that of a

conventional boost converter, and the voltage stress on the

switches and output diodes is half the output voltage.

However, the reverse recovery of the output diodes is still a

Manuscript received Apr. 18, 2017; accepted Aug. 14, 2017 Recommended for publication by Associate Editor Chun-An Cheng.

†Corresponding Author: madani104@yahoo.com Tel: +98-31-37934547, Fax: +98-31-37933071 , University of Isfahan*Dept. of Eng., Univ. of Isfahan, Iran

**Dept. of Electrical and Computer Eng., Isfahan Univ. of Tech., Iran

12 Journal of Power Electronics, Vol. 18, No. 1, January 2018

problem. In cascade boost converters, the voltage gain is high

and equal to the product of its stages. However, the second

stage has high voltage stress on the switch and diode, which

results in low efficiency, due to two stage power processing.

In addition, using two magnetic cores and switches, and its

instability issue are the disadvantages of this converter [1]. In

quadratic boost converters [1], [2], the active switch of the

first stage is replaced with a diode, which makes the circuit

simpler. However, like cascade boost converters, on the

second stage, the high voltage stress on the output diode and

active switch is equal to the output voltage. The integration of

a boost converter with another converter, such as flyback or

SEPIC [1], [3], [4] has the following advantages: some of the

elements such as the active switch or inductor are shared

between two converters, both converter outputs are added

together, and the boost converter section behaves like a

clamping circuit. The switched capacitor [1] and voltage lift

[5] techniques are appropriate for low power applications.

Meanwhile, in high power applications, high transient current

passes through the active switch which reduces efficiency.

Using voltage multiplier cells in the boost converter [6]-[9] is

suitable for moderate voltage gain applications, because for a

high gain voltage, a high number of cells decreases efficiency.

Using a switched inductor in a boost converter [10] is also

not appropriate for high voltage gain and high power

applications, because the conduction losses of the switched

inductor diodes are high, and the voltage stress of the active

switch and output diode is equal to the output voltage. In

active network converters (ANC) [10], the diodes of the

switched inductor are removed and an active switch is added.

In this configuration, the voltage and current stress on the

switches are reduced. However, the voltage gain is low and it

needs two isolated gate pulses for its two switches. Three

state switching cell (3SSC)-based converters [11] have a low

input current ripple, where the current ripple frequency of the

auto transformer and inductor is twice the switching

frequency, which reduces the volume and weight of the

magnetic elements. Due to the presence of an autotransformer

with a unit turn ratio, there is good current sharing between

the switches. Although these converters have a large number

of component, they are suitable for high power applications.

In high step-up applications, boost converters with

coupled-inductors are particularly important. There are three

main advantage of these converters. 1) Their high voltage

gain with a low operating duty cycle can be adjusted by a

proper turn ratio of the coupled inductor. 2) Their switch

voltage stress is low. Therefore, switches with a low Rds (on)

and low conduction losses can be utilized. 3) Their secondary

leakage inductance reduces the reverse recovery ringing of

the output diode.

There are three disadvantage of converters with coupled

inductors. 1) When the active switch is turned off, the stored

energy in the leakage inductance causes a voltage spike

across the switch. 2) Their input current ripple is high,

especially with increments of the turn ratio. 3) Using a higher

turn ratio to achieve a higher voltage gain causes higher

parasitic winding capacitors and leakage inductance, which

increase the losses and EMI noise.

To overcome the problem of leakage inductance energy,

Resistor-Capacitor-Diode (RCD) snubber circuits, passive

clamp circuits [12] and active clamp circuits [13] have been

proposed. The RCD snubber suppresses switch voltage spikes.

However, it wastes the leakage inductance energy in the RCD

resistor, which reduces the efficiency. Unlike the RCD

snubber, both active and passive clamp circuits recover the

energy of the leakage inductance. In the active clamp circuit,

the zero voltage switching (ZVS) conditions is provided for

each of the switches, but at the cost of an additional switch

with an isolated drive circuit, resulting in increased

complexity of the converter. Passive clamp circuits have

simpler structure and do not need additional switches.

References [3], [14], [18], [20], [23], [25] employ output

stacking techniques to directly transferred the leakage

inductance energy of the coupled inductor to the output.

To achieve a high voltage gain, various technique have

been applied on the coupled inductor. In [18], by using output

stacking and a switched capacitor in the secondary of the

coupled inductor, the winding number of the coupled inductor

is decreased and the voltage gain and core utilization-factor is

increased. The authors of [14] proposed a high voltage gain

converter with a low input ripple current, which is suitable

for high power applications. This converters uses two

coupled inductors, interleaved switching, a voltage multiplier

cell, output stacking and voltage lift techniques. The

converter in [20] has less input current ripple and the same

voltage gain when compared to the converter in [14].

However, it uses two inductors and one coupled inductor.

The converter in [21] uses a coupled inductor and the

switched-capacitor technique. In flyback mode when the

switch is off, four capacitor are charged. In the forward mode

when the switch is on, the capacitors, input source and

secondary of the coupled inductor are in series and supply the

load. However, the source current in this converter is

discontinuous.

In [22] a passive clamp capacitor, which recycles the

leakage inductance energy, in series with the secondary of

the coupled-inductor charges a voltage-lift capacitor. This

increases the voltage gain of the converter. Using the

three-winding coupled-inductor in [25] offers a more flexible

adjustment of the voltage conversion and less voltage stress

on each diode. However, it is more complicated. In [26],

using two coupled-inductors and a switched-capacitor cell, a

high step-up Z-source converter was proposed. Compared

with a boost converter, the Z-source converter has a higher

voltage gain. The converter in [26] has a high voltage gain

and voltage spike across the switch is clamped. However, the

presence of a diode at the input and a high current section

cause losses which decreases efficiency. The converter in

Analysis and Implementation of a New Single Switch, High Voltage Gain … 13

[27] has a three-winding coupled-inductor and an isolated-

gate driver for the switch, which makes it complicated. The

authors of [28] proposed a high step up converter using an

active network, a three-winding coupled-inductor and a

switched-capacitor cell. The active network reduces the

voltage and current stress on the active switches and

increases the voltage gain. This converter is complicated, due

to the three-winding coupled-inductor and the two active

switches with isolated gate drives.

The authors of [23], [24] proposed a cascade coupled

inductor with a boost converter, which achieved a low input

ripple current and a high voltage gain. However, like

quadratic boost converters, due to the two power processing

stages in the high current section, the efficiency is reduced. In

addition, these converters use two magnetic cores which

increase the volume.

In this paper a high voltage gain converter using a boost

coupled inductor with a passive clamp circuit is proposed that

utilizes the switched capacitor and the voltage lift technique

to further increase the voltage gain. The configuration of the

passive clamp and switched capacitor circuit increase the

voltage gain. A high voltage gain without a large duty cycle,

a high conversion ratio, a wide CCM operation, low voltage

stress on the switch, switch turn on under almost ZCS, low

voltage stress on the output diode, leakage inductance energy

recovery and high efficiency are the benefits of this

converter.

II. OPERATING PRINCIPLE OF THE

PROPOSED CONVERTER

Fig. 1 shows the circuit configuration of the proposed

converter. The coupled inductor is shown with its equivalent

circuit including an ideal transformer, the magnetizing

inductance Lm and the leakage inductance Llk. NP and NS are

the number of primary and secondary winding turns of an

ideal transformer, respectively. C1 is a clamp capacitor, C3,

C4, C5 are switched capacitors, C2 is a voltage lift capacitor,

and CO is an output capacitor. D1 is a clamp diode, DO is the

output diode and D2, D3, D4, D5 are blocking diodes. The

semiconductor elements are assumed to be ideal. The

coupling coefficient is represented by k=Lm/(Lm+Llk ), and

n=NS/NP is the ideal transformer turn ratio.

A. Continuous Conduction Mode (CCM) Operation

There are five operating modes in one switching cycle of

the proposed converter. Fig. 2 represents theoretical waveforms

of the proposed converter at the CCM operation.

1) Mode I [t0-t1]: Fig. 3(a)

Before t0, the switch S is off and the diodes D3, D4, Do are

conducting. At t0, the switch S is turned on. The primary side

current of the coupled inductor iLlk increases linearly until it

reaches the magnetizing inductor current iLm at t1. During this

D3

D4

D5

Do

D2D1

C2

C1

C3

C4

C5

CO R

s

Lm

NPNS

+ vLm -

iLm

+ vlk -

iLlk

ids

- VC2 +

- VC4 +

VC5

iD1 iD2

iD5

iDo

iD4

+

Vo

- VC1

VC3

+

-

+

+

-

-

-

+

ioiCo

Vin

iC2

iC5

iC4

iC1

iC3+ vs -

isiD3

Llk

Coupled inductor Voltage lift

capacitor

Switched capacitor circuit

Passive clamp

circuit

Fig. 1. Circuit configuration of the proposed converter.

Mode I Mode II Mode III Mode IV Mode V

t0

Ts

DTsDcTs (1-D)Ts

ilk

VGS

iLm

iS

iD1

iD3,

iD4

t

t

t

t

t

t

t

iD2,

iD5

t1 t2 t3 t4 t5

Fig. 2. Theoretical waveforms of the proposed converter at

the CCM.

time interval the difference between iLm and iLlk (iLm-iLlk) flows

through the primary side of the ideal transformer T1. The

current of T1’s secondary is equal to n(iLm-iLlk) which

decreases linearly until it reaches zero at t1. The currents of

D3, D4, Do decrease linearly and reach zero at t1. Therefore,

the reverse recovery problems of these diodes are alleviated.

In addition, S1 turns on under almost ZCS.

2) Mode II [t1-t2]: Fig. 3(b)

At t1, iLlk is equal to iLm. Therefore, the magnetizing

inductance Lm begins to absorb energy from Vin. The current

and voltage direction in the primary and secondary side of T1

are reversed. Diodes D2, D5 begin to conduct. In this mode,

the voltage lift capacitor C2 is charged via the clamp capacitor

C1, the switched capacitor C3 and the secondary side of T1.

Moreover, the switched capacitor C5 is charged via the

switched capacitor C4 and the secondary side of T1.

14 Journal of Power Electronics, Vol. 18, No. 1, January 2018

D3

D4

D5

Do

D2D1

C2

C1

C3

C4

C5

CO R

s

Llk

Lm

NP NS

+-

+

+

+

+

+

-

-

-

-

-

-

+

Vo

Vin

(a)

D3

D4

D5

Do

D2D1

C2

C1

C3

C4

C5

CO R

s

Llk

Lm

NP NS

+-

+

+

+

+

+

-

-

-

-

-

-

+

Vo

Vin

(b)

Vo

D3

D4

D5

Do

D2D1

C2

C1

C3

C4

C5

CO R

s

Llk

Lm

NP NS

+-

+

+

+

+

+

-

-

-

-

-

-

+

Vin

(c)

(d)

Vin

D3

D4

D5

Do

D2D1

C2

C1

C3

C4

C5

CO R

s

Llk

Lm

NP NS

+-

+

+

+

+

+

-

-

-

-

-

-

+

Vo

(e)

Fig. 3. Current path of the operating modes during one switching

cycle in the CCM operation: (a) Mode I; (b) Mode II; (c) Mode

III; (d) Mode IV; (e) Mode V.

3) Mode III [t2-t3]: Fig. 3(c)

At t2, switch S is turned off. Diode D1 conducts and

transfers the energy of the leakage inductance Llk to the clamp

capacitor C1. Therefore, the voltage of the switch clamps to

VC1. In addition, a part of the magnetizing inductance energy

is absorbed by this capacitor in the next mode, which is used

to charge the capacitor C2. In this mode, iLlk is greater than iLm,

and iLlk-iLm flows through the primary side of T1. Lm still

absorbs energy and the polarity of the T1 voltage has not

changed yet. Therefore, the difference of C1 in series with the

primary side of the T1 voltages and the input source voltage

are imposed to Llk and force iLlk to decreases rapidly to iLm at

t3. The currents of the T1 secondary side and the diodes D2, D5

decline and reach zero at t3.

4) Mode IV [t3-t4]: Fig 3(d)

In this mode, the current of the leakage inductance iLlk is

less than the current of the magnetizing inductance iLm.

Therefore, the current direction and voltage polarity of the T1

primary and secondary are reversed. The diodes D3, D4, DO

conduct and their currents increase. In this mode, D1 still

conducts and the reduction rate of its current is less than that

of the previous mode, because the T1 voltage polarity is

reversed. At t4, iLlk reaches iDO and the diode D1 turns off.

5) Mode V [t4-t5]: Fig. 3(e)

During this time interval, the energy of the magnetizing

inductance Lm, leakage inductance Llk and input source Vin

along with C2 and C5 is delivered to the load R. In addition,

the switched capacitors C3, C4 are charged. In this mode C1,

C5 are discharged. This mode ends at t5 when S is turned on

and the next switching period starts.

B. Discontinuous Conduction Mode (DCM) Operation

Since the leakage inductance is very small, its voltage drop

can be neglected when compared to the voltage across Lm.

Therefore, the leakage inductance is ignored in these models.

Fig. 4 shows theoretical-waveforms during the three major

operating modes in the DCM. Fig. 5 shows the current flow

paths for theses modes.

1) Mode I [t0-t1]: Fig. 4(a)

At t0, the switch S is turned on. The magnetizing

inductance Lm absorbs energy from the source and its current

increases linearly from zero. Simultaneously, the coupled

inductor is in forward operation and transfers a part of the

source (Vin ) energy to the capacitors C2 and C5. This mode

ends at t1 when S is turned off.

2) Mode II [t1-t2]: Fig. 4(b)

In this mode, S is off. The energy of Lm is transferred to the

capacitors C1, C3, C4, Co and the load R. The capacitors C2

+

Vo

Vin

D3

D4

D5

Do

D2D1

C2

C1

C3

C4

C5

CO R

s

Llk

Lm

NP NS

+-

++

+

+

-

-

-

-

-

-

+

Analysis and Implementation of a New Single Switch, High Voltage Gain … 15

Mode I Mode II Mode III

t0 t1 t2 t3

LmpI

VGS

iLm

iS

iD2,

iD5

iD3,

iD4

t

t

t

t

t

TS

DTS DLTS

Fig. 4. Theoretical waveforms of the proposed converter at the

DCM operation.

D3

D4

D5

Do

D2D1

C2

C1

C3

C4

C5

CO R

s

Lm

NP NS

+-

+

+

+

+

+

-

-

-

-

-

-

+

Vo

Vin

(a)

D3

D4

D5

Do

D2D1

C2

C1

C3

C4

C5

CO R

s

Lm

NP NS

+-

+

+

+

+

+

-

-

-

-

-

-

+

Vo

Vin

(b)

Vo

Vin

D3

D4

D5

Do

D2D1

C2

C1

C3

C4

C5

CO R

s

Lm

NP NS

+-

+

+

+

+

+

-

-

-

-

-

-

+

(c)

Fig. 5. Current flowing path of operating modes during one

switching cycle at DCM operation. (a) Mode I. (b) Mode II. (c)

Mode III.

and C5 are in series with the source and Lm, and give their

energy to CO and the load R. This mode ends at t=t2 when Lm

is discharged.

3) Mode III: [t2-t3] Fig. 4(c)

In this mode, the switch S remains off and the Lm current is

zero. Therefore, the load R is supplied by CO.

III. STEADY-STATE ANALYSIS OF THE

PROPOSED CONVERTER

A. CCM Operation

Modes I and III are very short, and can be neglected in the

calculation of the converter DC gain. In modes III and IV the

energy of the leakage inductor Llk is released to the clamp

capacitor C1. As shown in the appendix, the duty cycle of the

charging clamp capacitor C1, if mode III is neglected, is:

=

=

(1)

where tc1 is the charging duration of C1, and Ts is the

switching period. Applying the voltage-second balance

principle on Llk and Lm yields:

=

()

() (2)

,=

(3)

where k is the coupling-coefficient and it is equal to

k=Lm/(Lm+Llk).

By using (2), (3) the voltage of the clamp capacitor C1 can

be obtained as:

= +

+ =

+

()

() (4)

Using (3), the voltage across the switched capacitors C3,C4

can be written as:

= = =

=

(5)

Using (5), the voltages of the lifting capacitor C2 and the

switched capacitor C5 are obtained as:

= + + = (

+

()

()) (6)

= + = (1 +

) (7)

The output voltage VO is given as:

= + + +

+ (8)

Substituting (3),(4),(6) and (7) into (8) results in the DC

voltage gain MCCM as:

=

= ()

() (9)

Fig. 6 shows the voltage gain variations versus the duty

ratio of the proposed converter, in the CCM operation for

various coupling coefficient k=1, 0.95 and for n=1.5, 2, 3, 4.

Fig. 6 concludes that the voltage gain is not sensitive to the

coupling coefficient k.

16

V

V

Fi

va

Fi

co

op

du

[1

D

B

in

A

w

6

Vo/Vin

Vo/Vin

ig. 6. Voltage ga

arious value of n

ig. 7. Voltage

onverter and t

peration when n

For k=1 the id

Fig. 7 shows v

uty ratio of the

15]-[19] when k

The voltage st

D5, Do are:

. DCM Operat

In the previo

nductance, thre

According to Fig

written:

ain versus duty

n, k.

e gain versus

the converters

n=2.

deal CCM voltag

variations of the

e proposed con

k=1 and n=2.

tress of switch

tion

ous section, w

e major opera

g. 4 in mode I

Journal of Po

ratio in the CCM

duty ratio of

in [15]-[19]

ge is:

e CCM voltage

nverter and the

S and diodes D

.

while neglecting

ational modes

I, following equ

ower Electronic

M operation for

the proposed

in the CCM

(10)

gain versus the

e converters of

D1, D2, D3, D4,

(11)

(12)

(13)

(14)

g the leakage

are described.

uations can be

(15)

(16)

D

D

cs, Vol. 18, No.

r

)

f

where ILm

balance pr

where DL

Consideri

Therefo

Accord

equations

Writing

(22), VC2 a

The out

Substitu

Therefo

As expr

the charg

equal. Th

Since t

current of

The no

defined as

Equatio

converter

1, January 20

mp is the peak

rinciple to Lm y

L is the duty

ing 0 an

ore, the seconda

ding to Fig. 5(b

can be written:

g the voltage eq

and VC5 are obta

tput voltage is:

uting (19), (20)

2

ore:

ressed in the Ap

es and conduct

erefore, the Do

the average cur

f the load:

ormalized mag

s:

ons (17),(27)-(3

in the DCM:

18

value of Lm. A

ields:

cycle of the c

nd substituting

ary winding vol

b) and using (19

:

1

quations for Fig

ained as:

1 1

, (23) and (24)

1

3

ppendix, in the

ting durations o

peak current is

rrent of DO is

gnetizing induc

≡

30) yields the dc

1

Applying volt-

0

conducting dio

(15) into (18) y

ltage in mode II

9), (20) the fol

g. 5(a) and usin

11

into (25) yields

2

same way, in m

of D1, D3, D4,

:

equal to the a

ctor time cons

c gain of the pr

1

(17)

-second

(18)

ode Do.

yields:

(19)

I is:

(20)

llowing

(21)

(22)

ng (21),

(23)

(24)

(25)

s:

(26)

(27)

mode II

Do are

(28)

average

(29)

stant is

(30)

oposed

(31)

C

of

th

ca

n=

pl

th

pr

th

co

se

in

re

w

im

lo

vo

in

lo

D

co

ob

Si

V

V

T

o

S

s

c

Q

C. BCM Conditi

In the boundar

f the CCM and

he boundary nor

an be expressed

The variation c

=2 for this con

lotted in Fig. 8.

hat converter op

roposed convert

he converters pr

The comparis

onverters in [1

eries elements b

ncreases the p

esults in a highe

IV.

To verify the

with the speci

mplemented.

The first step

oad duty cycle

oltage stress. O

n a higher rms

osses. An appro

D=0.6. Accordin

onverter, and

btained. In this

ince the windin

Voltage gain

Voltage stress o

The highest vol

on diodes

Series elements

switch and clam

capacitor

Quantities of di

Analy

COMPARIS

ion

ry condition mo

DCM operatio

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d as:

.

curve of

nverter and the

For each conve

perate in the CC

ter has a wider

esented in [15]-

on among the

5]-[19] are sum

between the swi

parasitic induct

er voltage spike

DESIGN GU

EXPERIMEN

theoretical an

ifications in

of the design

e. A larger du

On the other han

(root-mean-squ

opriate duty cyc

ng to the inpu

using equation

example, assum

g turn numbers

C

on switch

tage stress

s between

mp

odes

ysis and Implem

SON AMONG THE

ode (BCM), the

ns are equal. Fr

etizing-inductor

versus the duty

e converters of

erter, if τLm is gr

CM. As this fig

CCM operation

-[19].

proposed conv

mmarized in T

itch and the clam

tance and resi

across the swit

UIDELINES AN

NTAL RESULT

nalysis, a proto

Table II is

is selecting th

uty-cycle result

nd, a lower dut

uare) current a

cle selection is

ut and output v

n (10), the tur

ming D=0.6 re

N1

and N2 are s

Converter

in [15]

C

i

1 diode 1

4

mentation of a N

TA

PROPOSED CONV

e voltage gains

rom (14), (31),

r time-constant

(32)

y cycle D, with

f [15]-[19] are

reater than τLmB

gure shows, the

nal region than

verter and the

Table I. More

mped capacitor

istance, which

ch.

ND

TS

otype converter

designed and

he nominal full

ts in a higher

ty-cycle results

and conduction

s considered as

voltage of the

rns ratio n is

esults in n=1.3.

small, n=1.5 is

Converter

in [16]

1 diode and

1 capacitor

4

New Single Sw

τLmB

ABLE I

VERTER AND CON

B,

Fig. 8. Bo

converter

Paramet

Maximu

Input DC

Output D

Switchin

C

Compon

Power sw

Schottky

Fast diod

Fast diod

Coupled

Capacito

Capacito

Capacito

Converter

in [17]

1 diode

6

witch, High Volta

NVERTERS IN [15

oundary conditio

in [15]-[19] und

THE PROT

er

um output power

C voltage

DC voltage

ng frequency

COMPONENT SPEC

nent

witch (MOSFET

y diode D1

des D3,D4,D5

des D2,Do

d inductor

ors C1,C3,C4

ors C2, C5

or Co

Converter

In [18]

1 diode

6

age Gain …

]-[19] FOR k=1.

on of the propose

der n=2.

TABLE II

TOTYPE SPECIFICA

r

TABLE III

CIFICATIONS OF T

Specifi

T) IRF441

MBR20

MUR 8

MUR 8

n=1:1.5

, Llk=.

2*10µF

10µF, 2

220µF,

Converte

in [19]

2 diode

1 capac

5

ed converter and

ATIONS

Value

200W

28 V

380 V

50 KHz

THE PROTOTYPE

cation

10

0100CT

820

830

5 , Lm=80µH

.4µH

F, 100V, MKT

250V, MKT

450V

er Propos

conver

s and

citor 1 dio

6

17

d

sed

rter

ode

6

D

18

Fi

yi

op

Lm

op

Lm

di

(4

C

ca

ca

w

is

th

ca

ca

C

an

th

co

co

Fi

dr

pe

Th

co

sw

sw

sw

sw

le

co

sh

it

ou

vo

8

ig. 9. Prototype

selected. Ther

ielded. In the n

peration is selec

m is obtained.

peration is ch

m=83µH is yiel

iodes are obtain

4)-(7) are used t

C3, C4, C5. Sinc

apacitors C1, C

apacitors are ob

where Io is the lo

the ripple facto

he ratio of the

apacitor averag

apacitor. By ch

C1=16µF, C2=6.

nd Fig. 9 show

he implemented

Fig. 10 prese

onverter under

onfirm the stea

ig. 10(a) show

rain-source volt

eak voltage Vds

herefore, a MO

onduction losse

witch S turns o

witch S turn

witching turn o

witch turns off,

eakage inductor

onduction time

how that when t

is off D3 and

utput voltage o

oltage and outp

of the proposed

refore, the theo

next stage, the

cted, and by usi

In this examp

hosen as 25%-

lded. The volta

ned based on E

to obtain the vo

e the charges

C2, C3, C4, C5 ar

btained as:

∆

∆

oad current, Ts

or of the capaci

capacitor peak-

ge voltage. Vi i

hoosing r=.01,

4µF, C3=C4=1

the component

converter, resp

nts experiment

r full load co

ady-state operat

ws the leakage

tage of the swit

is limited to 85

OSFET with a

es can be used

on under almos

off interval, w

off losses. Fig

the clamp diod

r energy is rele

of D1 is consist

the switch is on

D4 conduct. Fi

of the converte

put current wh

Journal of Po

d converter.

oretical duty cy

range of the c

ing (30) and (31

ple, the range

-100% full loa

age stresses of t

Equations (11)-(

oltage of the cap

absorbed or pr

re all equal, the

.

is the switching

itor voltage, wh

-to-peak ripple

is the average

the size of the

18.7µF, C5=10.

t specifications

pectively.

tal results obta

onditions. The

ting modes of

e inductance cu

tch Vds, which

V.

a low withstan

d. Fig. 10(b) s

st ZCS. Fig 10

which is used

. 10(d) shows

de D1 starts to c

ased to the cap

tent with (1). Fi

n, D2 and D5 con

ig. 10(i) shows

er. Fig. 11 sho

hen load steps

ower Electronic

ycle D=0.57 is

converter CCM

1), the value of

of the CCM

ad. Therefore,

the switch and

(14). Equations

pacitors C1, C2,

roduced by the

e size of these

(33)

g period, and r

hich is equal to

voltage to the

voltage of the

capacitors are

4µF. Table III

and a photo of

ained with the

se waveforms

the converter.

urrent iLlk and

shows that the

nd voltage and

shows that the

0(c) shows the

d to calculate

that after the

conduct and the

pacitor C1. The

igs. 10(e)-10(h)

nduct and when

s the input and

ows the output

up/down from

cs, Vol. 18, No.

f

f

d

Po=70W t

Table

capacitors

These re

capacitors

To estim

the condu

inductor,

are estima

0.95, the

approxim

The re

total copp

coupled-in

inductor c

The con

multiplica

voltage d

VD1=0.7V

the diode

are:

The tur

switch ou

of the swi

According

Coss disch

on losses

Using F

Therefo

Accord

1, January 20

to a full load of

IV presents t

s C1, C2, C3,

esults show th

s are consistent

mate the efficie

uction losses o

as well as the t

ated. Assuming

RMS value of

ately equal to:

√

sistance of IRF

per resistance

nductor is 35

conduction losse

0. ∗ nduction losses

ation of their

drop. The ave

is equal to

V, VD3=VD4=VD

e datasheets, th

0.526 ∗ 0. 3.06

rn-on switching

utput capacitor (

itch voltage and

g to the data sh

harged energy i

are:

∗Fig. 10(b), the s

∗

ore, the total sw

ding to Fig. 10(c

50 ∗ 1 6

18

f Po=200W.

the measured

C4, C5 in acc

hat the measu

with the theore

ency of the conv

of the switch,

turn on and turn

g that the initial

the input or sw

√

.∗∗√

F4410 in the o

transferred to

5mΩ. Therefo

es , ∗

.009 ∗ 9.962 0.035 ∗

of the diodes a

average curren

erage current

the load curr

D5=0.94V and V

he diodes cond

0.526

!

"#

7 3 ∗ 0.94 losses are due t

(Coss) during tur

d current during

heet of an IRF4

is 1µJ. Therefo

∗ 1$ ∗ 50second term due

%& ∗ %& ∗ =witch turn-on los

0.05 c), the turn off l

∗ %&

∗∗ 10' ∗ 85 ∗ 8

DC voltage

cordance with (

ured voltages

etical calculation

verter under a fu

diodes and co

n off switching

l efficiency is e

witch current ID

√. 9.96

on-state is 9mΩ

the primary

ore, the switc are:

0.89

9.96 3.47are almost equa

nt and their f

through the

rent. By cons

VD2=VDO=1.15V

duction losses

2 ∗ 1.15 to the discharge

rn-on, and the o

g a switching in

4410, at Vds=68

re, the switchin

0 0.05e to the overlap

=0.5

sses are equal to

0.5 0.55osses are:

∗ %& ∗ 80 0.57

of the

(4)-(7).

of the

ns.

ull load,

oupled-

g losses

qual to

DS-rms is

(34)

Ω. The

of the

ch and

(35)

(36)

al to the

forward

diodes

idering

V from

(37)

(38)

e of the

overlap

nterval.

8V, the

ng turn

39 is:

(40)

o:

41

(42)

Analy

(a)

(b)

(c)

(d)

(e)

ysis and Implem

)

)

)

)

)

mentation of a NNew Single Sw

Fig. 10. E

conditions

Fig. 11. L

Po=200W

witch, High Volta

Experimental re

s.

Load variation

.

age Gain …

(f)

(g)

(h)

(i)

esult of the con

between Po=70

nverter under fu

0W and a full-l

19

ull load

load of

20 Journal of Power Electronics, Vol. 18, No. 1, January 2018

E

ffic

iency

(%

) TABLE IV

MEASURED AND ESTIMATED DC VOLTAGE OF THE CAPACITORS

C1, C2, C3, C4, C5, Co

Parameter Vc1 Vc2 Vc3 Vc4 Vc5 Vco

Measured

DC Voltage 68V 160V 57V 57V 95V 380V

Estimated

DC Voltage 65V 163V 55V 55V 97V 380V

Output power (watts)

Fig. 12. Measured efficiency under various output powers.

Therefore, the estimated efficiency at a full load is:

=

=

.= 95.9% (43)

The measured efficiency of the proposed converter is

shown in Fig. 12. The maximum efficiency is 96.1%, which

occurs at an output-power of 80W. The full load efficiency is

94.7%. The difference between the estimated efficiency

(95.9%) and the measured efficiency (94.7%) at a full load is

due to the core losses and other losses.

V. CONCLUSIONS

This paper proposed a new high step up DC-DC converter.

By using a coupled inductor and utilizing the switched

capacitor and voltage lift techniques, a high voltage gain is

achieved. In this converter, the energy of the leakage

inductance is recycled via a passive clamp circuit and the

switch peak voltage is limited at 85V. Therefore, a MOSFET

with a low withstand voltage and low conduction losses can

be utilized. The steady-state operation of the converter in the

CCM and the DCM is analyzed and the boundary condition is

calculated. It is shown that the proposed converter has a high

voltage gain and a wide CCM operation range with a low

turn-ratio coupled inductor. A laboratory prototype is

implemented in the laboratory. The prototype verifies the

theoretical analysis. Finally an analysis of the losses is carries

out and the experimental efficiency is obtained.

APPENDIX: Dc1 CALCULATION

Dc1 is the conducting duty-cycle of the diode D1. To

calculate Dc1, the ripple of the magnetizing inductor current ILm

is neglected. In modes III and IV, the leakage inductor energy

is released to the clamp capacitor C1. Since the interval of

[t2-t3] is very short, it is neglected. In the [t3-t4] interval, the

D1 current linearly decreases from iLm to zero. Therefore, the

charge value of the capacitor C1 is:

=

(44)

In steady-state operation, the charge balance principle

yields:

=

(45)

=

=

(46)

=

(47)

Thus, considering that the charging time of C3, C4 is equal to

the discharging time of the capacitors C2, C5, the current of

these the capacitors are equal:

=

=

= (48)

Therefore, in the [t4-t5] interval, the current of the capacitor

C2 is equal to:

=

(49)

During the [t3-t4] interval, the current of C2 increases from

zero to iLm/(3n+1). Therefore, the total charge of C2 that

discharges in the [t3-t5] interval is equal to:

=

1 − − +

(50)

In steady-state operation, the charged and discharged

charges of C1, C2 are equal (Qcharge = Qdischarge). Therefore,

using (44), (46) and (50), Dc1 is obtain as:

=

()

(51)

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in 197

degree

Isfahan

Iran, i

presen

in Elec

Isfahan

nclude high step

onverters.

Seyed

from t

Tehran

the U

1991;

Eindho

Eindho

Electri

was a Professor

y, College Stati

ico, Mayaguez,

n - Madison, Ma

d as an Assistant

gy, Isfahan, Ira

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o a Senior Mem

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k Honarjoo was

76. He receive

es in Electrical

n University of

in 1998 and 200

ntly working tow

ctrical Engineeri

n, Isfahan, Iran

p up DC-DC co

d M. Madani re

the Sharif Univ

n, Iran, in 1989

University of Te

and his Ph.D

oven Universi

oven, Netherlan

ical Power Engi

r or Visiting Pro

ion, Texas, US

Puerto Rico; a

adison, WI, USA

t Professor at th

an. He is pres

e University of

mber of the IEEE

electronics and e

and R. Barzeg

verter structure u

tage stress on th

6, No. 6, pp. 200

step-up convert

wer Electron., V

ng, and J. F. Ch

converter with

s,” IEEE Trans.

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ctor and diode-ca

lectron., Vol. 29

Huang, “High

ed inductor for f

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015.

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coupled inducto

r Electron., Vol

high step-up co

capacitor struct

wer Electron., V

ovel high step-u

inductor and

energy system,”

o. 7, pp. 4974-49

s born in Isfaha

ed his B.S. and

Engineering fr

f Technology, I

01, respectively

wards his Ph.D.

ing at the Unive

n. His current r

onverters and m

eceived his B.S.

versity of Techn

; his M.S. degre

ehran, Tehran, I

D. degree fro

ity of Techn

nds, in 1999,

ineering. From 2

ofessor at Texas

SA; the Univer

and the Univer

A. From 2005 to

he Isfahan Unive

sently working

f Isfahan, Isfahan

E. His current r

electric drives.

21

arkhoo,

using a

he main

05-2015,

ter with

Vol. 20,

hen, “A

single

Power

.

DC–DC

apacitor

, No. 2,

step-up

fuel cell

ectron.,

step-up

ors and

. 8, No.

onverter

ture for

Vol. 16,

up dual

voltage

” IEEE

983, Jul.

an, Iran,

d M.S.

om the

Isfahan,

y. He is

degree

ersity of

research

multiport

degree

nology,

ee from

Iran, in

om the

nology,

all in

2000 to

s A&M

rsity of

rsity of

o 2011,

ersity of

as an

n, Iran.

esearch

22

w

cu

un

in

2

where he is pres

urrent research

ninterruptible po

n power electroni

Mehdi Niroo

Iran, in 1979.

Ph.D. degrees

the Isfahan U

Isfahan, Iran

respectively.

the Departme

the Universit

sently working a

h interests

ower supplies, sw

ics and renewabl

Journal of Po

omand He was b

He received his

s in Electrical En

University of Tec

n, in 2001, 20

Since 2010, he

ent of Electrical

ty of Isfahan,

as an Assistant

include powe

witching power s

le energy.

ower Electronic

born in Isfahan,

s B.S., M.S. and

ngineering from

chnology (IUT),

004 and 2010,

has been with

Engineering at

Isfahan, Iran,

Professor. His

er electronics,

supplies, control

cs, Vol. 18, No.

h

t

Technolog

in journal

interests i

soft-switch

Ph.D. Diss

1, January 20

Ehsan

1982.

degree

Isfaha

Iran, i

He is

Memb

Compu

gy. He is the aut

ls and conferen

include dc–dc c

hing techniques.

sertation Award

18

n Adib was bor

He received his

es in Electrical

n University of

in 2003, 2006 a

s presently wo

ber in the Depart

uter Engineering

thor of more tha

nce proceedings

converters and t

. Dr. Adib was

from the IEEE I

rn in Isfahan, I

s B.S., M.S. and

Engineering fr

f Technology, I

and 2009, respe

orking as a

rtment of Electri

g, Isfahan Unive

n 100 papers pu

. His current r

their application

a recipient of th

Iran Section, in 2

Iran, in

d Ph.D.

rom the

Isfahan,

ctively.

Faculty

ical and

ersity of

ublished

research

ns, and

he Best

2010.