MICROCHIP MANUFACTURING by S. Wolf

Chapter 23CHEMICAL-MECHANICALPOLISHING (CMP)

© 2004 by LATTICE PRESS

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-2

CHAPTER 23 - CONTENTS

• History of CMP

• CMP Mechanisms

• CMP Equipment

• CMP Polishing-Tools

• CMP Pads & Slurries

• Endpoint Detection of CMP

• Cleaning Issues in CMP

• Dishing Problems & Thickness Non-Uniformity Within Wafers After CMP

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-3

PLANARIZATION

Different Degrees of Planarization

• More Levels of Interconnect Greater Planarization

• 2-Levels: Smoothing

• ILD Reflow

• 3-Levels: Partial-Planarization

• Resist-Etchback• Spin-On-Glass

• 4 (or More)-Levels: Global-Planarization

• Chemical-Mechanical Polishing

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-4

INTRODUCTION TO CHEMICAL-MECHANICAL POLISHING (CMP)

(a) Schematic of Rotary-Table CMP System(b) Photo of Rotary-Table CMP-Tool

• Global Planarization (GP) Enables ULSI

• Step-Coverage• Depth-of-Field Budget

• CMP Provides GP• Invented by IBM - Mid-1980s

• Industry Proliferation -1990s

• CMP Applications• Interlevel Dielectric CMP• Shallow-Trench-Isolation• Tungsten CMP• Copper CMP

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-5

CMP OF METAL LAYERS

Schematic Representation of CMP-Model of Metal-Films

• Various Metals Polished in ULSI• Copper• Tungsten• Tantalum (& TaN)• Titanium (& TiN)

• Basic Model of Metal CMP

• Chemical-Reaction Oxidizes Metal-Surface

• High-Spots are Abraded Away Exposing New-Metal

• New-Metal is Oxidized• Low-Spots not Affected Since No Abrasion Occurs

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-6

CMP OF DIELECTRIC LAYERS (SiO2)

(a) CMP Erosion on Leading-Edge of Features ofOxide-Steps (b) Schematic of Narrow & Wide Ox-ide-Steps Polished by CMP, as Function of Time

• SiO2 Polishing-Models are “Empirical”

• More “Art” than ”Science”

• Rely on History of Lens-Grinding

• Not Like Metal-CMP-Models: Can’t “Oxidize” an Oxide!

• Clues: Preston’s Law

R = Kp P v

R = Glass Polish-Rate Kp = Preston Constant P = Down-Pressure v = Velocity of Table

• Still Mostly -

Trial & Error

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-7

CMP PROCESS-INTEGRATION ISSUES

All Components of CMP must be Successfully Integ-rated to Develop a Production-Worthy CMP-Process

• Like Lithography: CMP has Many Components

• All Must Work Together (Process Integration)

• Polishing Tools

• Consumables

• Pads• Slurries

• Slurry Storage/ Distribution System

• Cleaning Module

• Endpoint Detection

• Metrology Systems

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-8

CMP POLISHING-TOOLS

Detailed view of Novellus Auriga Polishing Tool

• First CMP Polishing-Tools were Modified Wafer-Polishers

• CMP Requires Finer Capability: 0.5-µm vs 5-10-µm

• Types• Rotary-Table (Applied, Strasbaugh)

• Orbital (Speedfam/Novellus)

• Linear (Lam)

• Early Tools - Single-Platen

• Today - Multi-Platen

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-9

CONSUMABLES: CMP POLISHING PADS

Photo of CMP Polishing Pads

• Pad: Polishing-Table Material In Contact with Wafers

• Drags Slurry-Particles Under Wafer as Table Rotates

• Cast & Sliced Polyurethane w/ Grooved-Surface

• Rigid or Flexible (or Hybrid)

• Polish 400-800 Wafers

• Vendors

• Rodel• Cabot

• Fujimi

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-10

AGING OF CMP POLISHING PADS

SEM of (a) New Polishing Pad(b) Surface of a Glazed Pad

• Over-Time: Slurry-Particles Clog Pad Pores - Glaze Surface• Decreases Wafer-to-Wafer Polish-Rate • To Keep Polish-Rate Constant: Rejuvenate Pad

• Pad-Conditioning Arm:• Diamond-Abrasive Surface• Swept Over Pad

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-11

CMP SLURRIES

(a) SEM of Colloidal-Silica Slurry Particles(b) Fumed-Silica Slurry-Particle Formation

Schematic of a Slurry-Management Systemwith Metrology, Auto-Dosing, & Filtration

• Tiny, Abrasive Particles Sus- pended in Aqueous-Solution

• Slurry Properties

• SiO2-Layer Slurries (in KOH)

• Colloidal Silica • Fumed Silica

• Metal-Layer Slurries

• Alumina • Solution-Composition Depends on Metal-Layer

• Slurry-Distribution System

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-12

CMP END-POINT-DETECTION

Wafer-Frontside Laser-InterferometryEndpoint-Detection for Dielectric-CMP

• Film-Thickness-Reduction Requires Tight Control

• Need to Know CMP End-Point

• INLINE: Measure Thickness Before & After CMP

• REAL-TIME (In-Situ): Measure Thickness During CMP

• Wafer-Frontside Laser-Interferometry

• Wafer-Backside Optical-Sensing

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-13

POST-CMP CLEANING

AMAT Mirra Mesa Cleaning-Module Layout

• CMP is a Dirty Process• Residual-Slurry After CMP: Wafer Defects• Must Remove All Slurry Particles & CMP Residue• Use Post-CMP Cleaning Process

• Brush-Scrubbing (Double-Sided)• Megasonic

• UPW-Rinse

• Dry-In/Dry-Out

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-14

DISHING & EROSION PROBLEMS OF CMP

Origin of Dishing-Effect in CMP: (a) Polish-ing-Pad Flexes into Trench-Opening(b) Formation of Concave-Surface(c) Trench-Area is “Dished” after CMP

• If Flexible-Pads Used: Higher Downforce in Wide-Trench Center

• More Material Removed than at Trench-Edges

• After CMP: Material in Wide-Trenches is “Dished”• Interconnect-Capacitance

Increases

• In Arrays of Closely- Spaced Metal-Lines - Erosion of Dielectric- Material Between them Occurs

• Dishing + Erosion

• Control-Loss of Metal-Line Resistance

• How to Solve these Problems?

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-15

UNIFORMITY PROBLEMS OF CMP

If Rigid-Pad is used for CMP: (a) Films on Flat-Wafersare Uniformly Polished (b) Films on Tapered-Wafers Polished Thinner over Thick Wafer-End (c) In Wafers w/ Variations, Film Polished Thinner over Thick-Areas

• Rigid Polishing-Pads• Good Planarity Within Die (Less Dishing & Erosion)• Poor Film-Thickness-Uniformity Across Wafer

• For Flat-Wafers: No Problem• But, for Non-Flat Wafers: Polishing Nonuniformity Arises

• Hybrid-Pads• Air-Bearing Beneath Polish Belt

MICROCHIP MANUFACTURING © 2004 by LATTICE PRESS Sunset Beach CA 23-16

SUMMARY OF KEY CONCEPTS• Global-Planarization Capability Must Exist for ULSI

• Surface-Step-Heights Become too Severe• DOF Budget of Lithography is Too Small

• CMP Enables Global Planarization

• Multilevel-Interconnects with as Many Levels as Needed can be Fabricated with Aid of CMP

• Also Helps STI-Fabrication• Dual-Damascene Process Uses CMP to Erode Cu

• Challenges of CMP• Dishing & Erosion

• CMP of Low-k Dielectrics

• Effective Removal of 0.1-µm Particles after CMP