Joanna Ellis-Monaghan, St. Michaels College

Paul Gutwin, Principal Technical Account Manager, Cadence.

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• A set S of nodes ( the pins) hundreds of thousands.

• A partition P1 of the pins (the gates) 2 to 1000 pins per gate, average of about 3.5.

• A partition P2 of the pins (the wires) again 2 to 1000 pins per wire, average of about 3.5.

• A maximum permitted delay between each pair of pins (infinite unless there is a wire between the pins).

Netlist

,d x y

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Example

Gate Pin Wire

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The Wires

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The Wiring Space

Placement layer-gates/pins go here

Vias (vertical connectors)

Horizontal wiring layer

Vertical wiring layer

Up to 12 or so layers

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Netlist Layout

• Place the pins so that pins are in their gates on the placement layer with non-overlapping gates.

• Place the wires in the wiring space so that the delay constrains on pairs of pins are met, where delay is proportional to minimum distance within the wiring, and via delay is negligible

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Placement

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A Few Basic Questions

• Partition the netlist

• Leverage the hierarchy

• Identify congestion

• Automate small configurations

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PartitioningDivide the pins/gates into k roughly equal parts,

minimizing the number of hyperedges in the cutset.

• Optimal hypergraph bisection is NP

• Approximation heuristics—e.g. ‘coarsen’ the hypergraph by merging vertices, bisect, then ‘uncoarsen’ and refine.

(See Karypis, Aggarwal, Kumar, Shekhar: Multilevel Hypergraph Partitioning: Application in VLSI Domain)

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Leverage the Hierarchy• Designers think in ‘modules’

• Use the hierarchy tree to inform the partitioning.

* * * * * * * * * * (Netlist Level) * * * * * * *

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Identify Congestion• Identify dense substructures from the netlist

• Develop a congestion ‘metric’

• Brambles and tree width may be appropriate tools for this.

A

B

C

D

F

G

E H

Congested area

Routing

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Congested area

What often happens

What would be good

Real Life Congestion Examples

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Automate Wiring Small Configurations

Some are easy to place and route•Simple left to right logic•No / few loops (circuits)•Uniform, low fan-out•Statistical models work

Some are very difficult•E.g. ‘Crossbar Switches’•Many loops (circuits)•Non-uniform fan-out•Statistical models don’t work

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Control Signals

Crossbar Switch

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Control Signals

Single Direction Crossbar Switch

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Control Signals

Substructure

(Minimal layouts established for very regular structures: Mathukrishanan, Paterson, Sahinalp, Suel: Compact Grid Layouts of Multi-Level Networks, but no general heuristic)

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Some Possible Models• (Di)graph: pins = vertices, edges between pins which are

connected.

• Graph: gates = vertices, edges between gates which are connected.

• Two Hypergraphs: pins = vertices, H1=pins on the same gates, H2

= connected pins. (each vertex is in exactly one hyperedge in each of H1 and H2,, and a hyperedge in H1 intersects a hyperedge in H2 in at most one vertex)

• Single Hypergraph: gates = vertices, H = connected gates (ie contract H1 in the model above).

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Some Potential Tools

• Grid graphs

• Geometric thickness

• Graph drawing algorithms

• Hypergraph embeddings

Need to translate results to the wiring space!!