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THE RAPID DEPLOYMENT of gigabit I/O
buffers for key communication standards such
as Gigabit Ethernet, Infiniband, 3GIO, and
Sonet—as well as for high-bandwidth system
backplanes—presents several challenges for test-
ing. Testing these ICs requires expensive stand-
alone bit-error-rate test sets. Cost and excessive
test time make this approach impossible for vol-
ume production. However, the industrial trend
toward higher integration levels means that giga-
bit serial ports can serve as a standard I/O macro
for any IC, implying that all existing VLSI pro-
duction test systems must be retrofitted with cost-
effective gigabit test solutions. Thus, there is an
urgent need for a cost-effective technique to test
these gigabit transceivers on ATE in volume pro-
duction.1,2 This article introduces a low-cost
method to extend jitter testing to conventional
external loop-back testing (looping the transmit-
ted signal back to its own receiver) or golden-
device testing (using a known-good device to test
its link partner). The technique introduced is
independent of test platforms.
Serial communication transceivers Gigahertz transceiver devices once used
predominantly GaAs technology. With recent
improvements, CMOS, BiCMOS, and SiGe tech-
nology now provide lower cost, higher integra-
tion levels, and higher yield, making them more
attractive for many ASICs. Immediate applica-
tions for gigabit serial I/O buffers include the
computer and server backplane (NGIO/SIO/
Infiniband, Firewire IEEE 1394, and Flat Panel
Link) and short- and long-haul telephony and
data communication (ATM, Sonet/SDH, Gigabit
Ethernet, and Fibre Channel).
Besides the basic need for higher speed,
there is also a trend toward using high-speed
serial ports to replace very wide parallel buses
for interchip and interboard communication.
Serial ports will alleviate package pin-count
bottleneck problems for large SoC devices.
Most gigabit transceivers contain a transmit-
ter (Tx) and a receiver (Rx) section—that is,
there is one input and one output port. The
transmitter accepts data at a parallel input port
and converts it into a high-speed serial format.
Parallel bus width varies with applications—for
example, 4-, 8-, 10-, 16-bit lines, and so on. The
transmitter needs a clock input synchronized
with the parallel data. This clock serves to latch
in the data and synthesize the internal high-
speed serial-bit clock for the serializer. In prin-
ciple, it works like a data serializer with
reclocked high-speed differential data output,
as shown in Figure 1. The receiver accepts high-
speed serial data at its differential serial input
port. The internal clock recovery circuit gener-
ates a recovered clock derived from the data
and retimes the data. This retimed data is dese-
rialized and presented as parallel data on the
Jitter Testing for GigabitSerial CommunicationTransceivers
Transceiver Jitter Testing
66
Proper testing of transceivers requires the ability
not only to measure generated jitter but also to
inject in-band as well as out-of-band jitter for an
appropriate receiver tolerance test.
Yi Cai Agere Systems
Bernd Laquai and Kent LuehmanAgilent Technologies
0740-7475/02/$17.00 © 2002 IEEE IEEE Design & Test of Computers
output port. Some devices contain a built-in
frame (word boundary) alignment function to
recognize a word or frame delimiter. Therefore,
a gigabit receiver works like a data deserializer
with clock recovery and frame alignment, as
shown in Figure 1.
Jitter test challengesA high-speed digital serial communication
device’s basic function is to transmit data
through a medium to a remote receiver. To
receive the data and regenerate it using a clock
extracted from the incoming data stream, the
receiver must be immune to the timing jitter and
noise induced by the link partner and the trans-
mission medium.
Significance of jitter testingTo ensure a safety margin, it is important
that the transmitter generate as little jitter and
noise as possible. An eye diagram mask
explains this best. As Figure 2 shows, the eye
for the transmitted signal Tx is wide open. Jitter
noise should be controlled so that the actual
eye diagram lies outside the mask region. After
transmission through the medium, the eye
diagram shrinks horizontally by jitter and
noise, and vertically
by attenuation and
noise. The inner eye
diagram mask for
the received signal
defines the receiver’s
input acceptance tol-
erance. If the signal
presented at the Rx
input lies outside the
eye mask, the receiv-
er is expected to
recover the signal.
The opening between
the Tx and Rx eye
diagram masks deter-
mines the intercon-
nect noise budget.
The time axis of the
eye diagram is typi-
cally normalized to
the duration of a sin-
gle bit (bit time). The
67January–February 2002
Serialoutputport
Serialinputport
Linedriver
Linereceiver
Transmitter/serializer
Receiver/deserializer
Transceiver
Codinglogic
(optional)Tx
Rx
Referenceclock
Tra
nsm
issi
on m
ediu
m
Clockrecovery
Parallelinputport
Paralleloutput
port
Phase-lockedloop
Decodinglogicand
framealignment(optional)
Figure 1. Schematic of a serial communication transceiver device,
showing transceiver (Tx) and receiver (Rx) sections.
(a)
(c)
(b)
Tx eye maskRx eye mask
Jitterbudget
Jitterbudget
Attenuationbudget
Tx output Rx input
Figure 2. Eye masks on actual eye diagrams captured by an oscilloscope. Transceivers
are designed to transmit data through an interconnect with noise and distortion. The
transmitter should generate a minimum amount of output jitter (a). The receiver should
tolerate a maximum amount of input jitter (b). The margin between the receiver’s
tolerance and the transmitter’s intrinsic jitter represents the interconnect budget—that
is, the combined attenuation budget and jitter budget (c).
normalized unit is called a unit interval (UI).
To test the transceiver’s performance, we
need to measure jitter from the transmitter out-
put—a key figure of merit for Tx. We also need
to deliberately induce jitter and attenuation (as
the actual transmission medium will do) to test
the receiver input’s tolerance level—a key fig-
ure of merit for Rx.1
In general, most gigabit transceivers for line
interfaces use a phase-locked loop (PLL) to
generate the required high-speed bit clock for
transmission. On the receive side, a second PLL
or a delay-locked loop (DLL) extracts the high-
speed receive bit clock from the data.
Unfortunately, the PLLs and DLLs are exposed
to parametric variations of the manufacturing
technology. It is extremely challenging to
achieve an appropriately robust design with
respect to process variations. Verifying design
robustness requires extensive parametric test-
ing under the influence of jitter.
Spectral content of jitterThe receiver PLL is an analog timing recov-
ery loop that regenerates a high-speed clock
from data received. It compares the phase
between the data and the regenerated clock.
Without a voltage-controlled oscillator (VCO)
of its own, a receiver DLL is a digital timing
recovery loop that compares the input data
phase to multiple phases of the on-chip VCO in
the transmit PLL section.
The linear model of a PLL (shown in Figure
3) and its characteristics (shown in Figure 4)
help to further explain the jitter test challenge.
The linear model shows not only the regular
input ϕ1(s) and output phase ϕ2(s) signals in
the phase domain, but also additional random
VCO phase noise ϕr(s) injected into the loop.
Figure 4 shows a qualitative analysis of the
behavior in the spectral phase domain. The
PLL tracks phase noise below its natural fre-
quency, resulting in in-band jitter. Spectral
content of phase noise that is above the PLL’s
natural frequency results in out-of-band jitter.
The PLL cannot track it, and it will pass
through to the output.
A transmitter’s reference-clock jitter should be
suppressed as much as possible. This means
choosing a low corner frequency. However, if the
VCO generates phase noise beyond the selected
corner frequency, there will be out-of-band jitter
at the output. Selecting a higher corner frequen-
cy can avoid this situation and keep most VCO
noise in band. Because of the necessary com-
promise, the transmitter jitter contains a certain
amount of VCO-generated high-frequency jitter
that passes to the link partner receiver.
Transceiver Jitter Testing
68 IEEE Design & Test of Computers
Phasefrequencydetector
Loopfilter
Voltage-controlledoscillator
1/N
KLF(s) Ko(s)KD
r(s)ϕ
1(s)ϕ
2(s)ϕ
Figure 3. Linear model of a phase-locked loop, where s
is the complex frequency variable, N is the loop
multiplication factor, KD is detector gain, KLF is loop
filter gain, Ko is VCO control gain, and ϕr is random
phase noise generated by the VCO.
/ n)log(
ϕ2/ϕrl l(s)
ϕ2/ϕ1l l(s)
ω ω
In band Out of band
N
1
1
Figure 4. Phase transfer characteristics of
the linear phase-locked-loop model
illustrate the different responses for in-
band and out-of-band jitter. The transfer
function ϕ2/ϕ1(s) for input jitter shows a
low-pass characteristic, and the transfer
function ϕ2/ϕr(s) for the VCO jitter shows a
high-pass characteristic. In log(ω/ωn), ω is
angular velocity, and ωn is angular velocity
for normalization (PLL bandwidth).
Our design goal for the receiver is to track jit-
ter up to the highest frequency contained in the
incoming data such that the recovered bit
clock contains the same jitter as the data to be
sampled. We achieve this by choosing a corner
frequency that is as high as possible so that we
can track more high-frequency jitter, which oth-
erwise would be out of band.
Transceivers embedded in large digital
ASICs are particularly susceptible to out-of-
band jitter because of high-frequency ground
bounce and crosstalk from the digital circuitry.
The receiver PLL can no longer track this jitter,
directly reducing the jitter budget.
Other factors contribute to the total jitter
arriving at the receiver input. For example, a
lossy transmission medium and imperfectly ter-
minated lines also induce data-dependent jitter
(DDJ), and heated p-n junctions in the transis-
tor induce random jitter (RJ). We suggest a low-
cost jitter test that purposely induces DDJ on
top of the device’s intrinsic DDJ and RJ, there-
by stressing the receiver under test.
Low-cost jitter test for volume production
Our test concept uses cable-equivalent fil-
ters in conjunction with external loop-back or
golden-device testing. Let’s see how it com-
pares with current methods.
Instrument- versus filter-based jitter testTypical jitter measurement techniques
include
� an oscilloscope eye-diagram template,
� bit-error-rate-analyzer eye-width analysis,
� spectrum analysis,
� time-interval-analyzer measurement, and
� high-bandwidth undersampling.
We can immediately exclude the first four
methods from production test for high-volume,
low-profit-margin devices because these tech-
niques take 30 seconds or more to measure the
jitter from a serial data stream. Moreover,
instruments for the measurement techniques
just listed are not all readily available on exist-
ing ATE systems. The undersampling technique
is also a challenge on ATE because it requires
a stable and linear time-based sampler with
picosecond resolution.3
Typical jitter injection techniques include
phase modulation and wave shaping using an
arbitrary waveform generator (AWG). For current
2.125- to-3.125-Gbps CMOS transceivers, existing
AWGs on ATE do not have adequate sampling
rates and bandwidth. The phase modulation
technique is a viable solution, but it requires a
multigigabit pattern generator with a modulated
multigigahertz clock. This is not readily available
in most ATE systems.
As macrocells, gigabit serial transceivers are
finding their way into many high-volume, low-
price ASICs. In such cases, creating an ultra-
high-performance customized test set1 for
production is generally not an option. This
challenge requires leveraging existing ATE
resources. With all these limitations and the
need for immediate volume production, semi-
conductor manufacturers must either compro-
mise product quality or use a strategy that
justifies eliminating or combining specific tests.
The external loop-back or golden-device
approach that can induce jitter may reduce test
time and capital expense. We propose using a
cable-equivalent filter as the most realistic way
of generating jitter introduced by the transmis-
sion medium. As Figure 5a (next page) shows,
the loop-back test uses the on-chip transmitter
as the gigabit data source. The signal passes
through a filter designed to emulate a nonideal
transmission medium with loss and dispersion.
When the data pattern varies the number of con-
secutive 0s and 1s, the filter attenuates the sig-
nal and adds the proper amount of jitter on top
of the transmitter’s intrinsic jitter. After jitter has
been injected, the jittered data is fed into the
receiver portion of the transceiver to test its jit-
ter tolerance. Because the jitter used to stress the
receiver is the sum of the transmitter’s intrinsic
jitter and the filter-injected jitter, it allows an
implied testing of Tx jitter output. The filter’s sig-
nal attenuation permits simultaneous testing of
receiver voltage sensitivity.
This jitter test, based on a loop-back test with
a jitter injection filter, verifies device perfor-
mance in five areas: transmitter at functional
speed, receiver at functional speed, receiver jit-
ter tolerance, receiver minimum detectable
69January–February 2002
level, and transmitter implied jitter generation.
Because throughput is as high as for a single
functional test, this is a very cost-effective tech-
nique. The jitter injection circuitry is strictly pas-
sive, so we expect it to be cost-efficient and
stable while requiring less-frequent calibration
than an active circuit. Moreover, a properly
designed cable-equivalent filter provides a trans-
ceiver environment closely resembling that of
the intended system application, where the
transmitted signal must pass through an inter-
face medium with attenuation and dispersion.
Another key advantage of using a filter for jit-
ter injection is the ability to precisely control the
jitter frequencies generated by varying the tran-
sition density (the number of consecutive 1s
and 0s). In particular, it’s possible to generate
jitter frequencies beyond typical PLL cutoff fre-
quencies. Equipment limitations on modulation
depth at higher frequencies make it difficult to
achieve an out-of-band jitter injection capabili-
ty with most conventional clock sources.
The filter-based technique’s major limitation
is its susceptibility to process variation, because
it is essentially a device self-test instead of a
test conducted with a calibrated instrument.
Normally, a calibrated instrument performs bet-
ter than the device itself. In addition, a passive fil-
ter with fixed-frequency response isn’t designed
to verify a transceiver’s jitter tolerance specifica-
tions at several data rates simultaneously.
Successful use of the technique requires
extensive characterization to properly establish
the test limits and guard bands. For example,
the amount of intrinsic jitter the transmitter gen-
erates can vary from part to part, resulting in
nonconstant jitter in the receiver after jitter
injection. To conduct a proper jitter tolerance
test with the filter-based loop-back technique,
we must understand the range of the Tx jitter
variation through extensive characterization.
For example, if the transmitter jitter varies
between 0.15 UI and 0.2 UI from part to part,
then to guarantee a 0.5-UI receiver out-of-band
jitter tolerance we must tune the DDJ filter with
the transmitter’s lower intrinsic jitter (0.15 UI).
Transceiver Jitter Testing
70 IEEE Design & Test of Computers
Rx
Tx
ƒ ƒ
AT
E te
ster
AT
E te
ster
Reference clockLow-jitter
clock source
ƒ
Golden device
Out_1
Out_10
In_1
In_10
Rx
Tx
Device under test
Out_1
Out_10
In_1
In_10Rx
Tx
Device under test
Out_1
Out_10
In_1
In_10
(a)
(b)
ƒ = jitter injection filter
Figure 5. Schematic diagrams for external loop-back test (a) and golden-device test (b), both with cable-
equivalent jitter injection.
In that case, if the filter delivers a 0.5-UI total jit-
ter to the receiver with a 0.15-UI jitter transmit-
ter, it will produce more than a 0.5-UI jitter with
a 0.2-UI jitter transmitter. Although this will
stress the receiver beyond its specification,
such a guard band is necessary to avoid ship-
ping devices with less than 0.5-UI jitter toler-
ance. The receiver-level sensitivity test and the
implied Tx jitter test will be similarly affected
by this transmitter and receiver interaction,
which is a given for loop-back test.
An alternative to a simple loop-back and
passive filter method is the use of a golden
device, connected as shown in Figure 5b. The
golden-device approach with thorough cali-
bration can reduce transmitter and receiver
interaction and enable asynchronous test.
Essentially, though, it is still a device self-test
without a calibrated instrument that can per-
form better than the device. The golden-device
test also requires more tester resources and
complicated test fixtures than the loop-back
test. This can be impractical for large ASICs
with multiple serial ports on the same chip.
Filter-based data-dependent jitter injection Some communication standards (for exam-
ple, the IEEE 802.3 10BASE-T Ethernet standard)
specify cable-equivalent filters for receiver tol-
erance testing.4 Other standardizing authorities
specify special patterns that accentuate data-
dependent jitter.5
Transmission of a repetitive clock will con-
centrate the energy around the clock signal’s
fundamental frequency. When random data is
serially transmitted, its energy is spread over a
wide spectral range. This spreading results from
the varying run lengths of 1s and 0s in a random
data signal. The key problem induced by this sig-
nal property is that the transmission path’s group
delay must be constant over a wide spectral
range to ensure undistorted transmission. When
the group delay is not constant over the full sig-
nal bandwidth, the distortion depends on the
transition density variations in a pattern; in other
words, the distortion will be data dependent.
The transmission path’s spectral characteris-
tic strongly influences the data dependency. In
many cases, the data-dependent distortion also
causes a data-dependent shift or jitter of the sig-
nal transitions with respect to a given threshold.
This effect significantly affects the receiver’s
operation when it extracts the clock from the
transitions in the distorted data received. Our
filter-based jitter injection technique closely
emulates the transmission path’s distortion
effects for certain applications.
Generation of data-dependent jitter can be
best visualized with a simulation result using a
simple low-pass transmission path characteristic.
Figure 6 shows the output of a simple low-pass fil-
ter with a binary sequence containing different
run lengths of 1s and 0s. The 20-bit sequence
0011111010 1100000101 serves as input.
The graph highlights the first 0 after five con-
secutive 1s and the first 1 after five consecutive
0s (bold segments of the waveform). The filter
attenuates fast-toggling bits more than long con-
secutive runs of the same bit value and has an
asymmetric step response. Therefore, the zero
crossing is significantly displaced in time when
a bit toggles immediately after a long run of 1s or
0s. In Figure 6, the dotted line represents the
input stimulus, and the solid line designates the
output (response), where the zero-cross points
are displaced in time. The data-dependent zero-
cross-point movement is the root cause of DDJ.
This becomes evident when looking at the data
eye, shown in Figure 7 (next page).
The bold waveform segments in Figure 6
determine the inner eye contour. Selection of an
appropriate pattern with a given periodic change
in run lengths can directly control the frequency
of the injected data-dependent jitter. The se-
quence used in Figures 6 and 7 with a10-bit per-
iod injects the jitter with a frequency of 100 MHz
71January–February 2002
10 2 3 4 5 6 7 8 9 1011121314151617181920
0.6
0.4
0.2
Vol
tage
0
−0.2
−0.4
−0.6Bit time (unit intervals)
Figure 6. A simple RC low-pass filter response to a binary
sequence of varying run lengths produces data-dependent jitter.
at a 1-Gbps data rate. A sequence of 0010 1101
would produce 250-MHz jitter at 1 Gbps.
Practical implementation issuesThe simple low-pass filter we described
serves only to illustrate the concept. Ideal char-
acteristics require more complicated types of
filters. We use a filter to create not only jitter
(horizontal data eye closure) but also attenua-
tion (vertical data eye closure). A simple filter
cannot provide enough flexibility in tuning
these two separate parameters. The design goal
for a DDJ injection filter is to achieve the opti-
mum ratio of vertical-to-horizontal eye closure,
emulating the worst-case transmission distor-
tion that the device is intended to tolerate.
Obviously, this varies by application. For exam-
ple, Sonet transceivers designed for long-haul
communications can tolerate far more attenu-
ation and jitter than system backplane applica-
tions designed for transmission over a short
distance.
For the filter-based jitter injection method-
ology to be suitable for production test, the fil-
ter designs must be simple, passive, and
insensitive to part variations. This is especially
true for ASICs with multiple transceiver ports
embedded.
Using simulation, we evaluated several differ-
ent filter designs to achieve the optimum ratio of
vertical-to-horizontal eye closure. Figure 8 illus-
trates a simulation result for a jitter
injection filter with the optimum
ratio. For a given horizontal eye clo-
sure, there is far less vertical eye clo-
sure than for a simple RC circuit. In
a loop-back or golden-device test, a
device transmitter supplies the seri-
al data stream for the receiver test.
The frequency spectrum and the
transmitter’s intrinsic jitter cannot be
simulated precisely. The final filter
design must be fine-tuned to the test
limits with a real device, as shown
in Figure 9. Figure 9a shows the
transmitter’s 2.5-Gbps intrinsic jitter.
Figures 9b, 9c, and 9d show the jit-
ter at the receiver input after filtering
with three different filter parameters.
By varying the filter parameters, we
gradually approached predetermined test limits,
vertically as attenuation and horizontally as jitter.
Although a higher-order filter provides more
flexibility for tuning the characteristic, in prac-
tice such filters are more difficult to replicate
reliably. Higher-order filters contain more
components, and every component must be
carefully and consistently matched for a multi-
gigahertz response.
For transceivers operating at various data
rates, the injected jitter can vary significantly by
data rate. Despite the constant device output
rise time (hence, the maximum signal band-
Transceiver Jitter Testing
72 IEEE Design & Test of Computers
1.25 1.35 1.45 1.55 1.65 1.75 1.85 1.95 2.05 2.15 2.25
0.6
0.4
0.2
Vol
tage
0
−0.2
−0.4
−0.6
Bit time (unit intervals)
Figure 7. Data eye of a simple filter response. The signal
waveform is decomposed into individual bit contributions to the
data eye.
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 1.00.80.60.40.2
Bit time (unit intervals)
Am
plitu
de
Figure 8. Simulation result for a jitter injection filter with an optimized eye
closure ratio.
width), the frequency contents inside this band-
width will redistribute with a data rate change.
The filter’s nonlinear characteristic will then
inject different amounts of DDJ. Figure 10
shows that intrinsic jitter varies slightly with the
data rate, and injected jitter varies significantly
with the data rate. Therefore, a single passive
filter with fixed-frequency response is not suffi-
cient to verify that a transceiver meets its jitter
tolerance specification simultaneously at sev-
eral data rates.
THE KEY ADVANTAGES of the modified external
loop-back approach or golden-device testing
with passive-filter-based jitter injection are low
cost, high throughput, out-of-band jitter capabil-
ity, and close resemblance to the intended sys-
tem application. Both techniques use existing
ATE capabilities without external instruments.
Replacing many conventional precision tests
with a single filter-based loop-back or
golden-device test reduces test time dramatical-
ly compared with the high-precision ATE
and external instrument hybrid tester.1 However,
the compromise between precision and cost
may not be acceptable for very high-end perfor-
73January–February 2002
(a) (b)
(c) (d)
Figure 9. Filter designed for a 2.5-Gbps transceiver is fine-tuned to
the test limit with a real device. Transmitter intrinsic jitter (a);
receiver input jitter after filtering with various parameters, 0.28 UI
(b), 0.31 UI (c), and 0.33 UI (d).
(a) (b) (c)
(d) (e) (f)
Figure 10. Intrinsic transmitter
jitter of the same transmitter
for three different data rates:
2.125 Gbps (a), 2.5 Gbps (b),
and 2.67 Gbps (c). Injected
jitter for the same transceiver
and the same filter for the three
different data rates: 0.25 UI at
2.125 Gbps (d), 0.35 UI at 2.5
Gbps (e), and 0.42 UI at 2.67
Gbps (f).
mance-based devices. In such cases, an instru-
ment-based hybrid tester must be used despite
its high cost and long test time.
Because filter-based loop-back testing is sus-
ceptible to IC process variation, successful use
of the filter-based production test requires
extensive characterization using precision ATE
and lab instruments to determine proper design
margins and test limits. �
Acknowledgments We thank Mark Barber, Kadaba Lakshmikumar,
John Khoury, Peter Metz, Jim Chlipala, and Sunil
Rane of Agere Systems (formerly Lucent Tech-
nologies Microelectronics Group), and Alfred
Rosenkraenzer, Ralf Stoffels, and Juergen Serrer
of Agilent for their technical help.
References1. Y. Cai et al., “Digital Serial Communication Device
Testing and Its Implications on Automatic Test
Equipment Architecture,” Proc. Int’l Test Conf.
(ITC 00), IEEE CS Press, Los Alamitos, Calif.,
2000, pp. 600-609.
2. “High Frequency Serial Communication: Technol-
ogy Requirement,” International Technology
Roadmap for Semiconductors, Test and Test
Equipment Section, 1999, pp. 64-65.
3. W. Dalal and D. Rosenthal, “Measuring Jitter of
High Speed Data Channels Using Undersampling
Techniques,” Proc. Int’l Test Conf. (ITC 98), IEEE
CS Press, Los Alamitos, Calif., 1998, pp. 814-818.
4. IEEE Std. 802.3 Part 3, Carrier Sense Multiple
Access With Collision Detection Access Method
and Physical Layer Specifications, Clause 14,
IEEE Press, Piscataway, N.J., 1996.
5. National Committee for Information Technology
Standardization (NCITS), T11.2/Project
1230/Rev. 10, Fibre Channel—Methodologies for
Jitter Specification, 9 June 1999.
Yi Cai is a member of thetechnical staff in the IC Testing Technology Group atAgere Systems (formerlyLucent Technologies Micro-electronics Group). His re-
search interests include high-speed IC testingdevelopment, signal integrity, and system-
timing-accuracy analysis. Cai has a BS in elec-trical engineering from Beijing University, Beijing,China, and an MS and PhD in electrical engi-neering from the New Jersey Institute of Tech-nology, Newark, New Jersey.
Bernd Laquai is a mem-ber of the product generationteam for the 93000 ATE plat-form at Agilent Technologies.He was responsible for thetechnical definition of Agil-
ent’s parametric test solution for high-speed ser-ial communication links. His research interestsinclude high-speed telecommunications anddata communications applications. Laquai hasa Dipl.-Ing. in electrical engineering from the Uni-versity of Stuttgart, Germany.
Kent Luehman is a leadtechnical consultant in AgilentTechnologies’ ATG Group,specializing in high-speedand mixed-signal testing onAgilent’s 83000 and 93000
ATE platforms. He has a BS and MS in electricalengineering from Stevens Institute of Technology,Hoboken, New Jersey.
Direct comments and questions about thisarticle to Yi Cai, Agere Systems, 555 Union Blvd.,Room 24U-019HB, Allentown, PA 18103;[email protected].
For further information on this or any other comput-
ing topic, visit our Digital Library at http://computer.
org/publications/dlib.
Transceiver Jitter Testing
74 IEEE Design & Test of Computers