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High Speed On-chip Interconnect Modeling and Reliability Assessment by Jiedong Diao A Thesis Submitted to the Graduate Faculty of Rensselaer Polytechnic Institute in Partial Fulfillment of the Requirements for the degree of DOCTOR OF PHILOSOPHY Major Subject: Electrical Engineering Approved by the Examining Committee: _________________________________________ Prof. John F. McDonald, Thesis Adviser _________________________________________ Prof. Yannick L. Le Coz, Member _________________________________________ Prof. Tong Zhang, Member _________________________________________ Prof. Toh-Ming Lu, Member Rensselaer Polytechnic Institute Troy, New York December, 2006

Jiedong Diao

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High Speed On-chip Interconnect Modeling and Reliability Assessment

by

Jiedong Diao

A Thesis Submitted to the Graduate

Faculty of Rensselaer Polytechnic Institute

in Partial Fulfillment of the

Requirements for the degree of

DOCTOR OF PHILOSOPHY

Major Subject: Electrical Engineering

Approved by the Examining Committee:

_________________________________________ Prof. John F. McDonald, Thesis Adviser

_________________________________________ Prof. Yannick L. Le Coz, Member

_________________________________________ Prof. Tong Zhang, Member

_________________________________________ Prof. Toh-Ming Lu, Member

Rensselaer Polytechnic Institute Troy, New York

December, 2006

ii

© Copyright 2006

by

Jiedong Diao

All Rights Reserved

iii

TABLE OF CONTENTS

LIST OF TABLES........................................................................................................... vii

LIST OF FIGURES ........................................................................................................ viii

ACKNOWLEDGMENT ................................................................................................... x

ABSTRACT .................................................................................................................... xii

1. Introduction................................................................................................................. xi

1.1 Research topic .................................................................................................... 1

1.2 Thesis outline ..................................................................................................... 2

2. Historical Review ........................................................................................................ 3

2.1 High Speed Interconnection............................................................................... 3

2.2 Transmission Line.............................................................................................. 6

2.3 MIS Transmission Line Theory ......................................................................... 9

2.3.1 Three Fundamental Modes..................................................................... 9

2.3.2 Quasi-TEM method................................................................................ 9

2.3.3 Lossless line ......................................................................................... 11

2.3.4 Low loss line ........................................................................................ 11

2.4 Effective Dielectric Constant ........................................................................... 12

2.5 Conformal Transformation............................................................................... 13

2.6 Skin Effect........................................................................................................ 14

2.7 Silicon Slow-wave ........................................................................................... 17

3. Modeling of Single Transmission Line ..................................................................... 19

3.1 General Analysis .............................................................................................. 19

3.1.1 Computing Output Waveform ............................................................. 19

3.1.2 Characteristic Impedance ..................................................................... 19

3.2 Basic Model Ignoring the Insulator Layer ....................................................... 20

3.2.1 Geometry.............................................................................................. 20

3.2.2 Equivalent Circuit ................................................................................ 20

iv

3.2.3 Effective Dielectric Constant ............................................................... 21

3.2.4 Analytical Solution .............................................................................. 22

3.2.5 Attenuation Constant............................................................................ 24

3.2.5.1 Conductor Loss ...................................................................... 24

3.2.5.2 Substrate Loss ........................................................................ 24

3.3 Extended Model Considering the Insulator Layer ........................................... 25

3.3.1 Geometry.............................................................................................. 25

3.3.2 Equivalent Circuit ................................................................................ 25

3.3.3 Effective Dielectric Constant ............................................................... 26

3.3.4 Analytical Solution .............................................................................. 27

3.3.5 Computing ki........................................................................................ 29

3.4 Numerical Computing...................................................................................... 29

4. Modeling of Two Coupled Lines............................................................................... 30

4.1 General Analysis .............................................................................................. 30

4.2 Model Ignoring Insulator Layer ....................................................................... 32

4.2.1 Equivalent Circuit ................................................................................ 32

4.2.2 Even Mode ........................................................................................... 33

4.2.3 Odd Mode ............................................................................................ 33

4.3 Model Considering Insulator Layer ................................................................. 34

4.3.1 Equivalent Circuit ................................................................................ 34

4.3.2 Even Mode ........................................................................................... 35

4.3.3 Odd Mode ............................................................................................ 35

4.4 Calculating Parameters..................................................................................... 36

4.4.1 Effective Dielectric Constant ............................................................... 36

4.4.2 Capacitance .......................................................................................... 36

5. Simulation Results of the First Improved Model ...................................................... 38

5.1 Results of A Single Line .................................................................................. 38

v

5.1.1 Pulse Propagation along Microstrip Line............................................. 38

5.1.2 Conductor and Substrate Attenuation Constants αc and αd................. 40

5.1.3 Total Attenuation Constant   ............................................................. 42

5.1.4 Factors that Affect Pulse Propagation.................................................. 44

5.1.4.1 Pulse Width............................................................................ 44

5.1.4.2 Insulator Layer Thickness...................................................... 47

5.1.4.3 Insulator Dielectric Constant ................................................. 49

5.1.4.4 Substrate Resistivity............................................................... 52

5.1.4.5 Conductor Materials............................................................... 55

5.2 Simulation Results of Two Coupled Lines ...................................................... 57

6. An Improved Transmission Line Model.................................................................... 60

6.1 Microstrip structure and its equivalent circuits at high frequency................... 60

6.2 Calculation of the values of circuit components .............................................. 61

6.3 Experimental Verification................................................................................ 63

6.3.1 Test Structures...................................................................................... 63

6.3.2 S-parameter measurement and RLGC extraction ................................ 64

6.4 De-embedding Techniques............................................................................... 65

6.5 Experimental Results ....................................................................................... 67

6.5.1 Single Wire Model vs. Extracted RLGC Verification ......................... 67

6.5.2 Single Wires with Different Lengths ................................................... 69

6.5.3 Coplanar Waveguide (CPW) with Different Bottom Shielding .......... 72

6.5.4 Coupled Transmission Lines................................................................ 76

6.6 Summary .......................................................................................................... 76

7. Timing Derived Current for Signal Net Reliability Assessment ............................... 77

7.1 Introduction ...................................................................................................... 77

7.2 Background ...................................................................................................... 78

7.3 Methodology .................................................................................................... 79

vi

7.3.1 Two-step approach ............................................................................... 80

7.4 PI Model........................................................................................................... 81

7.5 Current Calculation .......................................................................................... 82

7.5.1 Average DC current calculation........................................................... 82

7.5.2 RMS current calculation ...................................................................... 83

7.6 Verification ...................................................................................................... 83

7.7 Implementation of Filtering Step ..................................................................... 84

7.7.1 Detailed Analysis Step ......................................................................... 84

7.8 Results .............................................................................................................. 85

7.8.1 Test Case .............................................................................................. 85

7.8.2 Sensitivity Analysis.............................................................................. 86

7.9 Future Work ..................................................................................................... 88

7.9.1 Enhancement of Existing Ability ......................................................... 88

7.9.2 Temperature-aware Electromigration Analysis ................................... 88

7.10 Summary .......................................................................................................... 88

8. Discussion and conclusion......................................................................................... 89

8.1 Application....................................................................................................... 89

8.1.1 Transmission Line Modeling Work ..................................................... 89

8.1.2 Signal Net Reliability Assessment ....................................................... 89

8.2 Future Work ..................................................................................................... 89

8.2.1 Future Modeling Work......................................................................... 89

8.2.2 CAD Tool Development ...................................................................... 90

References........................................................................................................................ 91

Appendix A...................................................................................................................... 97

Appendix B.................................................................................................................... 102

Appendix C.................................................................................................................... 140

vii

LIST OF TABLES

Table 2-1 Typical interconnections and maximum usable length.......................... 3

Table 2-2 Common line structures for wave propagation ...................................... 7

Table 7-1 Calculated Current vs. Simulated Current ........................................... 84

viii

LIST OF FIGURES

Figure 2-1 A typical microstrip line structure ......................................................... 8

Figure 2-2 Distributed circuit model for transmission line...................................... 9

Figure 2-3 Illustration of current distribution in a microstrip vs. wire dimension

and frequency. (Current density increases with darkness) ...................................... 15

Figure 2-4 Resistance of 1cm microstrip vs. frequency at different dimension .... 16

Figure 2-5 Electric and magnetic field within a microstrip structure .................... 17

Figure 3-1 Simplified microstrip line structure ..................................................... 20

Figure 3-2 Equivalent circuit of one line ignoring the insulator layer................... 20

Figure 3-3 Geometry of one line considering insulator layer ................................ 25

Figure 3-4 Equivalent circuit of one line considering insulator layer ................... 25

Figure 4-1 Equivalent circuit of two lines ignoring the insulator layer................. 32

Figure 4-2 Equivalent circuit of one line considering the insulator layer.............. 34

Figure 4-3 Field line surrounding two lines in even(top) and odd(bottom) mode. 36

Figure 5-1 Square pulse propagation including SiO2 layer................................... 39

Figure 5-2 Square pulse propagation ignoring SiO2 layer .................................... 40

Figure 5-3 Conductor attenuation facor under different conductor resistivies ...... 41

Figure 5-4 Substrate attenuation factor vs. frequency under different substrate

resistivies .............................................................................................................. 41

Figure 5-5 Total attenuation factor for Cu, Al, W and poly-Si microstrip ............ 44

Figure 5-6 Square pulse propagation vs. pulse width at 0, 1, 2, 3, 6, 9mm........... 46

Figure 5-7 Square pulse propagation vs. insulator layer thickness........................ 49

Figure 5-8 Square pulse propagation vs. different insulating dielectric constants 52

Figure 5-9 Square pulse propagation vs. different substrate resitivities................ 54

Figure 5-10 Square pulse propagation vs. different conductor resitivities .............. 57

Figure 5-11 Simulated waveforms in even mode at 1, 2, 4, 6 mms......................... 58

Figure 5-12 Simulated waveforms in odd mode at 1, 2, 4, 6 mms .......................... 59

Figure 6-1 The equivalent circuit of on-chip interconnect with consideration of

skin effect at high frequency.................................................................................... 60

Figure 6-2 Skin effect and its modeling in circuits................................................ 61

Figure 6-3 Micrograph of the fabricated test structures......................................... 63

ix

Figure 6-4 Layout and micrograph of dummy “open” and “short” structures ...... 66

Figure 6-5 RLGC values as a function of frequency (Measurement vs. Model)... 69

Figure 6-6 S11 and S21 magnitude and phase of 1mm and 3mm single wire ...... 71

Figure 6-7 Characteristic impedance Z0 of 1mm and 3mm single wire ............... 72

Figure 6-8 Cross section view of a coplanar waveguide ...................................... 73

Figure 6-9 Extracted RLGC of coplanar waveguides with different bottom

shielding .............................................................................................................. 75

Figure 6-10 Characteristic impedance Z0 of different bottom shielding coplanar

waveguides ............................................................................................................. 75

Figure 7-1 A cross section picture of electromigration effect ........................... 77

Figure 7-2 A simple inverter circuit where both unidirectional current and

bidirectional current exist ........................................................................................ 79

Figure 7-3 Channel connected components........................................................... 80

Figure 7-4 The PI Model and the relationship between the input slew and the

duration of current spike.......................................................................................... 81

Figure 7-5 Clock net and signal net current waveform.......................................... 82

Figure 7-6 Filtering Result of a Test Macro e ....................................................... 76

Figure 7-7 Sensitivity to (a) Wire Width and (b) Load Capacitance .................... 87

x

ACKNOWLEDGMENT

First and foremost, I want to thank my family for their endless love and support

in my life.

I want to thank my academic and research advisor, Prof. John F. McDonald, for

his assistance and guidance during my Ph.D. research journey and for providing me with

the opportunity to work in this very important field. The members of my doctoral

committee, Prof. Yannick Le Coz, Prof. Tong Zhang and Prof. Toh-Ming Lu also

deserve thanks for reviewing my work and providing insight and guidance.

This research work is not possible without the support of IBM Fellowship. I

would like to extend my sincere thanks to Dr. Raminderpal Singh, Dr. Youri Tretiakov,

and Dr. Wayne Woods in IBM Semiconductor Research and Development Center

(SRDC) in Burlington, Vermont for their continuous support and help in the research

work of transmission line modeling. They also helped me with fabrication and testing of

my test structures and provided me additional insight in the research. I also would like

to thank Dr. Thomas Bucelot in IBM T.J. Watson Research Center in Yorktown Heights,

New York for his support and help in the research work of signal net reliability

assessment.

I would like to thank my colleagues in the lab, Dr. Russ Kraft, Dr. Steven

Carlough, Dr. Samuel Steidl, Dr. Peter Curran, Dr. Matthew Ernest, Dr. Bryan Goda, Dr.

Thomas Krawczyk, Dr. Bin Wang, Dr. Kuan Zhou, Dr. Chao You, Dr. Jong-ru Guo, Dr.

Young Yim, Dr. Okan Erdogan, Paul Belemjian, Liyong Wang, Xin Ma, Micheal Chu,

John Mayega, Robert Heikaus, Jin-woo Kim, Peng Jin, Amir Zia, Philip Jacob, Steve

Nicholas and Jesse Kempf.

xi

ABSTRACT

This thesis presents a CAD-oriented modeling for on-chip microstrip and coplanar-

strip interconnect. Two improved model have been developed and several test structures

have been designed and fabricated in a SiGe BiCMOS technology. The modeling

technique uses a SPICE-friendly equivalent circuit approach which takes into account

the wire skin effect and silicon substrate effect. The fully scalable ladder network

contains only frequency-independent passive devices whose values are determined by

geometry and technology specifications. It can be easily incorporated into standard

industry simulation tools and migrated among various design environments. The

numerical simulation results have been provided as well as the measured S-parameters,

which are used to verify the model by extracting the RLGC parameters in the classical

transmission line approach up to 50GHz.

This thesis also presents a methodology to do signal net electromigration and

Joule heating analysis. A tool to filter signal nets to identify potential electromigration

and Joule heating violation has been developed. A new approach to do static detailed

analysis using linear solver has been explored. Future plans to enhance and complete

the modeling and reliability checking work have been proposed.

1

1. Introduction

1.1 Research topic

Constantly decreasing device size and increasing frequencies bring a lot of new

challenges that very large integrated circuits (VLSI) designers must face today,

especially in radio-frequency (RF) and analog and mixed signal (A&MS) areas. The

behavior of the on-chip interconnects emerged as the dominating factor in overall circuit

performance and the accurate and efficient modeling and simulation of on-chip

interconnects are practical necessities for modern design [Deutsch1].

A complete description of interconnect behavior can be derived and solved from

Maxwell’s equations describing electromagnetic behavior of physical structures. There

are commercial software available that use a full-wave 2-D or 3-D electromagnetic (EM)

field solver to be used to achieve that goal. They can be further categorized as finite

element method (FEM) [Jin1], finite-difference time-domain (FDTD) methods [Yee1]

and the method of moments (MoM) [Harrington1]. However, this “field” approach is

computationally expensive and hard to integrate into a regular design flow in general.

The effects of Maxwell equations can often be simplified by models such as lumped

passive circuits and discrete transmission line segments. This “circuit” approach is

much more desirable since it is more intuitive to design and convenient to simulate for

circuit designers, and most importantly, provides a much shorter turn-around time.

There has been a great interest in recent years to determine the frequency-dependant

characteristic of on-chip interconnect [Zheng1] and other passive components such as

inductors [Yue1]. There is also much interest in the development of closed-form

expression for the components values of the equivalent circuits in these models

[Weisshaar1, Cao1]. In this thesis work, we present a frequency-independent equivalent

circuit to model both the series impedance Z and shunt admittance Y for broad

bandwidth applications.

2

1.2 Thesis outline

Chapter 2 gives the historical review of the research in this field. Chapter 3

provides the basics of a transmission line model at low frequency. Chapter 4 gives our

first new model of single on-chip transmission line. Chapter 5 gives the model of two

coupled on-chip transmission lines based on the model in Chapter 4. Chapter 5 gives the

numerical simulation results of previous models. Chapter 6 extends the model to high

frequency by constructing a ladder network and shows the test structures as well as the

experimental measurement results. Chapter 7 is about the work of signal net reliability

check. Chapter 8 discusses the results and future work.

3

2. Historical Review

2.1 High Speed Interconnection

Interconnection is becoming a more and more important issue when people

design smaller and faster VLSI chips. The wiring cross sections are reducing and the

lines are packed closer together, while at the same time the propagated signals switch

with faster rise time. When the chip shrinks, the resistance, capacitance and inductance

per unit length increase so that they cannot be ignored anymore. Both attenuation and

delay need to be decreased by various ways to keep the chip work at higher and higher

clock frequency. As processor cycle times become shorter and chips become larger and

more complex, the performance of on-chip interconnections becomes more important.

On-chip interconnection delay and cross-talk are rapidly becoming important problems.

The average interconnection length L per gate on VLSI chips in known to increase with

the gate count G, as in the following empirical formula:

α AKGL = (2-1)

where K and α are empirical constants, and A is the logic cell layout area. This equation

can also be derived theoretically on the basis of the Rent’s rule concerning the pin versus

gate count relationship.

Table 2-1 Typical interconnections and maximum usable length

Interconnection

type

Line

Width

(μm)

Wiring

resistance

(Ω/cm)

Maximum interconnection

length

(cm)

On-chip 1–2 130–260 0.7–1.4

Thin-film

carriers

10–25 1.25–4 20–45

Ceramic 75–100 0.4–0.7 20–50

Printed circuit 60–100 0.06–0.08 40–70

4

Table 2-1 show several typical interconnections used in today’s industry and the

maximum interconnection lengths. [Deutsch2]

When the wavelengths of pulses are comparable with wire dimension, the wires

act like transmission lines and microwave theory must be applied to solve these kinds of

problems. In these cases, study of propagation of ultra-fast transients becomes important.

The challenges in VLSI techniques are bringing into focus the need of understanding

pulse distortions caused by loss mechanisms in microwave region such as skin effect,

dielectric dispersion and silicon slow-wave. On-chip interconnects have unique

characteristics, namely very high capacitive and inductive coupling and resistive losses,

and very non-uniform transmission-line structures. Most of their parameters are

frequency-dependent. These characteristics make major limitation of further

improvement of on-chip delays. For example, reducing wiring dimensions results in

appreciably resistive lines, even when the best conductive metals, such as copper, are

used. Also the semiconductor substrates used in MMIC’s and VLSI interconnects cause

dielectric losses to become a major contributor to signal attenuation. In addition, high

dielectric loses, such as slow-wave loss, can cause a significant change in the

propagation constant, and a severe pulse dispersion.

As one of the most widely used and most important microwave interconnections,

microstrip line gains a lot of attentions for past 40 years. The conventional lumped-

capacitance model assumes that signal propagation delays are much shorter than pulse

rise times, but this assumption is no longer valid for high-speed VLSI circuits. Hasegawa

and Seki [Hasegawa1] have shown that the traditional lumped-circuit RC representation

is no longer adequate when the switching speeds are faster than 100 ps. Because the

propagation time of an ideal Transverse Electromagnetic Mode (TEM) wave over 1-mm

distance is typically 8–10 ps on a semiconductor substrate (εr = 12–13), validity of such

an approach becomes very doubtful in high-speed VLSI system.

All of works above are analytic approaches. When encounter with multi-

conductor and multi-layer problems, these analytic approaches are no long practical

because of the unwieldy mathematical complexity. In these cases, a full-wave approach

has its advantages to give accurate characterization of dielectric losses in structures with

5

semiconductor substrates. Although full-wave approaches can give rigorous simulation

results, their electromagnetic boundary-value problems are usually too laborious and

time-consuming for direct application in CAD programs. They usually do not provide a

clear analysis review of the effect of geometry of microstrip and the material properties

of substrate. When encountering multi-conductor and multi-layer problems, these full-

wave approaches are computationally prohibitive because of the extreme complexity. In

these cases, analytic approaches have their advantages of simplicity and ease for CAD

implementation.

Spectral Domain Approach (SDA) has been discussed extensively in previous

works. The SDA is simpler to formulate for multi-layer, multi-conductor structures and

also in taking metal loss into consideration. It gives quick and accurate results, over a

wide range of conductivities and frequencies. A lossy multi-layer, multi-conductor

microstrip structure is analyzed by Gilb and Balanis [Gilb1] using SDA method. The

paper gives attenuation and propagation constants over a wide range of substrate

parameters and frequencies, covering all three propagation mode regions: low loss, slow

wave, and skin effect. Spectral domain approach (SDA) with complex permittivity for

the dielectric layers is also used to analyze microstrip structures.

There are several other approaches published in past decade, including mode-

matching approach [Fukuoka1, Tzuang1, Kowalski1], Fourier-transformed domain

analysis [Shih1], finite-element method [Auboug1], integral equation method

[Yamashita1], point matching method, finite difference method, boundary element

method, step current density approximation, as well as other unique ways of solving this

problem [Krowne1]. Among them, mode-matching approach is another popular method

that has also been applied to give accurate results for a limited range of substrate

parameters.

The purpose of this research work is to investigate the on-chip MIS microstrip

line attenuation and delay in very high-speed integrated circuits by analytic approaches,

using quasi-TEM assumptions. We extended a previous work [Goosen1] to develop our

new theoretical model for a MIS microstrip interconnection. We have included several

high-frequency physical effects: slow-wave substrate coupling, conductor resistance

6

loss, skin-effect degradation, distributed RC propagation. As extensions, we have

studied, in particular, the influences of an underlying insulator layer for a single line and

different excitation modes of two coupled lines. Our research results show that this

insulator layer is very important for signal attenuation and can not be simply ignored.

The simple approximate formulas to express the attenuation and dispersion property in

this paper are suitable for the purpose of desk calculations or the computer aided design

of microwave integrated circuits.

Several basic physics concepts are needed for modeling the microstrip

interconnections. Simplified microstrip line structure has to be identified to represent

major characters of actual on-chip interconnections. Transmission line theory is a

necessity of understanding the propagation of signals along this kind of lines because the

signal transmission is under microwave region at very high switch-speeds such as pico-

second or faster. Conformal transformation is a very powerful mathematical way to

calculate electrical parameter such as capacitance, effective dielectric constant, and

characteristic impedance. It transforms coordinates system to another geometry in which

the Laplace’s equation could be possibly solved while conserves certain values. Skin-

effect is obvious at high frequencies because the current is more packed at the region

near the surface. This causes additional frequency-dependent resistance and internal

inductance. Slow-wave loss is another very important effect on silicon substrate due to

the finite resistivity of substrate layer. Unlike electric field, the magnetic field can feel

free to penetrate the silicon substrate and this induces the separation of the electric field

and magnetic field and finally causes slow-wave mode propagation. In the rest of the

chapter, these physics effects are investigated more deeply and should be very helpful

for understanding the calculation shown later in this document.

2.2 Transmission Line

First, a “transmission line” is defined by Dworsky [Dworsky1] as any structure

that guides a propagating electromagnetic wave from one point to the other. But it is

usually restricted to the line whose electrical length is at least several percent of a

wavelength in high frequency range.

7

The transmission mode in a transmission line can be simply divided into two

categories, TEM mode and non-TEM mode. If the electric and magnetic fields, which

surround the transmission line, are normal both to each other and to the direction of

energy propagation, the signal is transmitting in Transverse Electromagnetic mode

(TEM). Two features can be used to distinguish a TEM mode: the longitudinal

components of electromagnetic fields are zero or neglected; the phase velocity is

independent of frequencies.

Table 2-2 Common line structures for wave propagation

Symbol Common Name TEM Type Transmission Line

Coaxial cable Yes Yes

Stripline Yes Yes

Balanced two-wire line Yes Yes

Microstrip No Yes

Slot-line No Yes

Rectangular wave guide No No

Not all the transmission lines support the TEM mode propagation. For a

transmission line that is surrounded by an inhomogeneous dielectric, the TEM mode can

be supported at only dc frequency. This is because the electric field lines cannot satisfy

all the necessary boundary conditions at the dielectric interfaces and conductor surfaces

without inclusion of a longitudinal component of the electric field at the dielectric

interface. Several commonly used transmission lines are listed in Table 2-2 [Dworsky1].

The propagation modes in these lines are also specified.

8

Among the transmission line above, the most important practical one for VLSI

on-chip interconnection is microstrip principally because it is easily made in the

photolithographic fabrication technology predominant today. It is defined as a

transmission line consisting of a strip conductor and a ground plane separated by a

dielectric medium. However, since the dielectric layer is usually semiconductor such as

silicon, an insulator layer is frequently inserted between the conductor and dielectric

substrate. This structure is often call MIS structure although the conductor is not

necessary to be a metal (e.g. poly-silicon). Figure 2-1 illustrates a typical microstrip line

structure.

insulator

semiconductor

ground

conductor

Figure 2-1 A typical microstrip structure

Circuits built with microstrip transmission lines have several important

advantages as:

The microstrip circuits can be fabricated at a substantially lower cost that of

wave-guide or coaxial circuit configurations. The complete conductor pattern can be

deposited and processed on a single dielectric substrate supported by a single metal

ground plane.

The microstrip circuits can be easily sampled or measured by external

equipment. Devices and components incorporated into hybrid integrated circuits are

accessible for probing and circuit measurements (with some limitations imposed by

external shielding requirement).

9

Beam-leaded active and passive devices can be bonded directly to metal stripes

on the dielectric substrate.

It is important to remember that the microstrip is intrinsically dispersive . It is

incapable of supporting a pure TEM wave. This non-TEM property of microstrip is

caused by the existence of three different dielectric constants in the line cross section.

The inhomogeneous dielectric experienced by the fringing field of the microstrip leads

to a discontinuity of the field at the interfaces and ultimately, the presence of

contributions from longitudinal components.

2.3 MIS Transmission Line Theory

2.3.1 Three Fundamental Modes

To date, a number of approximation techniques have been used for analyses of

microstrip interconnections. Hasegawa, et al., [Hasegawa2] have thoroughly

investigated the MIS (Metal-Insulator-Semiconductor) microstrip structures. They

introduced three modes, skin-effect mode, slow-wave mode, and dielectric quasi-TEM

mode propagating in microstrips according to the product of the frequency and substrate

resistivity. Goossen and Hammond collect many theoretical formulas from previous

works and use quasi-TEM assumption to analysis a typical MIS microstrip line

[Dworsky1].

2.3.2 Quasi-TEM method

R

G C

L

I I+dI

V V+dV

Figure 2-2 Distributed circuit model for transmission line

10

For a uniform transmission line, the differential equations for the line voltage V

and current I can be expressed in frequency domain[Dworsky1]:

ZIxV

−=∂∂ (2-1)

YIxI

−=∂∂ , (2-2)

where impedance LjRZ ω+= and admittance CjGY ω+= . R, L, C, and G are the

line resistance, inductance, capacitance, and conductance per unit length and are

frequency-dependent in general.

It is worth of mentioning that quasi-TEM behavior is assumed for typical

interconnection geometry for the transmission line cross section is a small fraction of the

wavelength in the frequency range of interest.

The general solution to Equations (2-1) and (2-2) can be expressed as

[Dworsky1]

xb

xa eVeVV γγ += −

xb

xa eIeII γγ += −

(2-3)

where the complex propagation factor is defined as

( )( )CjGLjRZY ωωγ ++== .

(2-4)

The characteristic impedance is in the form of

CjGLjR

YZZ

ωω

++

==0 .

(2-5)

Va, Vb, Ia, and Ib in equation (2-3) are constants that can be determined by

boundary conditions at the two ends of the transmission line. The complex propagation

11

factor γ can also be written into a form of real part and imagine part as βα j+ , where

( )γα Re= is the attenuation constant and ( )γβ Im= is the propagation constant.

2.3.3 Lossless line

In the case of lossless line, R = G = 0, the propagation delay per unit length is

LC=ωβ . (2-6)

And the propagation velocity is of course

LC

v 1= . (2-7)

Please note that for TEM mode propagation, the condition below

με=LC (2-8)

is held. μ is permeability and is equal to μ0μr, ε is dielectric constant and is equal to ε0εr.

The characteristic impedance is defined as

CLZ =0 . (2-9)

2.3.4 Low loss line

In the case when losses are small but not negligible, i.e.

ω<<LR and ω<<

CG ,

the attenuation and propagation constant per unit length according to [Tzuang1], can be

approximated by

2222

0

0

GZZR

CLG

CLR

+=+≅α , (2-10)

LCLC

RGL

GCLG

LR

CLRLC ω

ωωωωβ ≅−⎟⎟

⎞⎜⎜⎝

⎛+⎟

⎟⎠

⎞⎜⎜⎝

⎛+≅

44242. (2-11)

12

If the series resistive loss is small but finite, some pulse distortion will be

encountered because the different frequency components attenuate the same amount but

are shifted in phase differently. The rise time is degraded by dispersion. However, for

interconnections with maximum length lmax, if Rlmax << Z0, dispersion is usually

negligible, and the total signal line resistance results in a dc drop.

If the medium in which the conductors are located has finite resistance, then the

dielectric ε must be replaced by ( )δε tan1 j− , where δtan is the loss tangent of the

lossy material. The effective conductivity of the material is σ, where δωεσ tan= , and

the shunt conductance G is then given by δωεσ tanCCG == . The complex propagation

factor γ can then be expressed as

( )( )δωωγ tan112 jLjRLC −−−= . (2-12)

2.4 Effective Dielectric Constant

The concept of an effective dielectric constant is introduced to describe the

permittivity encountered by a wave on a transmission line structure that contains the

multi-dielectric interface, for example, an air-substrate interface. It describes the

interaction of the field with a dielectric, which are both the substrate and the open air.

Once the correct values of L and C of a guild line structure have been found, the

εeff can be solved by equation

LC = με (2-8)

This εeff has a value lying between εrε0 and ε0. Also, owing to the now-TEM

nature of this transmission line, it is dependent on the frequency of a signal.

Qualitatively, more field lines are in the substrate dielectric at high frequencies than at

low frequencies, leading to an effective permittivity that increases with frequency. Once

the formula of effective dielectric constant is derived, εeff can be used by substituting εr,

which is, located anywhere.

The value of εeff is stable at both very low and very high frequencies. But there is

a certain frequency region where εeff varies significantly. If a pulse contains frequency

13

components in this region, dramatic changes in the shape of a waveform will result from

the action of this function.

2.5 Conformal Transformation

Conformal transformation is a mathematical technique that allows particular

transmission line geometry to be transformed into a new geometry with a second

coordinate system without changing certain values. If the second coordinate system is

judiciously chosen, the new geometry may be more amenable to being solved by

Laplace’s equation than be the original geometry.

Consider a function ( )yx,φ , which satisfies the Laplace’s equation

02

2

2

22 =

∂∂

+∂∂

=∇yxφφφ .

We can define a new coordinate system, in which the problem is more easily

solvable. In general, the coordinates in new system has follow relationship with the old

one:

( )yxuu ,= (2-13)

( )yxvv ,=

( ) ( )vuWyx ,, ⇒φ .

If the transformation or mapping satisfies the Cauchy-Riemann conditions, which

is

yv

xu

∂∂

=∂∂ (2-14)

yu

xv

∂∂

−=∂∂

,

then the new function W(u, v) can be proved that it still satisfies the Laplace’s equation,

14

02

2

2

22 =

∂∂

+∂∂

=∇vW

uWW

There are some values that are not changed after the mapping. For example, let

us consider the energy stored in electric field in both coordinate systems. In the (x, y)

system, this is simple

( ) ( )∫∫−

+=−=

planeyx

yx dxdyCCV 22212

2

221

21 φφεφφ . (2-15)

With the conformal transformation, we can prove the following result is correct

[Fukoka1]:

( ) ( )∫∫∫∫−−

+=+

planevu

vu

planeyx

yx dudvdxdy 2222

22φφεφφε . (2-16)

Since the energy stored in electric field is directly related with capacitance of a

structure, this equation shows that the capacitance of this structure in the (u, v) system is

identical to the one in the original (x, y) system. This is the reason that the conformal

transformation is a very useful method to calculate capacitance and effective dielectric

constant.

2.6 Skin Effect

At high frequencies, current tends to crowd on the surface of the conductor. The

crowding decreases the effective flow area and increases its effective resistance due to

the simple resistance formula

SlR ρ

= . (2-17)

where ρ is resistivity, l is the length of a line, S is the flow area.

Also the conductor exhibits an internal inductance, Lint, due to magnetic flux

penetration, in addition to the external inductance. A reduction in phase velocity and an

increase in series impedance and attenuation are caused by the penetration of the electric

15

field into the conductor as it propagates along the surface. For an arbitrary solid

conductor, the skin effect results in a surface resistance, Rs, and reactance intLX ω= ,

which are both frequency-dependent, and, in general, not equal. However, at sufficiently

high frequency, the skin depth is much smaller than the conductor cross-sectional

dimensions, Then XRs ≅ . The additional series impedance due to skin effect will be

proportional to the square root of the frequency. The skin depth δ is defined as the

penetration distance at which the current density is attenuated by 1 neper (1/e = –8.7

decibels) and is equal to:

μπσμπ

ρδff

1== (2-18)

where f, ρ, and μ are the frequency, conductor resistivity, and permeability of the

medium, respectively. At low frequency or very small wire dimension, the skin depth δ

is much larger than the conductor cross section. The current approaches uniform

distribution, and the resistance is approximately equal to Rdc. On the other hand, at high

frequency and relatively large dimension, the δ becomes smaller than the cross section,

and both R and L are frequency-dependent.

4μm ×2μm

At100 GHz

1000 GHz

1 GHz1 GHz

100 GHz

10 GHz

8μm ×4μm

4μm ×2μm

2μm ×1μm

1μm ×0.5μm

0.5μm ×0.25μm

Figure 2-3 Illustration of current distribution in a microstrip vs. wire dimension and frequency. (Current density increases with darkness.)

16

1

10

100

1000

10000

1E+00 1E+02 1E+04 1E+06 1E+08 1E+10 1E+12

Frequency

Res

ista

nce

( Ω)

8 μm ×4 μm

4 μm ×2 μm

2 μm ×1 μm

1 μm ×0.5 μm

0.5 μm ×0.25 μm

Figure 2-4 Resistance of 1 cm microstrip vs. frequency at different dimensions

Wheeler [Wheeler1] developed a very simple rule of calculating the skin effect

resistance when δ < wire dimension. The rule states that the effective resistance in a

circuit is equal to the change of reactance caused by the penetration of magnetic flux into

the conductor. While the internal inductance is due to the flux penetration of δ /2. The

( )fR and ( )fL can be calculated as follows [Kowalski1]:

( )nLfR∂∂

=2δω (2-19)

( ) ( )nLLfLLfL extintext ∂∂

+=+=2δ , (2-20)

where n is the direction normal to the surface and Lext is the external circuit inductance,

which is associated with the magnetic field surrounding the conductors. Using equations

(2-12), (2-19), and (2-20), a more approximate formula for resistance can be obtained as:

( )δρ

twR

+=

2. (2-21)

A reasonable result can also be obtained by using the approximations in

[Dworsky1]. For high frequency, we have

17

( ) fRfR 0=

and ( )f

LLfL ext0+= . (2-22)

Please note that for highly resistive interconnections, conductor loss dominates.

Therefore, the dielectric loss can be ignored for most practical digital circuit-switching

speeds. In the case of wiring with small R, the dielectric loss should be included in the

analysis.

2.7 Silicon Slow-wave

Although the resistivity of GaAs wafer could be high enough to form a fairly low

loss dielectric for a microstrip line, the resistivity of the silicon wafer used in

semiconductor device manufacture varies with the needs of the semiconductor device

designer and usually do not have very high values. In this case, this silicon substrate can

not be considered to be a good insulator.

Because of the Si-SiO2 double layer dielectric, there exists a slow-wave loss in

the silicon substrate. The electric field is confined in the SiO2 layer while the magnetic

field feels free to penetrate the silicon substrate. This separation of electric and magnetic

field causes the slow-wave mode propagation. Figure 2-5 illustrates the distribution of

electric field and magnetic field.

MetalSiO2

Si

Electric Field

Magnetic Field

Figure 2-5 Electric and magnetic field within a microstrip structure

18

Although the compound dielectric is made up of materials with an εr = 12 (Si)

and εr = 4 (SiO2), the slow wave mode may propagate as slowly as if the dielectric had

an εr of 1600. [Hasegawa2] At certain circumstances, the silicon substrate slow-wave

loss could be very severe and dominant. The silicon dioxide layer grown on the surface

of the silicon can help to increase the resistance to ground seen by the upper metal and

thus reduce the attenuation due to the substrate slow-wave.

19

3. Basic Model and First Improved Model of Single Transmission Line

3.1 General Analysis

3.1.1 Computing Output Waveform

The voltage waveform V is a function of position x and time t. For a given input

waveform V(0,t),

( ) ( ) ( )[ ] tVFeFtxV xj ,0, 1 ×= +−− βα

(3-1)

where F and F-1 denote the Fourier and inverse Fourier transforms respectively,

α and β are the attenuation and propagation constants respectively.

3.1.2 Characteristic Impedance

The following formulas approximate Equations by rational function

approximation and give an accuracy of ±0.25% for 0 ≤ w/h ≤ 10 which is the range of

importance for most engineering applications.

⎟⎠⎞

⎜⎝⎛ +=

hw

whZ

48ln600 Ω, hw ≤

60

144.042.2

120

⎟⎠⎞

⎜⎝⎛ −+−+

=

wh

wh

hw

Z πΩ , hw ≥ .

(3-2)

We can solve this kind of problem by using the concept of effective

width[Dworsky1]:

⎟⎠⎞

⎜⎝⎛ ++=

thtwweff

2ln1π

, for π21

≥hw ;

20

⎟⎠⎞

⎜⎝⎛ ++=

twtwweffπ

π4ln1 , for

π21

≤hw .

(3-3)

3.2 Basic Model Ignoring the Insulator Layer

3.2.1 Geometry

The geometry of the simplified microstrip transmission line is shown in Figure 3-

1. The insulator layer is ignored here [Goosen1].

tw

h semiconductor

ground

conductor

Figure 3-1 Simplified microstrip line structure

3.2.2 Equivalent Circuit

V+dV

Rc

Rd Cd

L

I I+dI

V

Figure 3-2 Equivalent circuit of one line ignoring the insulator layer

21

Figure 3-2 gives the equivalent circuit for the model ignoring the insulator layer.

Rc and L are the resistance and the self-inductance of the transmission line respectively.

Rd and Cd are the resistance and self-capacitance of the silicon substrate respectively.

They are all per-unit-length.

3.2.3 Effective Dielectric Constant

The effective dielectric constant is frequency-dependent because more field lines

are in the substrate dielectric at high frequencies than at low frequencies. An empirical

formula that describes the frequency dependence of εeff was given below by Yamashita

[Yamashita1] et al..

230

0 41 −+

−+=

Feffr

effeff

εεεε (3-4)

where ⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ +++

−=

2

10 1log212114

hw

cfh

F rε .

Here, f is signal frequency and c is velocity of light in vacuum.

Recently the Kirschning and Jansen have found the most accurate formula

compared against the measured value [Kirschning1] as below.

( ) ( )( )fP

f effrreff +

−−=

10εε

εε . (3-5)

( ) ( )[ ] 5763.14321 1844.010 fhPPPPfP += (3-6)

with ( )

hw

ehw

fhP

7513.8

201 065683.0157.01525.06315.027488.0

−−⎥

⎤⎢⎣

⎡+

++= ,

( )reP ε03442.02 133622.0 −−= ,

⎥⎥⎦

⎢⎢⎣

⎡−=

⎟⎠⎞

⎜⎝⎛−−

97.4

87.324

3 10363.0fh

hw

eeP ,

22

and ⎥⎥

⎢⎢

⎡−+=

⎟⎠⎞

⎜⎝⎛−

8

916.154 1751.21

r

ePε

,

where fh represents the normalized frequency in unit of (GHz cm). The accuracy of this

expression is better that 0.6% in the range 0.1 ≤ w/h ≤ 100, 1 ≤ εr ≤ 20 and 0 ≤ h/λ0 ≤

0.13.

3.2.4 Analytical Solution

From Section 2.3.2

( )( )γ ω ω= + +1 R i C R i Ld c

(2-4)

and βαγ i+= .

(3-5)

By expanding (3-4) and (3-5), we have

( )( ) ( )1 2R i C R i L id c+ + = +ω ω α β

and ( ) )2(2 2222

222222 αββαωωωω i

RRCL

RLRCiCL

RR

d

c

dc

d

c +−=⎟⎟⎠

⎞⎜⎜⎝

⎛+++⎟⎟

⎞⎜⎜⎝

⎛− .

(3-6)

Solving this equation, we have

α =− +f f1 2

2

2

21 ff +=β

(3-7)

where

23

d

c

RRLCf −= 2

1 ω

⎟⎟⎠

⎞⎜⎜⎝

⎛+⎟⎟

⎞⎜⎜⎝

⎛+=

CRLLC

LCRLCf

d

c2

22

22 ωω

(3-8)

By analyzing the microwave circuit shown in Figure 3-2 in low loss condition

[Goosen1], we have the relationship that

LCRc

c 2=α ,

CL

Rdd 2

1=α ,

cf

LC effεπωβ

20 == ,

(3-9)

where c is the speed of light in vacuum. Substitute (3-9) into (3-8), we finally get

f c d1 02 4= −β α α

( )( )220

2202 44 dcf αβαβ ++= .

(3-10)

At low loss conditions, i.e. β0 >> αc, αd, the equations (3-7) are simplified as

α α α= +c d

( ) 20

2 βααβ +−= dc .

(3-11)

Although the model is derived under low loss condition, It actually fits into all

the frequencies because at sufficiently high frequencies (~10 GHz), even the most lossy

line is in the low-loss regime[Goosen1].

24

3.2.5 Attenuation Constant

3.2.5.1 Conductor Loss

With the expression of L given by Wheeler [Wheeler3], we can derive that:

⎥⎥⎥⎥

⎢⎢⎢⎢

⎟⎠⎞

⎜⎝⎛ +

+′

+⎥⎥⎦

⎢⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ ′

−=w

wt

twh

wh

hw

hZRs

c π

π

πα

4ln1

41

2

2

0

, π21

<hw ;

⎥⎥⎥⎥

⎢⎢⎢⎢

⎟⎠⎞

⎜⎝⎛ −

+′

+⎥⎥⎦

⎢⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ ′

−=w

ht

thh

wh

hw

hZRs

c ππα

2ln1

41

2

2

0

, 221

<<hw

π;

( )( )

⎥⎥⎥⎥

⎢⎢⎢⎢

⎟⎠⎞

⎜⎝⎛ −

+′

+⎥⎦

⎤⎢⎣

⎡+′

′+′

⎭⎬⎫

⎩⎨⎧

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ +

′+′

=w

ht

thh

wh

hwhw

hw

hwe

hw

hZRsc π

π

ππ

α

2ln1

94.0294.0

22ln2

20 ,

hw

<2

(3-12)

where R fs c= π μρ is the surface skin resistance and μ is the permeability of the

conductor.

3.2.5.2 Substrate Loss

An expression of dielectric slow-wave loss αd due to the non-zero conductivity in

the substrate has been derived by Welch and Pratt [Welch1] as

( )( ) effr

effsd εε

εσηα

1210

−=

(3-13)

25

3.3 Extended Model Considering the Insulator Layer

3.3.1 Geometry

tti

w

h

insulator

semiconductor

ground

conductor

Figure 3-3 Geometry of one line considering insulator layer

Liyong Wang [Wang1] developed a model considering the effect of the insulator

layer that previous research chose to ignore. Figure 3-3 gives the geometry of the

transmission line he considered.

3.3.2 Equivalent Circuit

Here is the equivalent circuit of the transmission line as to the geometry above.

Rc

Rd Cd

L Ci

Figure 3-4 Equivalent circuit of one line considering insulator layer

26

3.3.3 Effective Dielectric Constant

Since we inserted an insulator layer between the conductor and the substrate, the

structure of the microstrip system is changed. The formula of effective dielectric

constant also changes. Jiri Svacina [Svacina1] gave a pretty accurate formula of effective

dielectric constant for double layer dielectrics by using conformal mapping method. The

formulas are:

( ) ( )12

221

2110qq

qqqqoxS

oxSeff εεεεε

++

+−−= ,

(3-14)

where

⎪⎪⎭

⎪⎪⎬

⎪⎪⎩

⎪⎪⎨

⎥⎥⎥⎥

⎢⎢⎢⎢

⎟⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎠

⎞⎜⎜⎝

−+=1

1

1

1

1

11 2

cos

2

2sin

ln4

12 h

h

hhhh

hw

wh

hhq eff

eff

ππ

π

ππ ,

1

112

1ln

211

hwh

w

qqeff

eff⎟⎟⎠

⎞⎜⎜⎝

⎛−

−−=π

for wide line w ≥ h.

And

⎥⎥⎥⎥

⎢⎢⎢⎢

⎟⎟⎟⎟⎟

⎜⎜⎜⎜⎜

+−

+−+

+−

+

=

hw

hh

hh

hw

hh

wh

hw

hh

hh

q

41

1

8arccos

21

418ln2

41

1ln

1

1

1

1

1

11

1

1π ,

11

2 8ln

9.021 q

whq −+=

π,

27

for narrow line w ≤ h.

The effective line width for dielectric constant weff is

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ ++= 92.0

208.17ln2

hwhwweff π

.

(3-15)

The accuracy of these formulas is within 2% as acclaimed.

3.3.4 Analytical Solution

By investigating this equivalent circuit, the relations between voltage and current

are changed to

( )iLiRdxdv

c ω+−=

v

CiR

Cidxdi

dd

i ωω ++

−=

111

1 .

(3-16)

From the equations above, we have

( )v

CiR

Ci

LiRdx

vd

dd

i

c

ωω

ω

++

+=

1112

2

(3-17)

and

( )i

CiR

Ci

LiRdx

id

dd

i

c

ωω

ω

++

+=

1112

2

.

28

Let

( )

dd

i

c

CiR

Ci

LiR

ωω

ωγ

++

+=

111

2

(3-18)

then the equations (3-17) are simplified as

vdx

vd 22

2

γ=

idx

id 22

2

γ= .

(3-19)

Similar as the derivation in Section 3.2, set βαγ i+= , then to find out the α and

β. We let

( ) ( )2

111

βα

ωω

ωi

CiR

Ci

LiR

dd

i

c +=

++

+.

(3-20)

Here, we introducing a new parameter ki, which is the ratio of the insulator

capacitance and the substrate capacitance ( dii CCk = ).

LCR dc

c 2=α

ddd C

LR21

dLCωβ =0

(3-21)

29

We get the attenuation and propagation factor again as

221 ff +−

=α ,

221 ff +

(3-22)

But the f1 and f2 are changed to

( ) ( )

20

22

220

20

2

1 4)1(

44

βα

αβααβ

di

didci

k

kkf

++

++−= ,

( )( )

20

22

220

220

2

2 4)1(

44

βα

αβαβ

di

dci

k

kf

++

++= .

(3-23)

3.3.5 Computing ki

The capacitance of Ci, Cm and Cd can be calculated by QuickCap.[RLC1]

3.4 Numerical Computing

Please see Chapter 4 for waveforms and Appendix for Mathematica® codes.

30

4. Modeling of Two Coupled Lines

4.1 General Analysis

For two coupled transmission lines, Line 1 and Line 2, we may write down the

MTL (multi-conductor transmission lines) equations as:

⎥⎦

⎤⎢⎣

⎡⎥⎦

⎤⎢⎣

⎡−=⎥

⎤⎢⎣

⎥⎦

⎤⎢⎣

⎡⎥⎦

⎤⎢⎣

⎡−=⎥

⎤⎢⎣

2

1

2221

1211

2

1

2

1

2221

1211

2

1

VV

YYYY

II

dzd

II

ZZZZ

VV

dzd

(4-1)

where the Z11 and Z12 are the self-impedance of Line 1 and the mutual impedance

between Line 1 and Line 2, similar for Z21, Z22, Y11, Y12, Y21 and Y22.

Let

⎥⎦

⎤⎢⎣

⎡⎥⎦

⎤⎢⎣

⎡=⎥

⎤⎢⎣

2221

1211

2221

1211

2221

1211

YYYY

ZZZZ

γγγγ

,

(4-2)

We have

⎥⎦

⎤⎢⎣

⎡⎥⎦

⎤⎢⎣

⎡−=⎥

⎤⎢⎣

2

1

2221

1211

2

12

2

VV

VV

dzd

γγγγ

.

(4-3)

For two identical lines, we have Z11 = Z22, Z12 = Z21, Y11 = Y22, and Y12 = Y21.

Let us denote them by

Z = Z11 = Z22, Z’ = Z12 = Z21, Y = Y11 = Y22, and Y’ = Y12 = Y21.

(4-4)

Then

31

γ = γ 11 = γ22 = ZY+Z’Y’, γ ‘ = γ 12 = γ21 = ZY’+Z’Y.

(4-5)

If V = V1 = -V2 which is called Odd Mode, (4-3) can be simplified as

VVdzd )'(2

2

γγ −=

(4-6)

Compared with one line case, we have

γ2 = (γ - γ’) = (Z – Z’) (Y – Y’)

(4-7a)

For Even Mode, which means V = V1 = V2, we have

γ2 = (γ + γ’) = (Z + Z’) (Y + Y’)

(4-7b)

The above results agree with Clayton Paul’s results [Paul1] solved by using the

transformation matrix.

32

4.2 Model Ignoring Insulator Layer

4.2.1 Equivalent Circuit

Figure 4-1 Equivalent Circuit of Two Lines Ignoring Insulator Layer

If we do not consider the insulation layer, we have

Z = Rc +iϖL,

Y = 1/Rd + iϖCd,

Z’ = 0,

Y’ = - iϖCm

(4-8)

Where Cm is the mutual capacitance between two lines.

The state equation for the equivalent circuit is

( ) vCiR

LiRdx

vdd

dc )1(2

2

ωω ++=

33

(4-9)

4.2.2 Even Mode

Now

γ2 = (Z + Z’) (Y + Y’)

= (Rc + iϖL) (1/Rd + iϖCd – iϖCm)

= (Rc + iϖL) [1/Rd + iϖ(Cd - Cm)]

(4-10a)

We find that we only need to change Cd to Cd – Cm, say Cd’ = Cd – Cm, we

may still use the formulae we derived in Chapter 2, (2-?) as analytical solutions. Let us

introduce a new parameter km, which equals to the ratio of Cm over Cd, so that

Cd’ = Cd(1 – km)

(4-11a)

and

f1 = (1 - km) β02 – 4 αc αd,

f2 = (β02 + 4 αc

2) [ (1 - km) β02 + 4 αd

2)

(4-12a)

while the formulae of α and β do not change.

4.2.3 Odd Mode

Since

γ2 = (Z + Z’) (Y + Y’)

= (Rc + iϖL) (1/Rd + iϖCd + iϖCm)

= (Rc + iϖL) [1/Rd + iϖ(Cd + Cm)]

(4-10b)

34

Cd’ = Cd(1 + km)

(4-11b)

We again write down the expression of f1 and f2:

f1 = (1 + km) β02 – 4 αc αd,

f2 = (β02 + 4 αc

2) [ (1 + km) β02 + 4 αd

2)

(4-12b)

4.3 Model Considering Insulator Layer

4.3.1 Equivalent Circuit

Figure 4-2 Equivalent Circuit of Two Lines Considering Insulator Layer

The state equation for the equivalent circuit is

35

( ) vCi

CiR

Ci

LiRdx

vdm

dd

i

c

⎪⎪⎪

⎪⎪⎪

⎪⎪⎪

⎪⎪⎪

+

++

+= ϖ

ωω

ω

111

12

2

(4-13)

for even mode; change Cm to – Cm, then get odd mode.

4.3.2 Even Mode

( ) ( )m

di

didci

k

kkf 2

20

22

220

20

2

1 4)1(

44β

βα

αβααβ−

++

++−=

( ) [ ]⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡++−+−+

⎥⎦

⎤⎢⎣

⎡++

+=

2

20

220

422

20

22

220

2 )1()1(4

)(.44

)1(

4iimi

dmiid

di

c kkkkkkk

k

fβα

βα

βα

αβ

(4-14a)

where

β2m = ω2LCm

4.3.3 Odd Mode

( ) ( )m

di

didci

k

kkf 2

20

22

220

20

2

1 4)1(

44β

βα

αβααβ+

++

++−=

( ) [ ]⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡++++++

⎥⎦

⎤⎢⎣

⎡++

+=

2

20

220

422

20

22

220

2 )1()1(4

)(.44

)1(

4iimi

dmiid

di

c kkkkkkk

k

fβα

βα

βα

αβ

(4-14b)

36

where

β2m = ω2LCm

4.4 Calculating Parameters

4.4.1 Effective Dielectric Constant

We used both (3-4) and (3-14) for frequency-dependent effective dielectric

constant.

4.4.2 Capacitance

When two ideal conductors are present over the lossy Si substrate the field

structure of the single conductor case is disturbed. More importantly the field structure

depends on symmetry or asymmetry of the voltages applied to the conductors. Figure 4-

3 depicts the fields for an even and odd excitation mode. Hence, we conclude that the

degree of decoupling from the substrate will depend on the voltages applied, and further

will be superior for the odd mode, also called the differential mode of excitation since

more of the field lines are attracted away from the substrate.

Figure 4-3 Field line surrounding two lines in even(top) and odd(bottom) mode

37

In this simplified analysis the circuit components below the surface of the

substrate are assumed to be approximately the same as in the single line case. Clearly an

error is committed since the field lines below the substrate are affected by the presence

of the other conductor. However, this error is on the conservative side. Another

approximation is taken by treating the silicon substrate surface as a quasi ground in

computing the other capacitances. This becomes the node between the decoupling

capacitance and the substrate model.

The other capacitances are computed using QuickCAP [RLC1], The results

shows that the decoupling capacitance Cd increases with dielectric constant of insulator

layer, the distance between two coupled lines, the ration of the width over the height of

the transmission lines. [Diao1]

38

5. Simulation Results of the First Improved Model

5.1 Results of A Single Line

We have analyzed several physical factors that affect the pulse propagation

along a microstrip line. [Wang1] The attenuation of pulses is smaller at wider pulse

width, thicker insulator layer, lower insulator relative dielectric constant, higher

substrate resistivity, and lower conductor resistivity. We also observed an interesting

phenomenon of pulse propagation at cryogenic temperature. The attenuation is

unexpectedly low although the substrate resistivity is very small. These results can be

used to choose proper microstrip structure parameters at high frequency interconnection

design.

By finding pulse propagation along microstrip in time domain, several physics

effects are investigated with the basic and extended model mentioned before such as

frequency dependency of attenuation and propagation constants, signal dispersion and

attenuation, conductor resistance, skin-effect degradation, distributed RC propagation.

We have also examined, in particular, the influence of an underlying insulator layer, as

the basic model has not included such a layer. Many new results are discovered. We

have found that the attenuation factor is strongly dependent on the dielectric thickness

and dielectric constant of the insulator layer. Another interesting phenomena is the

microstrip behavior under cryogenic temperature. We observe a small amount of

attenuation under very low substrate resistivity, which is unexpected. We also try to

separate the attenuation factors due to the conductor loss and due to substrate slow-

wave. We found that at some high pulse frequencies, substrate loss becomes a dominant

factor of pulse attenuation. At this frequency region, insulator layer plays a very

important role for decoupling the interaction between conductor and substrate, and thus

relieves the slow-wave loss due to the finite substrate resistivity.

5.1.1 Pulse Propagation along Microstrip Line

Figure 5-1 and 5-2 show the square pulse propagation along a microstrip line.

The dimensions of the microstrip structure are shown in the legends of these figures.

Silicon substrate with resistivity of 13 μΩcm is chosen because it is compatible for most

39

of the Si techniques. The relative dielectric constant of Si is 11.8. The insulator layer is

made of SiO2 since it has been extensively used in Si IC industry. The relative dielectric

constant of SiO2 is 4. Copper is selected as the conductor metal with resistivity of 1.72

μΩcm which is used in today’s industry as an upgrade from Aluminum for its low

resistivity and good electron migration properties. he pulse width is 50 ps with 12 ps  

rise and fall time. This pulse is suitable for about 8 GHz clock cycle.

These simulations tell us that there may exists a relatively high attenuation with

pulse propagation if the pulse frequency is high enough. In the microstrip structure

shown in Figure 5-1, the pulse remains only lower than half after 9mm propagation.

Also severe pulse dispersion is observed. The edge of pulses is degraded and pulses have

long tails. After long distance transmission, the pulses seem to have a tendency of being

split into two pieces. This is probably because of the existence of two major values of

effective dielectric constant and characteristic impedance.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

SiO2 Thickness = 1μmρsubstrate = 13Ω cm

Pulse Width = 50psR/F time = 12ps

Figure 5-1 Square pulse propagation along a microstrip at length intervals 0, 1,

2, 3, 6, and 9mm, including 1μm SiO2 layer.

Compare with Figure 5-1 and 5-2, the pulse attenuation is 40% reduced with only

1 μm SiO2 layer. This confirms that ignoring the effects of insulator thickness, which is

40

expressed in the basic modeling (Chapter 2), is not proper. The function of this insulator

layer is not only cutting off the dc current penetration from conductor to substrate, but

also decoupling the interaction between conductor and substrate at high frequencies and

such reducing the slow-wave loss. However, the dispersion is not improved with the

insulator layer.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

ρsubstrate = 13Ω cmPulse Width = 50ps

R/F time = 12psNo SiO2 Layer

Figure 5-2 Square pulse propagation along a microstrip at length intervals 0, 1,

2, 3, 6, and 9mm, ignoring the SiO2 layer.

5.1.2 Conductor and Substrate Attenuation Constants αc and αd

Figure 5-3 and 5-4 shows the frequency-dependent of conductor and substrate

attenuation factor. The conductor attenuation factor αc is strongly frequency-dependent.

However, the substrate attenuation factor is more stable throughout frequencies. At low

frequencies, substrate attenuation is the dominant attenuation factor. E.g. for copper

microstrip, the attenuation factor at 1 GHz is only 2.32, while the substrate attenuation

factor is all beyond the 20 at the same frequency. However, at very high frequency, the

skin-effect becomes the major loss comparing with substrate slow-wave loss. The

attenuation factor due to it could reach as high as a thousand.

41

0

100

200

300

400

500

600

700

800

900

1000

1 10 100 1000 10000

Frequency (GHz)

Con

duct

or A

ttenu

atio

n Fa

ctor

Cross Section: 4×1μmSiO2 thickness = 1μm

Substrate thickness = 450μm

ρ conductor = 1.72 μΩ cm

ρ conductor = 10 μΩ cm

ρ conductor = 500 μΩ cm

Figure 5-3 Conductor attenuation factors vs. frequency under different conductor resistivities

0

50

100

150

200

250

300

350

400

450

1 10 100 1000 10000

Frequency (GHz)

Subs

trat

e A

ttenu

atio

n Fa

ctor

Cross Section: 4×1μmSiO2 thickness = 1μm

Substrate thickness = 450μm

R substrate = 13Ω c

R substrate = 50Ω c

R substrate = 100Ω

Figure 5-4 Substrate attenuation factor vs. frequency under different substrate

resistivities

42

5.1.3 Total Attenuation Constant  

0

100

200

300

400

500

600

700

800

900

1 10 100 1000 10000

Frequency (GHz)

Tota

l Atte

nuat

ion

Fact

or α

Cuρ conductor = 1.72 μΩ cmSiO2 thickness = 1μm

Si Susbstrate thickness = 450mma

b

c

d

Figure 5-5(a)

0

200

400

600

800

1000

1 10 100 1000 10000

Frequency (GHz)

Tota

l Atte

nuat

ion

Fact

or α

Alρ conductor = 2.7 μΩ cmSiO2 thickness = 1μm

Si Susbstrate thickness = 450mm

a

bc

d

43

Figure 5-5 (b)

0

200

400

600

800

1000

1200

1400

1600

1800

1 10 100 1000 10000

Frequency (GHz)

Tota

l Atte

nuat

ion

Fact

or α

Wρ conductor = 10 μΩ cmSiO2 thickness = 1μm

Si Susbstrate thickness = 450mm

a

b

c

d

Figure 5-5 (c)

0

2000

4000

6000

8000

10000

12000

1 10 100 1000 10000

Frequency (GHz)

Tota

l Atte

nuat

ion

Fact

or α

Poly-Siρ conductor = 100 μΩ cmSiO2 thickness = 1μm

Si Susbstrate thickness = 450μm a

b

c

d

Figure 5-5 (d)

44

Figure 5-5 Total attenuation factor versus fr  equency for Cu, Al, W, and poly-Si microstrips. (a) – Line cross section = 1 x 0.6 μm, Substrate resistivity = 13 Ω cm (b) – Line cross section = 1 x 0.6 μm, Substrate resistivity = 100 Ω cm (c) – Line cross section = 10 x 2 μm, Substrate resistivity = 13 Ω cm (d) – Line cross section = 10 x 2 μm, Substrate resistivity = 100 Ω cm

Figure 5-5 shows a set of curves of total attenuation factor α. Several popularly

used conductor materials, Cu, Al, W, and poly-Si are investigated with variant silicon

substrate resistivities.

As expected, the total loss monotonically increases with the increasing conductor

resistivity and the decreasing substrate resistivity. At relatively low line resistivity and

low substrate resistivity, the conductor loss and substrate slow-wave loss are

comparable, as shown in (i – c) and (ii – c). We can see that the conductor loss becomes

dominant at several hundred GHz. However, in other circumstances, the conductor loss

is the major loss factor and the curve is very similar to the conductor loss factor αc as

shown before (Figure 5-3). At very high line resistivity, such as poly-Si, the conductor

loss become so high that changing the substrate resistivity does not help much (iv – a, b).

5.1.4 Factors that Affect Pulse Propagation

5.1.4.1 Pulse Width

The propagation of pulses with different pulse width is simulated in Figure 5-6.

The clock pulses frequency in picture (a), (b), (c), and (d) corresponds with 32 GHz, 16

GHz, 1.6 GHz, and 160 MHz. From the picture we can see that higher frequency pulses

have higher amount of attenuation, as we expected, because they contain more high

frequency component and attenuation factors increase at higher frequency. In the picture

(a), which has 160 MHz pulses, we can hardly see any attenuation and dispersion in

signals. This is why today’s industries do not pay much attention about the clock pulse

attenuation. However, at high frequency, which may be not too far in the future, the

attenuation and dispersion begin to show and finally become very severe, Figure 5-6 (a).

45

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 2 4 6 8 10

Time (ns)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmAl, ρconductor = 2.7μΩ cmSiO2 Thickness = 4μmρsubstrate = 13Ω cmPulse Width = 5nsR/F time = 12ps

Figure 5-6 (a)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 200 400 600 800 1000

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmAl, ρconductor = 2.7μΩ cmSiO2 Thickness = 4μmρsubstrate = 13Ω cm

Pulse Width = 500psR/F time = 12ps

Figure 5-6(b)

46

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmAl, ρconductor = 2.7μΩ cmSiO2 Thickness = 4μmρsubstrate = 13Ω cm

Pulse Width = 50psR/F time = 12ps

Figure 5-6(c)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 20 40 60 80 100

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmAl, ρconductor = 2.7μΩ cmSiO2 Thickness = 4μmρsubstrate = 13Ω cm

Pulse Width = 25psR/F time = 6ps

Figure 5-6(d)

Figure 5-6 Square pulse propagation along a microstrip at length intervals 0, 1, 2, 3, 6, and 9mm vs. different pulse width: (a) 5ns, (b) 500ps, (c) 50ps, and (d) 25ps

47

5.1.4.2 Insulator Layer Thickness

The main effect of insulator layer is decoupling interaction between conductor

and substrate in a microstrip and then reducing the slow-wave losses in resistive

substrate. Fig 5-7 shows a set of signals with different SiO2 layer thickness. We choose

copper as the conductor and large wire dimensions (4×1μm) to minimize the influence

from conductor loss.

Figure 5-7 (a) is the case in which the SiO2 layer is simply ignored, which is

modeled by Wheeler [Wheeler3]. Significant losses and dispersion is observed for 50 ps

pulse width. With an only 1 μm SiO2 layer thickness, (b) shows waveform attenuation is

reduced by approximately 40%. At 4 μm oxide layer thickness, (c), attenuation within

the 3 mm distance is only 10%. With 13 μm oxide layer thickness, the pulses can run

about 6 mm with <10% losses. However, the dispersion still can not be eliminated.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

ρsubstrate = 13Ω cmPulse Width = 50ps

R/F time = 12psNo SiO2 Layer

Figure 5-7(a)

48

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

SiO2 Thickness = 1μmρsubstrate = 13Ω cm

Pulse Width = 50psR/F time = 12ps

Figure 5-7(b)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

ρsubstrate = 13Ω cmPulse Width = 50ps

R/F time = 12psSiO2 Thickness = 4μm

Figure 5-7 (c)

49

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

ρsubstrate = 13Ω cmPulse Width = 50ps

R/F time = 12psSiO2 Thickness = 13μm

Figure 5-7 (d)

Figure 5-7 Square pulse propagation along a microstrip at length intervals 0, 1, 2, 3, 6, and 9mm vs. different insulator layer thickness: (a) 0μm, (b) 1μm, (c) 4μm, and (d) 13μm.

5.1.4.3 Insulator Dielectric Constant

Choosing insulator materials with dielectric constant can also help to reduce the

substrate losses because of the same reason described in last section, i.e. reduce the

interaction between conductor and substrate. Now a day, lots of materials with low

dielectric constant is of researcher’s interest. Again, we choose same conductor material

and dimensions for minimizing the conductor loss.

50

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

SiO2 Thickness = 1μmρsubstrate = 13Ω cm

Pulse Width = 50psR/F time = 12ps

Figure 5-8 (a)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cmInsulator Thickness = 1μmInsulator Dielectrics = 2.4

ρsubstrate = 13Ω cmPulse Width = 50ps

R/F time = 12ps

Figure 5-8 (b)

51

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cmInsulator Thickness = 1μmInsulator Dielectrics = 1.6

ρsubstrate = 13Ω cmPulse Width = 50ps

R/F time = 12ps

Figure 5-8 (c)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cmInsulator Thickness = 1μm

Insulator Dielectrics = 1ρsubstrate = 13Ω cm

Pulse Width = 50psR/F time = 12ps

Figure 5-8 (d)

52

Figure 5-8 Square pulse propagation along a microstrip at length intervals 0, 1, 2, 3, 6, and 9mm vs. different insulating dielectric constants: (a) 4, (b) 2.4, (c) 1.6 and (d) 1.

Figure 5-8 above shows the effects of insulator dielectric constant. Picture (a) is

the case in which normal SiO2 is used. However, Picture (b) shows pulse propagation

results when the SiO2 layer is replaced with low-dielectric constant parylene-F, whose

relative dielectric constant is 2.4. Attenuation is reduces 20% compared with using SiO2.

Picture (c) gives the results with aerogel or parylen-F co-polymer network dielectric. In

this case, an additional 15% attenuation reduction is achieved. Picture (d) shows the best

case in which the insulator layer is nothing but air, whose relative dielectric constant is

1. With changing dielectric constant in insulator layer, one can not have better results

than (d).

5.1.4.4 Substrate Resistivity

At relatively high frequency, substrate slow-wave loss is dominant loss factor.

Increasing substrate resistivity is the best way to reduce the resistive loss in this layer.

Figure 5-9 demonstrates the control of substrate losses. The conductor is chosen by the

same reasons described in section 5.4.4.2.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

SiO2 Thickness = 1μmρsubstrate = 13Ω cm

Pulse Width = 50psR/F time = 12ps

Figure 5-9(a)

53

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

ρsubstrate = 50Ω cmPulse Width = 50ps

R/F time = 12psSiO2 Thickness = 1μm

Figure 5-9 (b)

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

ρsubstrate = 100Ω cmPulse Width = 50ps

R/F time = 12psSiO2 Thickness = 1μm

Figure 5-9 (c)

54

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 4×1μmCu, ρconductor = 1.72μΩ cm

ρsubstrate = InfinityPulse Width = 50ps

R/F time = 12psSiO2 Thickness = 1μm

Figure 5-9 (d)

Figure 5-9 Square pulse propagation along a microstrip at length intervals 0, 1, 2, 3, 6, and 9mm vs. different substrate resistivities: (a) 13Ω cm, (b) 50Ω cm, (c) 100Ω cm, and (d) infinity.

By increasing substrate resistivity from 13 Ω cm to 50 Ω cm, the loss is lessened

50%. Further 40% reduction can be attained by increasing the substrate resistivity to 100

Ω cm. However, a silicon wafer with 100 Ω cm resistivity is very hard to get from

material suppliers. Other substrate materials, such as GaAs, SiC, may be used to achieve

this reduction. If the substrate resistivity is an infinity, the signal will propagate almost

without any attenuation. This case is suitable for SOI technology, in which an insulator

is acted as a substrate. However, the dispersion seems getting worse at higher substrate

resistivities.

55

5.1.4.5 Conductor Materials

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 0.8×0.6μmρconductor = 0 μΩ cmρsubstrate = 13Ω cm

Pulse Width = 50psR/F time = 12ps

SiO2 Thickness = 1μm

Figure 5-10 (a)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 0.8×0.6μmAl, ρconductor = 2.7 μΩ cm

ρsubstrate = 13Ω cmPulse Width = 50ps

R/F time = 12psSiO2 Thickness = 1μm

Figure 5-10 (b)

56

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 0.8×0.6μmW, ρconductor = 10 μΩ cm

ρsubstrate = 13Ω cmPulse Width = 50ps

R/F time = 12psSiO2 Thickness = 1μm

Figure 5-10 (c)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 50 100 150 200

Time (ps)

Puls

e Vo

ltage

(V)

Cross Section: 0.8×0.6μmpoly-Si, ρconductor = 100 μΩ cm

ρsubstrate = 13Ω cmPulse Width = 50ps

R/F time = 12psSiO2 Thickness = 1μm

Figure 5-10 (d)

57

Figure 5-10 Square pulse propagation along a microstrip at length intervals 0, 1, 2, 3, 6, and 9mm vs. different conductor materials with resistivities of: (a) 0 μΩ cm, (b) 2.7 μΩ cm (Al), (c) 10 μΩ cm (W), and (d) 100μΩ cm (poly-Si).

Although substrate loss is the dominant loss factor in pulse propagation, the

conductor losses is still not a totally negligible lossy factor. Especially at very high

frequencies, the conductor will finally become a controlling attenuation factor (Figure 5-

11). Figure 5-10 shows the pulse propagation within different conductor materials.

Figure (a) shows the condition with zero conductor resistivity, which occurs with

superconductors. There is still a lot of attenuation in this situation because of the silicon

slow-wave losses. The degradation of using aluminum is not very significant but visible

comparing between (a) and (b). Noticeable changes can also be seen in (c) and (d), in

which the aluminum conductor is changed with tungsten and poly-Si. Especially in the

poly-Si case, lots of losses are observed. Please notice the dispersion in these cases is not

like the one in previous sections. The edges of signals are extremely softened. Whereas,

for instance, the pulse seems to be split in Figure 5-9 (d). This is because the conductor

loss goes up monotonically with frequency as shown in Fig 5-9, so the high frequency

components have higher attenuation.

5.2 Simulation Results of Two Coupled Lines

The attenuation of odd mode is smaller than even mode when the mutual capacitance

is somewhat bigger. This is quite obvious in the point of view of physics. When there

are more electrical field line going to the neighboring line as attracted in odd mode

instead of penetrating to the silicon substrate, there will be less substrate loss which is

dominant in high frequency range. We use a wire with 2.4x2.07um cross section,

3.105uΩcm resistivity, 5.78um thick oxide layer, 4.0 dielectric constant, 450um thick

silicon bulk, 13Ωcm substrate resistivity, 11.8 substrate dielectric constant. Calculated

results for pulse propagation in even and odd mode at different distances are shown in

Figure 5-11 and 5-12. The simulated results agree with the original intuitive thoughts.

58

20 40 60 80 100

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1

(a)

20 40 60 80 100

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1

(b)

20 40 60 80 100

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1

(c)

20 40 60 80 100

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1

(d)

Fig 5-11 Simulated waveform in even mode at (a) 1mm, (b) 2mm, (c) 4mm, (d)

6mm.

20 40 60 80 100

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1

(a)

20 40 60 80 100

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1

(b)

59

20 40 60 80 100

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1

(c)

20 40 60 80 100

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1

(d)

Figure 5-12 Simulated waveform in odd mode at (a) 1mm, (b) 2mm, (c) 4mm, (d)

6mm.

60

6. Second Improved Transmission Line Model and Verification

6.1 Microstrip structure and its equivalent circuits at high frequency

Several compact circuit models [Ken1, Kim1] have been developed based from the

work of Wheeler [Wheeler1]. They usually are in the form of RL ladder network (Cauer

form). However the Foster form, as a series connection of parallel RL elements, is

convenient since contributions of the various elements to the frequency-dependent

impedance are easily visualized. A multi-segment Foster form model was proposed in

[Goren1]. We chose our model in the same Foster form and use two RL sections to

model the skin effect in high frequency. The equivalent circuit is shown in Figure 6-1.

Figure 6-1 The equivalent circuit of on-chip interconnect with consideration of skin

effect at high frequency

From Figure 6-1, one can determine that the overall R and L in series impedance Z are:

2

12

12

122

11

11

111

11 ⎟⎟⎠

⎞⎜⎜⎝

⎛+

+

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+=

LR

R

LR

RRR

ωω

and

2

12

12

122

11

11

111

11 ⎟⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎠

⎞⎜⎜⎝

⎛+

−=

RL

L

RL

LLLωω

(6-1)

61

Obviously, the DC resistance is R1 when frequency is zero and AC resistance is

the sum of R1, R11 and R12 when frequency goes to infinity, which agrees with the nature

of skin effect that resistance increases with frequency. Similarly the DC inductance is

L1 and the AC inductance is the difference of L1 and the sum of L11 and L12. Intuitively,

one can think that more current goes through L11 and L12 rather than R11 and R12 at low

frequency so that it has lower resistance and higher self inductance. At high frequency

the impedances of L11 and L12 go up so that more current will go through R11 and R12

and resistance goes up and inductance goes down as a result.

Figure 6-2 Skin Effect and its modeling in circuits

It is worth to mention that this is just one segment of the whole wire. The number

of the segments should be chosen so that the segment length is less than one tenth of the

on-chip wavelength [Ruehli1].

6.2 Calculation of the values of circuit components

The values of the passive devices in our model are calculated by closed-form

expressions. The DC resistance follows the classical equation that R is proportional to

the resistivity and length while inversely proportional to the cross-section area. Extra

attention should be paid to the thick and wide top level metal that has “cheese” shape

and need technology-based scaling factor.

62

There are a lot of published results to calculate the metal-to-metal and metal-to-

substrate capacitances either using conformal mapping [Svacina1] method or curve-

fitting method [Wong1, Delorme1]. We are using these analytical two-dimensional

capacitance equations and scale with their effective coupling length.

We can use Wheeler’ equation [Wheeler2] with a scaling factor α to calculate the

DC inductance, L1.

⎟⎟⎟

⎜⎜⎜

⎟⎟⎟

⎜⎜⎜

⎥⎥⎥

⎢⎢⎢

⎟⎟⎠

⎞⎜⎜⎝

⎛++⎟⎟

⎞⎜⎜⎝

⎛+=

22

01 8

11321ln4

Reeff

eff

hw

wh

L ππμ

α

and

797.0ln065.0 +⎟⎠⎞

⎜⎝⎛=

whα

(6-3)

where heff is the complex effective height of the interconnect line derived from

complex image theory [Bannister1] and h is the height of the interconnect line over the

backside of the silicon wafer [Singh1]. The AC inductance is obtained by the TEM

property that the product of the capacitance and inductance is equal to the reciprocal of

the square of the speed of light in the dielectrics.

The components values in RL ladder network, L11, L12, R11 and R12, to model the

skin effect can be determined after DC and AC inductances are obtained. First we need

to identify the maximum frequency of the interest, say 100GHz. Then we can let the

first ladder network, R11 and L11 to play a significant role in (6-1) at 10GHz and R12 and

L12 to be significant at 100GHz. To do so, we can set the ratio of R11 to L11 to 1 at

10GHz and the ratio of R12 to L12 to 1 at 100GHz. One can see that we can keep adding

more RL ladder networks to model more accurately at various frequencies in this

method. Finally, the ratio of L11 to L12 is determined by different skin depth at different

frequencies. Knowing the ratios of the variables in Equation (6-1) and values of L and

L1, we can solve for L11, L12 and R11, R12 consequently.

The substrate conductance calculation follows the formula that

63

Si

effSis h

wG

σ=

where

195)(22.3 +++= ttww oxeff

(6-4)

Here, weff refers to the effective width of the slab of silicon between the interconnect

line [Singh1].

6.3 Experimental Verification

6.3.1 Test Structures

A chip with various test structures has been designed and fabricated in an IBM

0.18μm SiGe BiCMOS technology. The test structures include single and coupled

microstrip lines with different shielding scenario and some coplanar waveguide

structures.

Figure 6-3(a) Micrograph of fabricated test structures.

64

Figure 6-3 (b) Micrograph of the fabricated test chip.

Figure 6-3 shows a picture of the fabricated chip. A similar method has been

reported to be valid up to 110GHz [Zwick1].

6.3.2 S-parameter measurement and RLGC extraction

Since at high frequencies there are no real “short” or “open”, it only makes sense to

measure the scattering parameters of the passive devices. We took a two-port vector

network analyzer (VNA) measurement using the HP8510C up to 50GHz and the RF

probe model 50A-GSG-150-P. We did SOLT calibration using GGB CS-5 calibration

substrate and standard calibration using the Cascade Microtech's WinCal. The averaging

set sample size is 256 and the input power is -10 dBm without smoothing.

Then we can extract the equivalent RLGC values from measured S-parameters

[Eo1] using the following equations:

65

1

11

221

211

21

⋅−

⎭⎬⎫

⎩⎨⎧

±+−

= KS

SSe lγ

where

( ) ( )( )

2/1

221

211

2221

211

221

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧ −+−

=S

SSSk

(6-5)

The characteristic impedance Z can be obtained by

( )( ) 2

212

11

221

2112

02

11

SSSS

ZZ−−−+

=

and

ZR γRe= ,

ωγ /Im ZL = ,

ZG /Re γ=

ωγ //Im ZC =

(6-5)

6.4 De-embedding Techniques

In general, pad-parasitic response must be subtracted from test structure response in

high frequency characterizations. Special AC measurement pads were designed and a

de-embedding technique was developed [Tretiakov1] that uses “open” and “short”

dummy structures which have been recently proposed in [Tiemeijer1]. The new “short-

open” de-embedding procedure is given by the following equation:

1111 )()( −−−− −−−= shortopenshortmeasureDUT ZYZYY

(6-6)

66

Figure 6-4 shows the layout of the dummy “open” and “short” devices and their

micrographs from the fabricated chip.

Figure 6-4 Layout and micrograph of dummy “open” and “short” structures

67

6.5 Experimental Results

6.5.1 Single Wire Model vs. Extracted RLGC Verification

We can verify our model by comparing the calculated RLGC parameters using

Equations (6-1) with the extracted RLGC parameters from S-parameters measurement.

Figure 6-5 shows the data from a 1000 μm length, 4 μm width and thickness, and 13 μm

height Copper interconnect. The sheet resistance of the wire is 7 mΩ/. The thickness

of the die is 250 μm and the substrate resistivity is 13.5 Ω•cm. The dielectric constants

are 4.13 for oxide and 11.7 for substrate. We can see the excellent agreement between

the model and measured data.

68

69

Figure 6-5 RLGC values as a function of frequency (Measurement vs. Model)

From Figure 6-5, we can see that our model matches experimental results very

well.

6.5.2 Single Wires with Different Lengths

We also measure the S-parameters of a 3mm long single wire to be compared

with the 1mm long wire. Figure 6-6 shows the S11 and S21 magnitude and phase of the

measured results. Figure 6-7 shows the calculated characteristic impedance of the 1mm

and 3mm wire. We can see that the S11 of 3mm line carries a sinusoidal pattern in the

frequency range measured and has a minimum at about 23GHz, which probably means

there might be some self-oscillating happening at that frequency since a transmission

line is also a LC tank in some way.

70

Figure 6-6(a) S11 magnitude (dB) of 1mm and 3mm single wire

Figure 6-6(b) S11 phase (degree) of 1mm and 3mm single wire

71

Figure 6-6(c) S21 magnitude (dB) of 1mm and 3mm single wire

Figure 6-6(d) S21 phase (degree) of 1mm and 3mm single wire

72

Figure 6-7 Characteristic impedance Z0 of 1mm and 3mm single wire

6.5.3 Coplanar Waveguide (CPW) with Different Bottom Shielding

One popular and very useful on-chip interconnect structure is the coplanar

waveguide (CPW). It differs from a single wire by adding two shielding ground wire

besides the signal wire on the same level. It has very good immunity to the interfering

signal noise from nearby wires and become the de facto on-chip transmission line design

standard. Figure 6-8 shows a cross section view of a coplanar waveguide (Courtesy of

IBM). We designed 4 CPW structure all with side shielding but with different bottom

ground shielding percentage, 0%, 25%, 50% and 100%. Figure 6-9 shows the

calculated RLGC from the measured S-parameters of all four cases. Figure 6-10 shows

the calculated characteristic impedances of all four cases. We conclude that the bottom

shielding with more than zero percentage does help reduce the loss and coupling to

bottom in some degree but the difference between different bottom shielding percentages

is not significant so there is no need of heavy bottom shielding for CPWs.

73

Figure 6-8 Cross section view of a coplanar waveguide.

Figure 6-9(a) Extracted R of different bottom shielding coplanar waveguides

74

Figure 6-9(b) Extracted L of different bottom shielding coplanar waveguides

Figure 6-9(c) Extracted G of different bottom shielding coplanar waveguides

75

Figure 6-9(d) Extracted C of different bottom shielding coplanar waveguides

Figure 6-10 Characteristic impedance Z0 of different bottom shielding coplanar waveguides

76

6.5.4 Coupled Transmission Lines

A pair of coupled transmission lines has been modeled in Section 4.3 using old

single line model without consideration of skin effect. Here we can extend our single

line model with consideration of skin effect to coupled line cases by simply adding one

coupling capacitor between two lines on the existing equivalent circuit.

6.6 Summary

A novel frequency-independent on-chip interconnect model has been presented.

Closed-form formulas are used to calculate the values of passive devices in the

equivalent circuit. Two series RL ladder network are used to capture the high frequency

skin effect in the frequency range of interest. Calculated equivalent RLGC values are

compared with the ones extracted from S-parameter measurement. Excellent agreement

between the model and experiments demonstrates the validity of the model up to 50

GHz. The analytical nature of this model makes it CAD-friendly and could be relatively

easily integrated into design methodology.

77

7. Signal Net Reliability Assessment

7.1 Introduction

Decreasing wire size, increasing frequency, higher circuit density and new

technologies requires new analysis tools to ensure that designs meet technology

specifications. We are studying circuit characteristics with new analytical techniques to

identify signal nets with potential electromigration (Idc) and Joule-heating (Irms)

violation.

Figure 7-1 A cross-section picture of a metal wire that has electromigration effect

Electromigration is a big concern in VLSI design today where unidirectional

currents dominate. Reverse-recovery effects [Ting1] make people think that

electromigration is not significant in signal net wires where bidirectional currents

dominate. However, we notice that some part of signal net also has unidirectional

current especially in big finger devices. So the average DC currents of signal net wires

should be checked against the technology limit set by the requirement of median time to

failure (MTTF) as well as those in power grid to prevent a potential failure.

Another concern is the Joule heating. The bidirectional current in a signal net

wire will heat up itself and its neighboring wires. Since the electromigration current

limit is exponentially dependent on temperature, the Joule-heating makes wires more

78

vulnerable to electromigration. So the root-mean-square (RMS) currents of signal net

wires should also be checked against the technology limit.

An effort has been made to take advantage of static timing analysis to address

these two problems has been made. The work is presented here and organized as

follows: Section 7.2 briefly discusses the electromigration and Joule heating problems in

signal net; Section 7.3 describes our work in detail including the filtering part and

detailed analysis part; Section 7.4 presents the result of a test run of our tool which

gives the violation and some feedback to designer; Section 7.5 lays out our future work

to enhance the existing ability and explore the alternatives in detailed analysis part;

Section 7.6 gives the conclusion.

7.2 Background

Electromigration is a well known process of metal-ion transport due to high

current density stress in metal. Reliability of on-chip interconnect is commonly

characterized by the median time to failure, whose general expression is given by the

Black’s formula [Black1].

)/exp( kTEAJMTTF an−=

(7-2)

where A is a material constant based on the structure and geometric properties of

the conductor, J is the current density, Ea is the activation energy, k is the Boltzmann

constant and T is the temperature in Kelvin. Given a required MTTF, we can set the

current limits for a certain technology.

Electromigration is mostly a problem in power nets because of the constant

bombarding on metal atoms by unidirectional current. But it is also seen in signal nets

where unidirectional current exist. Figure 7-2 shows where the unidirectional current

exists in a simple inverter circuit.

79

Figure 7-2 A simple inverter circuit where both unidirectional current and bidirectional current exist

Bidirectional current causes self-heating and increases temperature which lowers

the electromigration limit of nearby conductors. This is called Joule heating or self

heating problem and it is a traditional concern in signal net wires.

7.3 Methodology

The goal of our work is to analyze current in every signal net wire and via for

technology rule compliance. Ideally, we could run a SPICE simulation of the extracted

post-layout netlist to get the currents on every wire segment of the chip and compare

them to the technology rule for violation. However, simultaneous simulations and

circuit analysis of all nets on a full chip is impractical if not impossible.

One way to decrease the complexity of the problem is to partition the chip and

run the simulation one by one on different macros. It turns out that it is still

computational expensive with respect to turn-around time. A static signal net

electromigration analysis [NS1] is also utilized to expedite the simulation.

80

7.3.1 Two-step approach

The number of independent nets that need detailed simulations can be reduced by

estimating current of each net from operating frequency, load capacitance and signal

slew, assuming minimum width wire (worst case current density) by leveraging static

timing analysis in the first step. Any nets that pass this test can be excluded from further

detailed analysis in the second step.

The static timing analysis tool we used partitions chip into independent nets, so-

called “CCC” (Channel Connected Components), that can be independently solved and

analyzed. The static timing analysis tool also provides capacitance, signal slew,

independent netlist and stimulus for each signal net in a given timing run.

Figure 7-3 Channel connected components

Figure 7-3 shows how CCCs are constructed. CCCs are chosen as the best way

to split up transistor logic because transistor gate terminals make a natural break in

CMOS transistor logic.

81

7.4 PI Model

PI model is used in static timing to get total capacitance of RC network and input

slew at the driving point of RC network. It is generated by matching the first three terms

of a Taylor series expansion of admittance at the driving point of the RC network

[O’Brien1]. The sum of Cnear and Cfar turns out to be the exact sum of all Cs in the RC

network. Figure 7-4 shows a diagram of PI model derived from a complex RC network.

It also shows that we use the input slew as an estimate of the duration time of the pulsed

DC current spike.

Figure 7-4(a) PI Model

Figure 7-4(b) The relationship between the input slew and the duration of current

spike

82

7.5 Current Calculation

7.5.1 Average DC current calculation

It has been shown that electromigration driving force is determined by the

average current density at typical operating frequencies and temperatures [Towner1].

Thus we calculate the average DC current by dividing the total charge transferred by the

total time. We noticed the fact that signal wires typically switch once per cycle while

clock wires switch twice per cycle assuming unity switching factor. Figure 7-5 shows

the difference between a clock net and a regular signal net. To normalize to the clock

net, Equation (7-3) is used to get the average DC current when we divide the switching

factor by two to calculate the correct amount of charge.

FreqsfVddCloadIdc ⋅⋅⋅=2

(7-3)

where Cload is the load capacitance, Vdd is the operating voltage, sf is the

switching factor, Freq. is the operating frequency.

Figure 7-5 Clock net and signal net current waveform

83

7.5.2 RMS current calculation

Root-mean-square current value depends on the current waveform even the total

amount of transferred charge is fixed. Here, we assume triangular current waveform,

which is very close to the result of SPICE simulation. However, it is not an isosceles

one. So we need to use both rising slew and falling slew to approximate rising and

falling transition times. It can be shown that Equation (7-4) gives the RMS current value

for a signal net.

(7-4)

7.6 Verification

To verify our PI model and equations, we use an inverter to drive a single

capacitor and compare the calculated current and measured current by SPICE. In cases

with various driver strengths and loads, the calculation consistently gives a good

approximation and usually more conservative result as we wish. Table 7-1 shows the

results and in most cases a reasonable safety margin is provided. The exception where

Idc is 0.004mA might be caused by leakage current.

To verify our PI model and equations, we use an inverter to drive a single

capacitor and compare the calculated current and measured current by SPICE. In cases

with various driver strengths and loads, the calculation consistently gives a good

approximation and usually more conservative result as we wish. Table 7-1 shows the

results and in most cases a reasonable safety margin is provided. The exception where

Idc is 0.004mA might be caused by leakage current.

)11(32

frFreqsfVddCloadIrms

ττ+⋅⋅⋅⋅=

84

Table 7-1 Calculated Current vs. Simulated Current

Driver

(P/N)

C

load

(pF)

Idc

spice

(mA)

Idc

model

(mA)

Irms

spice

(mA)

Irms

model

(mA)

0.5/0.25 0.001 0.004 0.0036 0.006 0.0068

0.5/0.25 0.05 0.048 0.0671 0.125 0.1406

0.5/0.25 0.005 0.006 0.0068 0.034 0.0408

1.5/0.75 0.05 0.0515 0.0556 0.189 0.2339

7.7 Implementation of Filtering Step

The filtering part is automated by a program written in PERL. The application

reads the project file with technology parameters and specifications of Idc and Irms limit

and the nets file in static timing report which contains capacitance, rising and falling

slew for each signal net. It then calculates the Idc and Irms current, compares with

technology limit, and reports the failed nets. It reverse-calculates the load capacitance

and wire width that would make the net pass design rules in order to provide some

feedback to designer.

7.7.1 Detailed Analysis Step

After the filtering step, we have discovered the potential problematic nets that

could violate the Idc and Irms rules.

We carried out SPICE simulation on the detailed netlist of the problematic net,

which could be obtained by a special function to separate a certain CCC from others.

We simulated a detailed extracted netlist by putting current meters in series to every

resistor to measure their current as a function of time and let SPICE calculate average

DC current and RMS current.

85

Apart from this dynamic analysis approach, a static analysis approach has been

suggested [[Blaauw1]. We also tried to do a static detailed analysis by means of a

linear solver. In order to get the unidirectional current, we perform the linear analysis

twice. First we put stimulus on pull-up network (PUN) while shut off pull-down

network (PDN). We then put stimulus on PDN while shut off PUN. Since the linear

solver is very fast, we could afford to do this twice to tell which wire segment has

unidirectional current and which has bidirectional current. In both cases, we replace

every turned-on transistor with an equivalent resistor and driving transistor with an

equivalent capacitor. Our simulation shows that the linear solver is about hundred times

faster than SPICE simulation. However, the high degree of non-linearity in current

spikes implies inaccuracy.

7.8 Results 7.8.1 Test Case

Figure 7-6 shows the filtering result of a test circuit, which is 100 um by 100 um

in size and contains 3020 signal nets. It takes only a few seconds to run and about 5% of

total nets fail Idc test when the switching factor is 25%, which is a typical value in

digital circuits. As a very promising result, the work load of detailed analysis in the

second step is significantly reduced after filtering.

86

Failed Net Percentage vs. Switching Factor

0

5

10

15

20

25

30

35

40

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Switching Factor

Perc

enta

ge o

f Fai

led

Net

Idc

Irms

Figure 7-6 Filtering Result of a Test Macro

7.8.2 Sensitivity Analysis

We also did a sensitivity analysis by varying the minimum wire width and the

load capacitance. This would provide some feedback to the designer. Figure 7-7 shows

the results.

87

Sensitivity of Wire Width

0

1

2

3

4

5

6

1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2Wire Width (minum)

Perc

enta

ge o

f Fai

led

Net

s Idc

Irms

Sensitivity of Capacitance

0

1

2

3

4

5

6

1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1Total Capacitance (load)

Perc

enta

ge o

f Fai

led

Net

s

Idc

Irms

Figure 7-7 Sensitivity to (a) Wire Width and (b) Load Capacitance

88

7.9 Future Work

7.9.1 Enhancement of Existing Ability

We can have a better current limit for each net in the filtering step if we have the

geometry information of each wire segment of a signal net. In the detailed analysis step,

we need to automate the SPICE simulation to integrate it into the flow. It would also be

worthy to continue to explore the method of solving the circuit by a linear solver because

of the outstanding speed of the linear solver.

7.9.2 Temperature-aware Electromigration Analysis

We need to tie in thermal analysis at the macro/chip level to set the

electromigration limit for current as a function of temperature. Currently we use a

maximum temperature as default, which is extremely conservative and sacrifices the

chip performance unnecessarily.

7.10 Summary

A methodology to do signal net electromigration and Joule heating analysis has

been presented. A tool to filter signal nets to identify potential electromigration and

Joule heating violation has been developed. A new approach to do static detailed

analysis using linear solver has been explored. Future plans to enhance and complete

signal net electromigration and Joule-heating analysis at chip level have been proposed.

89

8. Discussion and conclusion

8.1 Application

8.1.1 Transmission Line Modeling Work

Due to the ubiquity of the on-chip interconnect, this work has very broad

application. It can be used to do signal integrity check for all integrated circuits (IC)

design as a step of the check-off procedures in the design flow. Fortunately our lab has

various IC design work going on such as RISC CPU, FPGA, SERDES, ADC/DAC.

Most of them are high performance digital circuits implemented in BiCMOS CML

circuits. At frequencies high enough, almost all wires behave as transmission lines. So

far, there is no a good tool in Cadence or other EDA tool that integrates the transmission

line simulation into SPICE-like simulator while the effect can not be ignored any more.

Everyone in our group is interested of simulating their chips with this modeling work

and we just got started to utilize it in our designs. For example, it helped to design the

H-shape clock tree in a 20x20 FPGA by simulating the signal attenuation of clock signal

and optimize the buffer placement [Guo1]. We expect to see more chip design will use

this tool to check the signal integrity before they are sent to fabrication which is a very

expensive process in these days. In semiconductor industry, it will be a million-dollar

mistake to have a design failure.

8.1.2 Signal Net Reliability Assessment

This work can be extended and completed to screen signal nets of a full chip to

identify potential electromigration and Joule heating violation as step of the final check-

off in a chip design methodology.

8.2 Future Work

8.2.1 Future Modeling Work

We can certainly improve our modeling work by considering more physical

effects such as mutual inductance or calculating the parameters more accurately with the

90

more latest published closed-form formulas. We can also explore multi-conductor and

multi-layer network to solve the general problem of n-line. However, it will be very

complicated to consider many lines at one time and their mutual coupling. The basic

idea to solve this problem should be only consider the nearest neighbor lines, say two, if

there is only one layer, and it leads to solve a big matrix of the circuit network which

would depend on an optimized matrix solver.

8.2.2 CAD Tool Development

For the transmission line modeling work, the simulation is done within

Mathematica® and Matlab® software and circuit designers has to run this standalone

simulation manually. It would be ideal to make a on-the-fly program that is totally

integrated into Cadence and invisible to designers that tells the designer possible

attenuation and delay once the layout has been drawn with other parameters given.

Since we do not have access to the source code of Cadence, we can only develop a

standalone program, hopefully with some graphic user interface (GUI), to help designers

to estimate the transmission line effect of their relatively long wires on the critical path

of the chip. An attempt has been made to write the spice style file to model the

transmission line, which is shown in Appendix B, but how to fully integrate it into the

Cadence design flow still need to be explored.

91

References

[Aubourg1] M. Aubourg et al. “Analysis of MIS or Schottky contact coplanar lines

using the FEM and the SDA”, IEEE MTT-S Int. Microwave Symp. Dig., pp. 396¨C398,

1983.

[Bannister1] P. R. Bannister, “Applications of Complex Image Theory”, Radio

Science, vol. 21, no. 4, pp. 605-616, August 1986.

[Blaauw1] Blaauw, D., Oh, C., Zolotov, V., Dasgupta, A., Static Electromigration

Analysis for On-Chip Signal Interconnects, IEEE Transactions on CAD, Vol. 22, No. 1,

January 2003, pp.39-48.

[Black1] Black, J.R., Electromigration Failure Modes in Aluminum Metalization

for Semiconductor Devices, Proceedings of IEEE, 57, p. 1587, 1969

[Delorme1] N. Delorme, M. Belleville and J. Chilo, “Inductance and capacitance

analytic formulas for VLSI Interconnects”, IEEE Electronics Letters, vol. 32, no. 11, pp.

996-997, May 1996.

[Deutch1] A. Deutsch, P.W. Coteus, G.V. Kopcsay, H.H. Smith, C.W. Surovic, B.L.

Krauter, D.C. Edelstein, and P.J. Restle, “On-Chip Wireing Design Challenges for

Gigahertz Operation”, IEEE Proceedings, vol. 89, no. 4, pp. 529-555, April 2001.

[Deutsch2] A. Deutsch, G. V. Kopcsay, V. A. Ranieri, J. K. Cataldo, E. A. Galligan,

W. S. Graham, R. P. McGouey, S. L. Nunes, J. R. Paraszczak, J. J. Ritsko, R. J. Serino,

D. Y. Shih, J. S. Wilczynski. “High-speed signal propagation on lossy transmission

lines”, IBM J. Res. Develop., vol. 34, no 4, pp. 601¨C615, July 1990.

[Diao1] J. Diao, Y.L Le Coz, R. B. Iverson, J. F. McDonald, Proc. of VLSI

Multilevel Interconnection Conference Proceedings, Santa Clara, California 1999.

[Diao2] J. Diao, Y.Tretiakov, R. Singh, Y.L Le Coz, J. F. McDonald, Proc. of

VLSI Multilevel Interconnection Conference Proceedings, Los Angels, California 2003.

92

[Diao3] J. Diao, Y.Tretiakov, R. Singh, Y.L Le Coz, J. F. McDonald, Proc. of

VLSI Multilevel Interconnection Conference Proceedings, Hawaii, 2004.

[Diao4] J. Diao, etc, Proc. of VLSI Multilevel Interconnection Conference

Proceedings, Santa Clara, California 2005

[Dworsky1] L. N. Dworsky, Modern Transmission Line Theory and Applications,

John Wiley & Sons, Inc, NY, 1979.

[Eo1] Y. Eo and W. R. Eisenstadt, “High-Speed VLSI Interconnect Modeling

Based on S-Parameter Measurements”, IEEE Trans. On Components, Hybrids and

Manufacturing Technol-ogy, vol. 16, no. 5, pp. 555-562, August 1993.

[Fukuoka1] Y. Fukuoka, Y. C. shih, T. Itoh, “Anylysis of slow-wave coplanar wave

guide for monolithic integrated circuits”, IEEE Trans. Microwave Theory Tech., vol.

MTT-31, pp. 567¨C573, July, 1983.

[Gilb1] J. P. K. Gilb, A. Balanis, “MIS Slow-Wave structures over a wide range

of parameters”, IEEE Trans. Microwave Theory Tech., vol. MTT-40, pp. 2148¨C2154,

Dec. 1992.

[Goossen1] K. Goossen, R. Hammond, “Modeling of Picosecond Pulse Propagation

in Microstrip Interconnnections on Integrated Circuits”, IEEE Trans. MTT, Vol. 37, No.

3, pp. 469-78, March 1989.

[Goossen1] K. W. Goossen, R. B. Hommond, “Modeling of picosecond pulse propa-

gation in microstrip interconnections on integrated circuits”, IEEE Trans. Microwave

Theory Tech., vol. MTT-37, No. 3, pp. 469¨C478, March 1989.

[Goren1] D. Goren, M. Zelikson, R. Gordin, I.A. Wagner, A. Barger, A. Amir, B.

Livshitz, A. Sherman, Y. Tretiakov, R. Groves, J. Park, D. Jordan, S. Strang, R. Singh,

C. Dickey, and D. Harame, “On-chip Interconnect-Aware Design and Modeling

Methodology, Based on High Bandwidth Transmission Line Devices”, Proceedings of

Design Automation Conference, pp. 724-727, June 2003.

[Guo1] J. Guo, C. You, M. Chu, J. Diao, R. Kraft, J. McDonald, “The 10GHz

4:1 MUX and 1:4 DEMUX implemented by the Gigahertz SiGe FPGA” Proc. GLVLSI,

Boston, Massachusetts 2004

93

[Harrington1] R. F. Harrington, Field Computation by Moment Methods. New York:

IEEE Press, 1993.

[Hasegawa1] H. Hasegawa, S. Seki, “On-chip pulse transmission in very high speed

LSI/VLSI”, IEEE Microwave and Millimeter-Wave Monolithic Circuits Symp. Dig.

(San Framcisco), 1984, pp. 29¨C33.

[Hasegawa2] H. Hasegawa, M. Furukawa, H. Yanai, “Properties of microstrip line on

Si-SiO2 system”, IEEE Trans Microwave Theory Tech., vol. MTT-19, no. 11, pp.

869¨C881, Nov. 1971.

[Jin1] J. Jin, The Finite Element Method in Electromagnetics. New York:

Wiley, 1993.

[Ken1] B. K. Sen and R. L. Wheeler, “Skin effects models for transmission line

struc-tures using generic Spice circuit simulators”, in Proc. EPEP??98-7th Topical

Meeting on Electrical Performance of Electronic Packaging, pp. 128¨C131, Oct. 1998.

[Kim1] S. Kim and D.P. Neikirk, “Compact equivalent circuit model for the skin

effect”, IEEE Microwave Theory and Techniques Symp. Dig., pp. 1815-1818, 1996.

[Kirschning1] M. Kirschning, R. H. Jansen, “Accurate model for effective dielectric

constant of microstrip with validity up to millimeter-wave frequencies”, Electronics

Letters, vol. 18, no. 6, pp. 272¨C273, March 1982.

[Kowalski1] G. Kowalski et al., Arch. Elek. ¨?bertragung, vol. 107, pp. 163, Apr.

1971.

[Krowne1] C. Krowne, G. Tait, “Propagation in layered biased semiconductor

structures based on transport analysis”, IEEE Trans. Microwave Theory Tech., vol.

MTT-37, pp. 711¨C722, Apr. 1989.

[NS1] NS, N., Cano, F., Haznedar, H., Young, D., A Practical Approach to

Static Signal Electromigration Analysis, Proceedings of DAC 1998, pp. 572-577.

[O'Brien1] O’ Brien, P., Modeling of Driving Point Characteristics of Resistive

Interconnect for accurate delay estimation, Proceeding of ICCAD 1991, pp. 515-515.

94

[Paul1] C. R. Paul, Analysis on Multiconductor Transmission Lines, John Wiley

& Sons, Inc. 1994.

[RLC1] QuickCAP, Random Logic Corporation, Fairfax, VA.

[Ruehli1] A. E. Ruehli and A.C. Cangelaris, “Progress in the Methodologies for the

Electrical Modeling of Interconnects and Electronic Packages”, IEEE Proceedings, vol.

89, no. 5, pp. 740-771, May 2001

[Shibata1] T. Shibata, E. Sano, “Characterization of MIS structure coplanar trans-

mission lines for investigation of signal propagation in integrated circuits”, IEEE Trans.

Microwave Theory Tech., vol. 38, pp. 881¨C890, July 1990.

[Shih1] Y. Shih, T. Itoh, “Analysis of printed transmission lines for monolithic

integrated circuits”, Electron. Lett., vol. 18, pp. 585¨C586, July 1982.

[Singh1] R. Singh, et al., Silicon Germanium Technology, Modeling, and Design,

IEEE Press, pp. 204. Wiley-Interscience, New York 2004.

[Svacina1] J. Svacina, “Analysis of Multilayer Microstrip Lines by a Conformal

Mapping Method”, IEEE Trans. Microwave Theory and Technology, Vol. 40, No. 4, pp.

769¨C72, April 1992.

[Svacina1] J. Svacina, “Analysis of multilayer microstrip lines by a conformal

mapping method”, IEEE Trans. Microwave Theory Tech. vol. MTT-40, no. 4,

pp769¨C772, Apr. 1992.

[Tiemeijer1] L. Tiemeijer, R. Havens, “A calibrated lumped- element deembedding

technique for on-wafer RF characterization of highquality inductors and high-speed

transistors”, IEEE Transactions on Electron Devices, Vol. 50, No. 3, March 2003, pp.

823-829.

[Ting1] Ting, L. May, J.S., Hunter, W.R. and McPherson, J.W., AC Electromigra-

tion Characterization and Modeling of Multilayered Interconnections, Proceedings of

IRPS, pp. 311-316, 1993

[Towner1] Towner, J.M., van de Ven, E., Aluminum Electromigration Under Pulsed

DC Conditions, Proceeding of 21st Annual IRPS, pp. 36, 1983

95

[Tretiakov1] Y. Tretiakov, K. Vaed, D. Ahlgren, J. Rascoe1, S. Venkatadri1, W.

Woods, “On-Wafer De-Embedding Techniques for SiGe/BiCMOS/RFCMOS

Transmission Line Interconnect Characterization”, IEEE Intl. Interconnect Technology

Conf., pp. 166-168, June 2004.

[Tretiakov1] Y. Tretiakov, K. Vaed, D. Ahlgren, J. Rascoe, Sonal Venkatadril, Wayne

Woods, “On-Wafer De-Embedding Techniques for SiGe/BiCMOS/RFCMOS

Transmission Line Interconnect Characterization”, IEEE Intl. Interconnect Tech-nology

Conf., 2004.

[Tzuang1] C. K. C. Tzuang, T. Itoh, “High-speed pulse transmission along a slow-

wave CPW for monolithic microwave integrated circuits”, IEEE Trans. Microwave

Theory Tech., vol. MTT-35, pp. 697¨C704, Aug. 1987.

[Wang1] L. Wang, etc., “Modeling of Metal-over-Silicon Microstrip

Interconnections: The Effect of SiO2 Thickness on Slow-Wave Losses”, IEEE Intl.

Interconnect Technology Conf., pp 178-180, 1998.

[Wang1] L. Wang, Y.L Le Coz, R. B. Iverson, J. F. McDonald, Proc. of IEEE Int.

Interconnect Tech. Conf., June 1998, pp. 178-180.

[Weisshaar1] A. Weisshaar, H. Lan, and A. Luoh, “Accurate Colosed-Form

Expressions for the Frequency-Dependent Line Parameters of On-Chip Interconnects on

Lossy Silicon Sub-strate”, IEEE Trans. On Advanced Packaging, vol. 25, no. 2, pp. 288-

296, May 2002.

[Welch1] J. D. Welch, H. J. Pratt, “Losses in microstrip transmission systems for

integrated microwave circuits”, NEREM Rec., vol. 8, 1966, pp. 100¨C101, 1966.

[Wheeler1] H.A. Wheeler, “Formulas for the skin effects”, Proceedings of

International Radio Engineers, pp. 4112-424, 1942.

[Wheeler1] H. A. Wheeler, “Formulas for the skin-effect”, Proc. IRE, pp. 412¨C424,

1942.

[Wheeler2] H. A. Wheeler, “Transmission-line properties of a strip on a dielectric

sheet on a plane”, IEEE Trans. Microwave Theory and Technology, vol. MTT-25, pp.

631-647, August 1977.

96

[Wheeler3] H. A. Wheeler, “Transmission-line properties of parallel wide strip by a

conformal-mapping approximation”, IEEE Trans. Microwave Theory Tech., pp.

280¨C289, May 1964.

[Wong1] S. Wong, G. Lee and D. Ma, “Modeling of interconnect capacitance,

delay and crosstalk in VLSI”, IEEE Trans. Semiconductor Manufacturing, vol. 13, no. 1,

pp. 108-111, February 2000.

[Yamashita1] E. Yamashita et al., IEEE Trans. Microwave Theory Tech., vol. MTT-24,

pp. 195, Apr. 1976.

[Yamashita1] E. Yamashita et al., IEEE Trans. Microwave Theory Tech., vol. MTT-24,

pp. 195, Apr. 1976.

[Yao1] Y. Cao, R. Groves, X. Huang, N. D. Zamder, J. Plouchart, R. Wachnik, T.

King, and C.Hu, “Frequency-Independent Equivalent-Circuit Model for On-Chip Spiral

Inductors”, IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 419-426, March 2003.

[Yee1] K. S. Yee, “Numerical solution of initial boundary value problems

involving Maxwell’s equations in isotropic media”, IEEE Trans. Antennas Propagat.,

vol. AP-14, pp. 302¨C307, May 1966.

[Yue1] C. P. Yue and S.S. Wong, “Physical Modeling of Spiral Inductors on

Silicon”, IEEE Trans. On Electron Devices, vol. 47, no. 3, pp. 560-568, March 2000.

[Zheng1] J. Zheng, Y. C. Hahm, V. K. Tripathi, and A. Weisshaar, “CAD-oriented

equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate”, IEEE

Trans. Microwave Theory Tech., vol. 48, pp. 1443¨C1451, Sept. 2000.

[Zwick1] T. Zwick, Y. Tretiakov, and D. Goren, “On-Chip SiGe Transmission Line

Measurements and Model Verification Up to 110GHz”, IEEE Microwave and Wireless

Compo-nents Letters, vol. 15, no. 2, pp. 65-67, February 2005.

97

Appendix A

The key parts of Mathematical codes used to do numerical simulation of the first improved model.

A. 1 Initialization

Off@General::spellD;Off@General::spell1D;FilenameBase = "E:\\Research\\clock\\clocktree_";

c = 3 108;μ0 = 4 π 10−7;μ = μ0;

w0 = 0.28 10−6;tc = 0.31 10−6;ρc = 0.089∗0.31 10−8;tox = 3.44 10−6;∂rox = 4.1;hall = h+ tox;h = 400 10−6;∂r = 11.8;ρs = 13.5 10−2;k = 1.55;km = 0.5;

98

A.2 Input singal generation

sp = 8192; sf = 60 1012; sτ =1sf

êê N;f = 20 109;

τ =12 f

;

rt =3 10−12

[email protected] ;

InputWave = −1+ 2∗J1 − E− trt + J−1+ E

τ−trt NUnitStep@−τ + tD

+ J1 − E2 τ−trt NUnitStep@−2 τ + tD+ J−1+ E

3 τ−trt NUnitStep@−3 τ + tD

+ J1 − E4 τ−trt NUnitStep@−4 τ + tD+ J−1+ E

5 τ−trt NUnitStep@−5 τ + tD

+ J1 − E6 τ−trt NUnitStep@−6 τ + tD+ J−1+ E

7 τ−trt NUnitStep@−7 τ + tD

+ J1 − E8 τ−trt NUnitStep@−8 τ + tD+ J−1+ E

9 τ−trt NUnitStep@−9 τ + tD

N;Print@"−−−−−− original input signal −−−−−−−−−−−−"D;ListInput = Table@N@InputWave, 5D, 8t, 0, sτ ∗Hsp− 1L, sτ<D;Length@ListInputD

99

A.3. Calculate effective width and dielectric constant

w = IfA w0h

<12 π

,

w0+tcπ

JLogA 4 π w0tc

E +1N,

w0+tcπ

JLogA 2 htc

E +1NE êê N;Print@"−−−−−−effective width−−−−−−−−−−−−"D;Wef = w +

2 hallπ

LogA17.08 J w2 hall

+0.92NEq1 = IfAw >= hall,

12

h

hall

i

k1+

π

4−hallWef

LogAπ Wefhall

SinA π h2 hall

Eπ h

2 hall

+ CosA π h2 hall

EEy

,

LogA 1+ hhall

1− hhall+ w

4 hallE

2 LogA 8 hallw

E

i

k1+

π

4−12ArcCosA hall

h

w8 hall

&1+ h

hall

1− hhall

+ w4 hall

Ey

Eêê N;

q2 = IfAw >= hall,

1− q1 −12

LogA π

hall Wef− 1E

Wefhall

,

12

+0.9

π LogA 8 hallw

E− q1E êê N;

∂eff0 = 1− q1 −q2 + ∂rox ∂rHq1 + q2L2

∂r q2 +∂rox q1;

Print@"−−−−−−effective dielectric constant−−−−−−−−−−−"D∂eff =

i

k

è∂eff0 + Iè∂r −

è∂eff0M ì

i

k1+ 4

ik4 f h

è∂r− 1c

J 12

+J1 + 2 LogA10, 1 +whEN2Ny

− 32 y

y

^2

100

A.4 Calculate attenuation constant

Z0 =60 LogA 8 h

w+ w

4 hE

è∂eff

;

Z00 =60 LogA 8 h

w+ w

4 hE

è∂eff0

Rs =è

π f μ ρc êê N;Print@"−−−−−− conductor attenuation −−−−−−−−−−−−"D

αc =Rs

2 π Z0 h J1 − J w

4 hN2N

i

k1 +

hw

+h

π w i

kLogA 4 π w

tc+ 1E −

1 − tcw

1 + tc4 π w

y

y

αc0 =

ρc2 w0 t Z00

êê N;

β0 =2 π fc

è∂eff ;

βm = β0 èkm ;

Print@"−−−−−− dielectric attenucation −−−−−−−−−−−−"D;αd =

60 π H∂eff − 1Lρs

è∂eff H∂r − 1L

αd0 =60 π H∂eff0 − 1L

ρs è∂eff0 H∂r − 1L

êê N;

Print@"−−−−−− f1 −−−−−−−−−−−−"D;

f1 =β02 k H k H−4 αc αd + β02L + H4 αd2 + β02LL

β02 + 2 k β02 + k2 H4 αd2 + β02L − βm2

Print@"−−−−−− f2 −−−−−−−−−−−−"D;

f2 =H4 αc2 + β02L

IH1 + kL2 + 4 αd2β02

M2

ik4 αd2 k4 + β02

ikHk − kmL

4 αd2

β02+ Hk − km Hk + 1LL Hk + 1Ly

2y

Print@"−−−−−− alpha −−−−−−−−−−−−"D;

α = $ −f1 +èf2

2êê N

Print@"−−−−−− beta −−−−−−−−−−−−"D;

β = $ f1 +èf2

2êê N

Fs = 8 1013; Pts = 8192; Secs =1012

Fsêê N;

Listα = PrependATableAα, 9f, FsPts − 1

,Fs Pts

2 HPts − 1L ,Fs

Pts − 1=E, 0E;

Listβ = PrependATableAβ, 9f, FsPts − 1

,Fs Pts

2 HPts − 1L ,Fs

Pts − 1=E, 0E;

101

A.5 Calculate output waveform

FourInput = Chop@Fourier@ListInputDD;TimeInteval = τê1000 êê N;TimeLabel = Table@TimeInteval∗i, 8i, 0, Length@ListInputD<D;PlotList0 = Table@8TimeLabel@@iDD, ListInput@@iDD<,

8i, 1, Length@ListInputD<D;Print@"−−−−−− input signal after fourier transform −−−−−−−−−−−−"D;ListPlot@PlotList0, PlotRange −> All, PlotJoined −> TrueD;

For@zlist = 80, 100 10−6, 200 10−6, 300 10−6, 400 10−6, 500 10−6,600 10−6, 700 10−6, 800 10−6, 900 10−6, 1000 10−6, 2000 10−6,3000 10−6, 4000 10−6, 5000 10−6, 6000 10−6<;i = 1, i <= Length@zlistD, i++,Print@"−−−−−−− At "<> ToString@zlistPiT∗106D <>

"um −−−−−−−"D;ListTrans0 = E−HListα−IListβL zlistPiT;ListTrans = Join@Delete@ListTrans0, −1D,Conjugate@Reverse@Delete@ListTrans0, 1DDDD;Result = N@Chop@Re@InverseFourier@FourInput∗ListTransDDD, 5D;Print@"The Maximum is "<> ToString@Max@ResultDDD;RealFilename = FilenameBase<> "output_" <>

ToString@zlistPiT∗106D<> ".dat";Print@"Wrinting "<> RealFilenameD;DataListWrite@Result, 512, RealFilenameD;Print@"Ploting"D;PlotList = Table@8TimeLabelPjT, ResultPjT<,8j, 1, Length@ListInputD<D;ListPlot@PlotList, PlotRange −> 8−1, 1<, PlotJoined −> TrueD

D

102

Appendix B

Matlab code for processing S-parameter data and numerical calculation of the second improved model.

B.1 alculate_circuit_elements.m

%

% /\/\/\/\ /\/\/\/\

%in r_line_1 l_line_1 | | | | out

% r_skin_11 r_skin_12

% o---+---/\/\/\/\------()()()()--------| |-----| |-------------------+------------------------o - - - - - - o

% | | | | | |

% | ()()()() ()()()() |

% | l_skin_11 l_skin_12 |

% | |

% | |

% | |

% ----- -----

% ----- c_ox_1 c_ox_2-----

% | |

% +-------------------+ +----------+

% | | | |

% | | | |

% / | / |

% \ r_sub_1 ----- c_sub_1 r_sub_2 \ ----- c_sub_2

% / ----- / -----

% \ | \ |

% | | | |

% | | | |

%o-+--------------------+-------------------------------------------------+--------+-------------o - - - - - - o

pw = 4e-6;

pheff = 13e-6;

eoxdepo = 3.9;

pl = 1000e-6;

103

e0 = 8.8542e-12;

u0 = 12.56637e-7;

ersi = 11.2;

rsub_f = 1e-4; % substrate resistivity

mat_f = 4e-6; % MA level metal thickenss ???

pmsxt = 1e-6; % unit scale factor (?)

mars_f = 1e-6; % unit scale factor (?)

ind = -1; % internal inductance

% calculate capacitance and resistance from top to bottom of Si substrate

if pw/pheff < 0.6

coxide = (1.74*e0*eoxdepo*((pw/pheff)+0.79115));

else

coxide = e0*eoxdepo*((pw/pheff) + 2.42 - 0.44*(pheff/pw) + (1-pheff/pw)^6);

end

cscaleox = 0.93 + 0.32*exp(-0.75*(pl/100e-6)) + 0.35*exp(-0.10*pw/1e-6);

cloxide = coxide*cscaleox*pl/9; % c_oxide

cond_si = 1/rsub_f;

cscalesub = 3/(pl/100e-6);

wsubc = pw + 2*pheff + mat_f;

clsub = pl*cscalesub*e0*ersi*(3*pw/pmsxt + 0.5*1.5823)/9; % c_sub

rscalesub = (1.41 + 0.4*log(0.1*pl/100e-6)) + (0.024 + 0.006*log(0.1*pl/100e-6))*pw/1e-6;

glsub = cond_si*6*wsubc/pmsxt;

rlsub = 9*rscalesub/(glsub*pl); % r_sub

rlinetot = mars_f/(pw);

rline = rlinetot*pl/8; % r_line_1

% calculate inductance of the line at DC and as f-->infinity

ind_h_inf = pheff;

ind_h_low = pheff + pmsxt;

ind_low = 1e-7*log(1 + (32*ind_h_low/pw)^2 * (1 + sqrt(1+(pi*pw/(8*ind_h_low))^2)));

ind_inf = 1e-7*log(1 + (32*ind_h_inf/pw)^2 * (1 + sqrt(1+(pi*pw/(8*ind_h_inf))^2)));

lscalefin = 0.75+0.03*log((pl/100e-6)^4-0.5) + (0.05+0.017*log(-0.95+pl/100e-6))*log10(pw/1e-

6);

diff_ind = lscalefin*(ind_low - ind_inf)*pl;

104

% if inductance value is passed in, scale final self and mutual inductances appropriately

if ind > 0

lscale = (ind - diff_ind)/(lscalefin*ind_inf*pl - diff_ind);

elseif ind == -1

lscale = (ind - diff_ind)/(lscalefin*ind_inf*pl - diff_ind) + 1;

end

plfinal=lscale*(lscalefin*ind_inf*pl - diff_ind)/8; % 8 segments

% calculate circuit element values for two R-L skin effect networks

dropf = 12.90 - 0.40*(pw/1e-6);

dllow = 0.08*exp(-0.35*((pw/1e-6)-4)) + 0.035;

delta_l_a = diff_ind/8; % l_skin_11

delta_r_a = 3162e9*delta_l_a; % r_skin_11 3.162 = sqrt(10)

delta_l_b = dllow*delta_l_a; % l_skin_12

delta_r_b = 2*pi*dropf*1e9*delta_l_b; % r_skin_12

% calculate equivalent RLGC

omega = 2*pie*freq;

rr = r + r1./(1+(r1./(omega*l1))) + r2./(1+(r2./(omega*l2)));

ll = l - l1./(1+(omega/r1*l1)) - l2./(1+(omega/r2*l2));

B.2 compareRLGC.m

% This Matlab program takes S parameters from a touchstone file

% and calculate the RLGC p.u.l as well as S11 and S21 mag(db) and phase

% The RLGC extracted from S-parameters are compared with closed-form

% calculation.

fname = 'line1_corrected_die_1.s2p';

[spars_spectre, freq_spectre, type, z0] = gettouch(fname,'s');

line_length = 1.0e-6;

freq_spectre = freq_spectre * 1.0e9;

105

% seperate s paramters and get S11, S21 20db magnitude and phase

s11_spectre = spars_spectre(:,1);

s12_spectre = spars_spectre(:,2);

s21_spectre = spars_spectre(:,3);

s22_spectre = spars_spectre(:,4);

s11_spectre_db = 20.0 * log10( abs( s11_spectre ) );

s11_spectre_ph = angle( s11_spectre ) * 180.0 / pi;

s21_spectre_db = 20.0 * log10( abs( s21_spectre ) );

s21_spectre_ph = unwrap(angle( s21_spectre )) * 180.0 / pi;

% extract RLGC from s paramters

[ r_spectre, l_spectre, c_spectre, g_spectre, z_spectre, gm_spectre ] =

tlinerlcg_total(freq_spectre, spars_spectre, line_length);

% plot extracted RLGC as a function of frequency

clf;

subplot(2,2,1);

title('R'); xlabel('freq (GHz)'); ylabel('R');

plot(freq_spectre, r_spectre, 'ro');

%plot(freq_spectre, r_spectre, 'ro',freq_spectre, r, 'b+');

subplot(2,2,2);

title('L'); xlabel('freq (GHz)'); ylabel('L');

plot(freq_spectre, l_spectre, 'b+');

subplot(2,2,3);

title('G'); xlabel('freq (GHz)'); ylabel('G');

plot(freq_spectre, g_spectre, 'y*');

subplot(2,2,4);

title('C'); xlabel('freq (GHz)'); ylabel('C');

plot(freq_spectre, c_spectre, 'gx');

%plot(freq_spectre, s11_spectre_db);

%everything = [freq_spectre r_spectre l_spectre c_spectre g_spectre z_spectre gm_spectre

s11_spectre_db s11_spectre_ph s21_spectre_db s21_spectre_ph];

% geomotry of the wire and substrate

rho = 10;

rhoSi = 13;

106

e0 = 8.854e-12;

u0 = 12.566e-7;

eSi = 11.9;

eOx = 3.9;

omega = 2*pi*freq_spectre;

height = 13e-6;

length = 1e-3;

width = 4e-6;

thickness = 4e-6;

distance = 5e-6;

delta =(rho/pi/u0./freq_spectre).^0.5;

teff = delta.*(1-exp(-thickness./delta));

r = rho/width./teff;

l = 2*length*(log(2*length/(width+thickness)) + 0.5 + (width+thickness)/3/length);

%calculate r,l considering skin effect

%alphaR = 3.47;

%alphaL = 0.315 * alphaR;

%r0 = rho * length / width / thickness;

%rs = 0.007;

%weff = 4;

%r0 = rs/weff*length*1e+6;

%r1 = r0 * alphaR;

%r2 = r1 * alphaR;

%l0 = 2*length*(ln(2*length/(width+thickness)) + 0.5 + (width+thickness)/3/length);

%l1 = l0 * alphaL;

%l2 = l1 * alphaL;

%r = r0 + r1./(1 + (r1/l1./omega).^2) + r2./(1 + (r2/l2./omega).^2);

%l = l0 - l1./(1 + (omega*l1/r1).^2) + l2./(1 + (omega*l2/r2).^2);

% calulate g,c from geometries

%c11 = eOx*e0*(1.13*width/height + 1.44*(width/height)^0.11 +

1.47*(thickness/height)^0.42);

%c11 = eOx*e0*(1.11*width/height + 0.79*(width/height)^0.1 + 0.59*(thickness/height)^0.53

+...

107

% (0.52*(width/height)^0.001 + 0.46*(thickness/height)^0.17)*(1-0.87*exp(-

distance/height)));

%Cinf = 1;

%Csi = Cox * Cinf / (Cox - Cinf);

%Cox = e0*width*length/height;

%Csi = 1;

%Gsi = 1/(rhoSi*e0*eSi*Csi);

%g = omega.^2*Gsi*Cox^2/(Gsi^2 + omega.^2*(Csi+Cox)^2);

%c = (omega.^2*Csi*Cox*(Csi+Cox) + Cox*Gsi^2)./(Gsi^2 + omega.^2*(Csi+Cox)^2);

B.3 create_golden_rfline_hspice_model_a.m

function z=create_golden_rfline_hspice_model_a(new_golden_circuit_fid),

fwrite(new_golden_circuit_fid,'* Path, Component, Release: %W%');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* CMVC Revision: %I% %E% %U%');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*> T-LINE MODEL 7HP "indline" Analog Metal (MA) Line over

BFMOAT'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* Indline model for MA line over BFMOAT');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* The indline model contains:');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 1. Eight R-L-C networks connected in series representing');

fwrite(new_golden_circuit_fid,10,'uchar');

108

fwrite(new_golden_circuit_fid,'* the variation in inductance, capacitance, and resistance with

frequency'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* Example of one of such a block is shown below.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 2. Nine oxide capacitances (c_ox_1, c_ox_2, ..., c_ox_last)

representing the capacitance'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* between the analog metal line and the substrate.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 3. Nine substrate capacitances (c_sub_1, c_sub_2, ..., c_sub_last)

and resistances'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* (r_sub_1, r_sub_2, ..., r_sub_last) representing the effect of the

loss in the'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* conductive silicon substrate.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* r_skin_11 r_skin_12 ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* /\/\/\/\ /\/\/\/\ ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* in r_line_1 l_line_1 | | | | out');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* o---+---/\/\/\/\------()()()()--------| |-----| |----+----o - - - - - - o ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | ()()()() ()()()() | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | l_skin_11 l_skin_12 | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

109

fwrite(new_golden_circuit_fid,'* ----- ----- ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* ----- c_ox_1 c_ox_2----- ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* +-------------+ +-------------+ ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* / | / | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* \ r_sub_1 ----- c_sub_1 \ r_sub_2 ----- c_sub_2

'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* / ----- / ----- ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* \ | \ | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* o----+-------------+------------------------------+-------------+----o - - - - - -

o '); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* gnd (substrate/groundplane)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* SYNTAX:'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* x1 in out gnd indline'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + l = 100e-6 // length of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

110

fwrite(new_golden_circuit_fid,'* + w = 4e-6 // width of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + ind = -1 // inductance of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* // if ind==-1 then calculate self inductance internally');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + tlev1 = 3 // Number of thin (1X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + tlev2 = 2 // Number of thick (2X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + grnd = -1 // Indicator for grounding scheme under line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* // -1 = BFMOAT (Default), -2 = N/A');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + dtemp = 0 // difference in temperature between line and

circuit (C)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* NOTES:'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 1. Length can vary continuously from 100um to 1500um');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 2. Width can vary continuously from 4um to 25um');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 3. Supported thin and thick metal combinations for "indline"

model:'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=2, tlev2=1'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=3, tlev2=1'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=4, tlev2=1'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=2, tlev2=2'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=3, tlev2=2'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

111

fwrite(new_golden_circuit_fid,'* 4. Indline element is always made up of an MA metal shape');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 5. If parameter "ind" is not passed in, the model will');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* calculate its value internally from the other parameters.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 6. Grounding scheme (grnd) assumes BFMOAT.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* T-LINE MODEL '); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* (C) 2004 T-LINE MODEL Corporation');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'simulator lang=spectre');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** indline circuit element difinition

**************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'.subckt indline ( in out gnd )');

fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'parameters'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** rfline default parameters

**********************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ l = 100e-6 $ length of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ w = 4e-6 $ width of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind = -1 $ inductance of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

112

fwrite(new_golden_circuit_fid,'* $ if ind==-1 then calculate self inductance internally');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ tlev1 = 3 $ Number of thin (1X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ tlev2 = 2 $ Number of thick (2X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ grnd = -1 $ Indicator for grounding scheme under line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* $ -1 = BFMOAT (Default), -2 = N/A');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ dtemp = 0 $ difference in temperature between line and

circuit (C)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'.param'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

%

% Begin writing spectre equations used to construct circuit model:

%

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate effective line width

*****************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ pw=' 39 'w+delma_f' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ pl=l']); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate the transmission line to substrate capacitance*');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ pheffa=' 39

'oppcsti_f+oppcthk_f+capct_f+m1t_f+m1m2t_f+m2t_f+mxmqt_f+mqt_f+mxlyt_f+lyt_f+lye1t_f+e1t

_f+e1mat_f' 39]); fwrite(new_golden_circuit_fid,10,'uchar');

113

fwrite(new_golden_circuit_fid,['+ pheffb=' 39

'(tlev1>=3)*(m2m3t_f+m3t_f)+(tlev1==4)*(m3m4t_f+m4t_f)+(tlev2==2)*(mqmgt_f+mgt_f)' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ pheff=' 39 'pheffa+pheffb' 39]');

fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'+

coxide=((pw/pheff)<0.6)*(1.74*e0*eoxdepo*((pw/pheff)+0.79115))+((pw/pheff)>=0.6)*e0*eoxdepo*((

pw/pheff)+2.42-0.44*(pheff/pw)+(1-pheff/pw)*(1-pheff/pw)* (1-pheff/pw)*(1-pheff/pw)*(1-

pheff/pw))'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ coxide=' 39

'((pw/pheff)<0.6)*(1.74*e0*eoxdepo*((pw/pheff)+0.79115))+\\' ]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,[' ' '((pw/pheff)>=0.6)*e0*eoxdepo*((pw/pheff)+2.42-

0.44*(pheff/pw)+(1-pheff/pw)**6)' 39]); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ cscaleox=' 39 '0.93+0.32*exp(-0.75*(pl/100e-6))+0.35*exp(-

0.10*pw/1e-6)' 39]); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ cloxide=' 39 'coxide*cscaleox*pl/9' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate capacitance and resistance from top to bottom of Si

substrate*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ cond_si=' 39 '1/rsub_f' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ cscalesub=' 39 '3/(pl/100e-6)' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ wsubc=' 39 'pw+2*pheff+mat_f' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ clsub=' 39 'pl*cscalesub*e0*ersi*(3*pw/pmsxt + 0.5*1.5823)/9'

39]); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ rscalesub=' 39 '(1.41 + 0.4*log(0.1*pl/100e-6)) + (0.024 +

0.006*log(0.1*pl/100e-6))*(pw/1e-6)' 39]); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ glsub=' 39 'cond_si*6*wsubc/pmsxt' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ rlsub=' 39 '9*rscalesub/(glsub*pl)' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

114

fwrite(new_golden_circuit_fid,['+ rlinetot=' 39 'mars_f/(pw)' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ rline=' 39 'rlinetot*pl/8' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate inductance of the line at DC and as f-->infinity

*************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ ind_h_inf=pheff']); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ ind_h_low=' 39 'pheff+pmsxt' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'+ ind_low=1e-

7*(log(1+(32*(ind_h_low/pw))*(32*(ind_h_low/pw))*(1+sqrt(1+(pi*pw/(8*ind_h_low))*(pi*pw/(8*in

d_h_low))))))'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ ind_low=' 39 '1e-

7*(log(1+(32*(ind_h_low/pw))*(32*(ind_h_low/pw))*\\' ]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,[' '

'(1+sqrt(1+(pi*pw/(8*ind_h_low))*(pi*pw/(8*ind_h_low))))))' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ ind_inf=' 39 '1e-

7*(log(1+(32*(ind_h_inf/pw))*(32*(ind_h_inf/pw))*\\' ]); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,[' '

'(1+sqrt(1+(pi*pw/(8*ind_h_inf))*(pi*pw/(8*ind_h_inf))))))' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ lscalefin=' 39 '0.75 + 0.03*log((pl/100e-6)**4-0.5) +

(0.05+0.017*log((pl/100e-6)-0.95))*log10(pw/1e-6)' 39]); fwrite(new_golden_circuit_fid,10,'uchar')

fwrite(new_golden_circuit_fid,['+ diff_ind=' 39 'lscalefin*(ind_low - ind_inf)*pl' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** if inductance value is passed in, scale final self and mutual');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* inductances appropriately');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ lscale=' 39 '(ind>0)*(ind-diff_ind)/(lscalefin*ind_inf*pl-

diff_ind)+(ind==-1)*1' 39]); fwrite(new_golden_circuit_fid,10,'uchar');

115

fwrite(new_golden_circuit_fid,['+ plfinal=' 39 'lscale*(lscalefin*ind_inf*pl-diff_ind)/8' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'***** calculate circuit element values for two R-L skin effect

networks****'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ dropf=' 39 '12.90-0.40*(pw/1e-6)' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ dllow=' 39 '0.08*exp(-0.35*((pw/1e-6)-4))+0.035' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ delta_l_a=' 39 'diff_ind/8' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ delta_r_a=' 39 '3162e9*delta_l_a' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ delta_l_b=' 39 'dllow*delta_l_a' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,['+ delta_r_b=' 39 '2*pi*dropf*1e9*delta_l_b' 39]);

fwrite(new_golden_circuit_fid,10,'uchar');

%+ wct = ((layerads==2)+(layerads==3)+(layerads==4))*w+\

% (layerads==5)*(w-2*(0.022u))+\

% (layerads==6)*(w-2*(-0.077u))+\

% (layerads==7)*(w-2*(-0.08u))

%low_drop_frequency=-0.395*line_width + 12.9;

%D_L_low_drop_scale_factor=0.08*exp(-0.35*(line_width-4))+0.035;

%fwrite(new_golden_circuit_fid,''); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,''); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,''); fwrite(new_golden_circuit_fid,10,'uchar');

%fclose(new_golden_circuit_fid);

%beginning_contact_file(SiGe_process,metal_layer_count,line_metal,line_length,line_width,target_

frequency,circuit_fid,file_name_sub,number_of_contacts);

%sub_circuit_file_contact_case_a(number_of_line_sections,C_oxide_a,C_sub_a,G_sub_a,R_line_a,

delta_r_a,L_line_a,delta_l_a,circuit_fid,file_name_sub,number_of_skin_sections,sub_con_r_a,sub_c

on_c_a,r_contact);

116

%ending_contact_file(SiGe_process,metal_layer_count,line_metal,line_length,line_width,target_fre

quency,circuit_fid,file_name_sub,number_of_contacts,contact_voltage);

B.4 create_golden_rfline_model_a.m

function z=create_golden_rfline_model_a(new_golden_circuit_fid),

fwrite(new_golden_circuit_fid,'* Path, Component, Release: %W%');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* CMVC Revision: %I% %E% %U%');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*> T-LINE MODEL 7HP "indline" Analog Metal (MA) Line over

BFMOAT'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* Indline model for MA line over BFMOAT');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* The indline model contains:');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 1. Eight R-L-C networks connected in series representing');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* the variation in inductance, capacitance, and resistance with

frequency'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* Example of one of such a block is shown below.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 2. Nine oxide capacitances (c_ox_1, c_ox_2, ..., c_ox_last)

representing the capacitance'); fwrite(new_golden_circuit_fid,10,'uchar');

117

fwrite(new_golden_circuit_fid,'* between the analog metal line and the substrate.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 3. Nine substrate capacitances (c_sub_1, c_sub_2, ..., c_sub_last)

and resistances'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* (r_sub_1, r_sub_2, ..., r_sub_last) representing the effect of the

loss in the'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* conductive silicon substrate.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* r_skin_11 r_skin_12 ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* /\/\/\/\ /\/\/\/\ ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* in r_line_1 l_line_1 | | | | out');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* o---+---/\/\/\/\------()()()()--------| |-----| |----+----o - - - - - - o ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | ()()()() ()()()() | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | l_skin_11 l_skin_12 | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* ----- ----- ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* ----- c_ox_1 c_ox_2----- ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

118

fwrite(new_golden_circuit_fid,'* +-------------+ +-------------+ ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* / | / | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* \ r_sub_1 ----- c_sub_1 \ r_sub_2 ----- c_sub_2

'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* / ----- / ----- ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* \ | \ | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* o----+-------------+------------------------------+-------------+----o - - - - - -

o '); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* gnd (substrate/groundplane)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* SYNTAX:'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* x1 in out gnd indline'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + l = 100e-6 // length of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + w = 4e-6 // width of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + ind = -1 // inductance of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* // if ind==-1 then calculate self inductance internally');

fwrite(new_golden_circuit_fid,10,'uchar');

119

fwrite(new_golden_circuit_fid,'* + tlev1 = 3 // Number of thin (1X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + tlev2 = 2 // Number of thick (2X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + grnd = -1 // Indicator for grounding scheme under line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* // -1 = BFMOAT (Default), -2 = N/A');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + dtemp = 0 // difference in temperature between line and

circuit (C)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* NOTES:'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 1. Length can vary continuously from 100um to 1500um');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 2. Width can vary continuously from 4um to 25um');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 3. Supported thin and thick metal combinations for "indline"

model:'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=2, tlev2=1'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=3, tlev2=1'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=4, tlev2=1'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=2, tlev2=2'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=3, tlev2=2'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 4. Indline element is always made up of an MA metal shape');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 5. If parameter "ind" is not passed in, the model will');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* calculate its value internally from the other parameters.');

fwrite(new_golden_circuit_fid,10,'uchar');

120

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 6. Grounding scheme (grnd) assumes BFMOAT.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* T-LINE MODEL '); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* (C) 2004 T-LINE MODEL Corporation');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'simulator lang=spectre'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** indline circuit element difinition

**************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'inline subckt indline ( in out gnd )');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'parameters'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** rfline default parameters

**********************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ l = 100e-6 // length of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ w = 4e-6 // width of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind = -1 // inductance of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* // if ind==-1 then calculate self inductance internally');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ tlev1 = 3 // Number of thin (1X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ tlev2 = 2 // Number of thick (2X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ grnd = -1 // Indicator for grounding scheme under line');

fwrite(new_golden_circuit_fid,10,'uchar');

121

fwrite(new_golden_circuit_fid,'* // -1 = BFMOAT (Default), -2 = N/A');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ dtemp = 0 // difference in temperature between line and

circuit (C)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

%

% Begin writing spectre equations used to construct circuit model:

%

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate effective line width

*****************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ pw=w+delma_f'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ pl=l'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate the transmission line to substrate capacitance*');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+

pheffa=oppcsti_f+oppcthk_f+capct_f+m1t_f+m1m2t_f+m2t_f+mxmqt_f+mqt_f+mxlyt_f+lyt_f+lye1

t_f+e1t_f+e1mat_f'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+

pheffb=(tlev1>=3)*(m2m3t_f+m3t_f)+(tlev1==4)*(m3m4t_f+m4t_f)+(tlev2==2)*(mqmgt_f+mgt_f)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ pheff=pheffa+pheffb'); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'+

coxide=((pw/pheff)<0.6)*(1.74*e0*eoxdepo*((pw/pheff)+0.79115))+((pw/pheff)>=0.6)*e0*eoxdepo*((

pw/pheff)+2.42-0.44*(pheff/pw)+(1-pheff/pw)*(1-pheff/pw)* (1-pheff/pw)*(1-pheff/pw)*(1-

pheff/pw))'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+

coxide=((pw/pheff)<0.6)*(1.74*e0*eoxdepo*((pw/pheff)+0.79115))+\');

fwrite(new_golden_circuit_fid,10,'uchar');

122

fwrite(new_golden_circuit_fid,' ((pw/pheff)>=0.6)*e0*eoxdepo*((pw/pheff)+2.42-

0.44*(pheff/pw)+(1-pheff/pw)**6)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ cscaleox=0.93+0.32*exp(-0.75*(pl/100e-6))+0.35*exp(-0.10*pw/1e-

6)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ cloxide=coxide*cscaleox*pl/9');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate capacitance and resistance from top to bottom of Si

substrate*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ cond_si=1/rsub_f'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ cscalesub=3/(pl/100e-6)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ wsubc=pw+2*pheff+mat_f');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ clsub=pl*cscalesub*e0*ersi*(3*pw/pmsxt + 0.5*1.5823)/9');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ rscalesub=(1.41 + 0.4*log(0.1*pl/100e-6)) + (0.024 +

0.006*log(0.1*pl/100e-6))*(pw/1e-6)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ glsub=cond_si*6*wsubc/pmsxt');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ rlsub=9*rscalesub/(glsub*pl)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ rlinetot=mars_f/(pw)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ rline=rlinetot*pl/8'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate inductance of the line at DC and as f-->infinity

*************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind_h_inf=pheff'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind_h_low=pheff+pmsxt');

fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'+ ind_low=1e-

7*(log(1+(32*(ind_h_low/pw))*(32*(ind_h_low/pw))*(1+sqrt(1+(pi*pw/(8*ind_h_low))*(pi*pw/(8*in

d_h_low))))))'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind_low=1e-

7*(log(1+(32*(ind_h_low/pw))*(32*(ind_h_low/pw))*\'); fwrite(new_golden_circuit_fid,10,'uchar');

123

fwrite(new_golden_circuit_fid,' (1+sqrt(1+(pi*pw/(8*ind_h_low))*(pi*pw/(8*ind_h_low))))))');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind_inf=1e-7*(log(1+(32*(ind_h_inf/pw))*(32*(ind_h_inf/pw))*\');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,' (1+sqrt(1+(pi*pw/(8*ind_h_inf))*(pi*pw/(8*ind_h_inf))))))');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ lscalefin=0.75 + 0.03*log((pl/100e-6)**4-0.5) +

(0.05+0.017*log((pl/100e-6)-0.95))*log10(pw/1e-6)'); fwrite(new_golden_circuit_fid,10,'uchar')

fwrite(new_golden_circuit_fid,'+ diff_ind=lscalefin*(ind_low - ind_inf)*pl');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** if inductance value is passed in, scale final self and mutual');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* inductances appropriately');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ lscale=(ind>0)*(ind-diff_ind)/(lscalefin*ind_inf*pl-

diff_ind)+(ind==-1)*1'); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'+ lscale=(ind>0)*ind/(lscalefin*ind_inf*pl-diff_ind)+(ind==-

1)*1'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ plfinal=lscale*(lscalefin*ind_inf*pl-diff_ind)/8');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'***** calculate circuit element values for two R-L skin effect

networks****'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ dropf=12.90-0.40*(pw/1e-6)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ dllow=0.08*exp(-0.35*((pw/1e-6)-4))+0.035');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ delta_l_a=diff_ind/8'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ delta_r_a=3162e9*delta_l_a');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ delta_l_b=dllow*delta_l_a');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ delta_r_b=2*pi*dropf*1e9*delta_l_b');

fwrite(new_golden_circuit_fid,10,'uchar');

124

%+ wct = ((layerads==2)+(layerads==3)+(layerads==4))*w+\

% (layerads==5)*(w-2*(0.022u))+\

% (layerads==6)*(w-2*(-0.077u))+\

% (layerads==7)*(w-2*(-0.08u))

%low_drop_frequency=-0.395*line_width + 12.9;

%D_L_low_drop_scale_factor=0.08*exp(-0.35*(line_width-4))+0.035;

%fwrite(new_golden_circuit_fid,''); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,''); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,''); fwrite(new_golden_circuit_fid,10,'uchar');

%fclose(new_golden_circuit_fid);

%beginning_contact_file(SiGe_process,metal_layer_count,line_metal,line_length,line_width,target_

frequency,circuit_fid,file_name_sub,number_of_contacts);

%sub_circuit_file_contact_case_a(number_of_line_sections,C_oxide_a,C_sub_a,G_sub_a,R_line_a,

delta_r_a,L_line_a,delta_l_a,circuit_fid,file_name_sub,number_of_skin_sections,sub_con_r_a,sub_c

on_c_a,r_contact);

%ending_contact_file(SiGe_process,metal_layer_count,line_metal,line_length,line_width,target_fre

quency,circuit_fid,file_name_sub,number_of_contacts,contact_voltage);

B.5 create_golden_rfline_model_lm_a.m

function z=create_golden_rfline_model_lm_a(new_golden_circuit_fid),

fwrite(new_golden_circuit_fid,'* Path, Component, Release: %W%');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* CMVC Revision: %I% %E% %U%');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*> T-LINE MODEL 7HP "indline" 2-2X parallel stacked LM||MQ

line over BFMOAT'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* or LM||MG');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

125

fwrite(new_golden_circuit_fid,'* Indline model for 2-2X parallel stacked LM||MQ line over

BFMOAT'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* or LM||MG');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* The indline model contains:');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 1. Eight R-L-C networks connected in series representing');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* the variation in inductance, capacitance, and resistance with

frequency'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* Example of one of such a block is shown below.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 2. Nine oxide capacitances (c_ox_1, c_ox_2, ..., c_ox_last)

representing the capacitance'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* between the analog metal line and the substrate.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 3. Nine substrate capacitances (c_sub_1, c_sub_2, ..., c_sub_last)

and resistances'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* (r_sub_1, r_sub_2, ..., r_sub_last) representing the effect of the

loss in the'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* conductive silicon substrate.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* r_skin_11 r_skin_12 ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* /\/\/\/\ /\/\/\/\ ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* in r_line_1 l_line_1 | | | | out');

fwrite(new_golden_circuit_fid,10,'uchar');

126

fwrite(new_golden_circuit_fid,'* o---+---/\/\/\/\------()()()()--------| |-----| |----+----o - - - - - - o ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | ()()()() ()()()() | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | l_skin_11 l_skin_12 | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* ----- ----- ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* ----- c_ox_1 c_ox_2----- ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* +-------------+ +-------------+ ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* / | / | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* \ r_sub_1 ----- c_sub_1 \ r_sub_2 ----- c_sub_2

'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* / ----- / ----- ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* \ | \ | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

127

fwrite(new_golden_circuit_fid,'* | | | | ');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* o----+-------------+------------------------------+-------------+----o - - - - - -

o '); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* gnd (substrate/groundplane)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* SYNTAX:'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* x1 in out gnd indline'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + l = 100e-6 // length of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + w = 4e-6 // width of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + ind = -1 // inductance of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* // if ind==-1 then calculate self inductance internally');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + tlev1 = 3 // Number of thin (1X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + tlev2 = 2 // Number of thick (2X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + grnd = -1 // Indicator for grounding scheme under line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* // -1 = BFMOAT (Default), -2 = N/A');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* + dtemp = 0 // difference in temperature between line and

circuit (C)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* NOTES:'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

128

fwrite(new_golden_circuit_fid,'* 1. Length can vary continuously from 100um to 1500um');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 2. Width can vary continuously from 4um to 25um');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 3. Supported thin and thick metal combinations for "indline"

model:'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=3, tlev2=2'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=4, tlev2=2'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=5, tlev2=2'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=6, tlev2=2'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=4, tlev2=3'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* tlev1=5, tlev2=3'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 4. Indline element is always made up of a parallel combination of

the two'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* topmost 2X Cu levels. Three 2X levels in parallel is not

allowed.'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 5. If parameter "ind" is not passed in, the model will');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* calculate its value internally from the other parameters.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* 6. Grounding scheme (grnd) assumes BFMOAT.');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* T-LINE MODEL '); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* (C) 2004 T-LINE MODEL Corporation');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'simulator lang=spectre'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

129

fwrite(new_golden_circuit_fid,'** indline circuit element difinition

**************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'inline subckt indline ( in out gnd )');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'parameters'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** rfline default parameters

**********************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ l = 100e-6 // length of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ w = 4e-6 // width of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind = -1 // inductance of the line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* // if ind==-1 then calculate self inductance internally');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ tlev1 = 3 // Number of thin (1X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ tlev2 = 2 // Number of thick (2X) metal levels');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ grnd = -1 // Indicator for grounding scheme under line');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* // -1 = BFMOAT (Default), -2 = N/A');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ dtemp = 0 // difference in temperature between line and

circuit (C)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'**********************************************************

*****************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

%

% Begin writing spectre equations used to construct circuit model:

%

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

130

fwrite(new_golden_circuit_fid,'** calculate effective line width

*****************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ pw=w+delma_f'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ pl=l'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate effective line thickness

*************************************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+

pt=(tlev2==2)*(lmt_f+mqlmt_f+mqt_f)+(tlev2==3)*(lmt_f+mglmt_f+mgt_f)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate the transmission line to substrate capacitance*');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+

pheffa=oppcsti_f+oppcthk_f+capct_f+m1t_f+m1m2t_f+m2t_f+m2m3t_f+m3t_f+mxmqt_f');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+

pheffb=(tlev1>=4)*(m3m4t_f+m4t_f)+(tlev1>=5)*(m4m5t_f+m5t_f)+(tlev1==6)*(m5m6t_f+m6t_f)+(

tlev2==3)*(mqt_f+mqmgt_f)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ pheff=pheffa+pheffb'); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'+

coxide=((pw/pheff)<0.6)*(1.74*e0*eoxdepo*((pw/pheff)+0.79115))+((pw/pheff)>=0.6)*e0*eoxdepo*((

pw/pheff)+2.42-0.44*(pheff/pw)+(1-pheff/pw)*(1-pheff/pw)* (1-pheff/pw)*(1-pheff/pw)*(1-

pheff/pw))'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+

coxide=((pw/pheff)<0.6)*(1.74*e0*eoxdepo*((pw/pheff)+0.79115))+\');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,' ((pw/pheff)>=0.6)*e0*eoxdepo*((pw/pheff)+2.42-

0.44*(pheff/pw)+(1-pheff/pw)**6)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ cscaleox=0.93+0.32*exp(-0.75*(pl/100e-6))+0.35*exp(-0.10*pw/1e-

6)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ cloxide=coxide*cscaleox*pl/9');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

131

fwrite(new_golden_circuit_fid,'** calculate capacitance and resistance from top to bottom of Si

substrate*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ cond_si=1/rsub_f'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ cscalesub=3/(pl/100e-6)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ wsubc=pw+2*pheff+mat_f');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ clsub=pl*cscalesub*e0*ersi*(3*pw/pmsxt + 0.5*1.5823)/9');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ rscalesub=(1.41 + 0.4*log(0.1*pl/100e-6)) + (0.024 +

0.006*log(0.1*pl/100e-6))*(pw/1e-6)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ glsub=cond_si*6*wsubc/pmsxt');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ rlsub=9*rscalesub/(glsub*pl)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ rlinetot=mars_f/(pw)'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ rline=rlinetot*pl/8'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** calculate inductance of the line at DC and as f-->infinity

*************'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind_h_inf=pheff'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind_h_low=pheff+pmsxt');

fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'+ ind_low=1e-

7*(log(1+(32*(ind_h_low/pw))*(32*(ind_h_low/pw))*(1+sqrt(1+(pi*pw/(8*ind_h_low))*(pi*pw/(8*in

d_h_low))))))'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind_low=1e-

7*(log(1+(32*(ind_h_low/pw))*(32*(ind_h_low/pw))*\'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,' (1+sqrt(1+(pi*pw/(8*ind_h_low))*(pi*pw/(8*ind_h_low))))))');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ ind_inf=1e-7*(log(1+(32*(ind_h_inf/pw))*(32*(ind_h_inf/pw))*\');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,' (1+sqrt(1+(pi*pw/(8*ind_h_inf))*(pi*pw/(8*ind_h_inf))))))');

fwrite(new_golden_circuit_fid,10,'uchar');

132

fwrite(new_golden_circuit_fid,'+ lscalefin=0.75 + 0.03*log((pl/100e-6)**4-0.5) +

(0.05+0.017*log((pl/100e-6)-0.95))*log10(pw/1e-6)'); fwrite(new_golden_circuit_fid,10,'uchar')

fwrite(new_golden_circuit_fid,'+ diff_ind=lscalefin*(ind_low - ind_inf)*pl');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'** if inductance value is passed in, scale final self and mutual');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'* inductances appropriately');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ lscale=(ind>0)*(ind-diff_ind)/(lscalefin*ind_inf*pl-

diff_ind)+(ind==-1)*1'); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,'+ lscale=(ind>0)*ind/(lscalefin*ind_inf*pl-diff_ind)+(ind==-

1)*1'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ plfinal=lscale*(lscalefin*ind_inf*pl-diff_ind)/8');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'***** calculate circuit element values for two R-L skin effect

networks****'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'*'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ dropf=12.90-0.40*(pw/1e-6)');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ dllow=0.08*exp(-0.35*((pw/1e-6)-4))+0.035');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ delta_l_a=diff_ind/8'); fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ delta_r_a=3162e9*delta_l_a');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ delta_l_b=dllow*delta_l_a');

fwrite(new_golden_circuit_fid,10,'uchar');

fwrite(new_golden_circuit_fid,'+ delta_r_b=2*pi*dropf*1e9*delta_l_b');

fwrite(new_golden_circuit_fid,10,'uchar');

%+ wct = ((layerads==2)+(layerads==3)+(layerads==4))*w+\

% (layerads==5)*(w-2*(0.022u))+\

% (layerads==6)*(w-2*(-0.077u))+\

% (layerads==7)*(w-2*(-0.08u))

133

%low_drop_frequency=-0.395*line_width + 12.9;

%D_L_low_drop_scale_factor=0.08*exp(-0.35*(line_width-4))+0.035;

%fwrite(new_golden_circuit_fid,''); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,''); fwrite(new_golden_circuit_fid,10,'uchar');

%fwrite(new_golden_circuit_fid,''); fwrite(new_golden_circuit_fid,10,'uchar');

%fclose(new_golden_circuit_fid);

%beginning_contact_file(SiGe_process,metal_layer_count,line_metal,line_length,line_width,target_

frequency,circuit_fid,file_name_sub,number_of_contacts);

%sub_circuit_file_contact_case_a(number_of_line_sections,C_oxide_a,C_sub_a,G_sub_a,R_line_a,

delta_r_a,L_line_a,delta_l_a,circuit_fid,file_name_sub,number_of_skin_sections,sub_con_r_a,sub_c

on_c_a,r_contact);

%ending_contact_file(SiGe_process,metal_layer_count,line_metal,line_length,line_width,target_fre

quency,circuit_fid,file_name_sub,number_of_contacts,contact_voltage);

B.6 gnd_back_high_freq_network.m

function

z=gnd_back_high_freq_network(line_length,line_width,oxide,line_metal,x_offset,y_offset,number_o

f_line_sections,number_of_skin_sections),

delta_x=line_length/number_of_line_sections;

horizontal_connection_offset=0.2*line_width;

colors=['r' 'g' 'b' 'm' 'c' 'y' 'r' 'g' 'b' 'm' 'c' 'y'];

for i=1:number_of_line_sections,

vertical_capacitor_symbol(x_offset + (i-1)*delta_x,y_offset,oxide(line_metal),oxide(line_metal),0.2

*line_width,colors(line_metal));

plot3([x_offset+(i-1)*delta_x x_offset+(i-1)*delta_x],[y_offset+horizontal_connection_offset y_offset-

horizontal_connection_offset],[0 0],'k');

plot3([x_offset+(i-1)*delta_x x_offset+(i-1)*delta_x],[y_offset+horizontal_connection_offset y_offset-

horizontal_connection_offset],[-oxide(line_metal) -oxide(line_metal)],'k');

vertical_capacitor_symbol(x_offset + (i-

1)*delta_x,y_offset+horizontal_connection_offset,0,oxide(line_metal),0.2*line_width,'k');

vertical_resistor_symbol(x_offset + (i-1)*delta_x,y_offset-

horizontal_connection_offset,0,oxide(line_metal),0.2*line_width,'k');

134

vertical_ground_symbol(x_offset + (i-1)*delta_x,0,-

oxide(line_metal),0.2*oxide(line_metal),0.2*line_width,'k');

line_resistor_symbol(x_offset + (i-

1)*delta_x,0,oxide(line_metal),delta_x/4,0.4*line_width,colors(line_metal));

line_inductor_symbol(x_offset + (i-

1)*delta_x+delta_x/4,0,oxide(line_metal),delta_x/4,0.4*line_width,colors(line_metal));

for ii=1:number_of_skin_sections,

plot3([x_offset + (i-1)*delta_x + delta_x/2 + (ii-1)*delta_x/(2*number_of_skin_sections) x_offset +

(i-1)*delta_x+ delta_x/2 + (ii-1)*delta_x/(2*number_of_skin_sections)],[y_offset+0.3*line_width

y_offset-0.3*line_width],[oxide(line_metal) oxide(line_metal)],'k');

plot3([x_offset+ (i-1)*delta_x+delta_x/2+(ii-

1)*delta_x/(2*number_of_skin_sections)+delta_x/(2*number_of_skin_sections+1) x_offset+ (i-

1)*delta_x+delta_x/2+(ii-

1)*delta_x/(2*number_of_skin_sections)+delta_x/(2*number_of_skin_sections+1)],[y_offset+0.3*lin

e_width y_offset-0.3*line_width],[oxide(line_metal) oxide(line_metal)],'k');

plot3([x_offset+(i-1)*delta_x+ (ii-

1)*delta_x/(2*number_of_skin_sections)+delta_x/2+delta_x/(2*number_of_skin_sections+1)

x_offset+(i-1)*delta_x+ (ii-

1)*delta_x/(2*number_of_skin_sections)+delta_x/2+delta_x/(2*number_of_skin_sections)],[y_offset

y_offset],[oxide(line_metal) oxide(line_metal)],'k');

line_resistor_symbol(x_offset + (i-1)*delta_x + delta_x/2 + (ii-

1)*delta_x/(2*number_of_skin_sections),y_offset +

0.3*line_width,oxide(line_metal),delta_x/(2*number_of_skin_sections+1),0.3*line_width,'k');

line_inductor_symbol(x_offset + (i-1)*delta_x + delta_x/2 + (ii-

1)*delta_x/(2*number_of_skin_sections),y_offset -

0.3*line_width,oxide(line_metal),delta_x/(2*number_of_skin_sections+1),0.3*line_width,'k');

end; % for-ii

end; % for-i

vertical_capacitor_symbol(x_offset +

line_length,y_offset,oxide(line_metal),oxide(line_metal),0.2*line_width,colors(line_metal));

plot3([x_offset+line_length x_offset+line_length],[y_offset+horizontal_connection_offset y_offset-

horizontal_connection_offset],[0 0],'k');

135

plot3([x_offset+line_length x_offset+line_length],[y_offset+horizontal_connection_offset y_offset-

horizontal_connection_offset],[-oxide(line_metal) -oxide(line_metal)],'k');

vertical_capacitor_symbol(x_offset +

line_length,y_offset+horizontal_connection_offset,0,oxide(line_metal),0.2*line_width,'k');

vertical_resistor_symbol(x_offset + line_length,y_offset-

horizontal_connection_offset,0,oxide(line_metal),0.2*line_width,'k');

vertical_ground_symbol(x_offset + line_length,0,-

oxide(line_metal),0.2*oxide(line_metal),0.2*line_width,'k');

B.7 read_zgb_param.m

function [ frq, zabs, zphs, alpha, betta ] = read_zgb_param( filename, lng );

[ sp, freq, type, z0 ] = gettouch( filename, 's' );

ztmp = sqrt( ( ( 1.0 + sp(:,1) ).^2 - sp(:,2).^2 ) ./ ( ( 1.0 - sp(:,1) ).^2 - sp(:,2).^2 ) ) * 50.0;

frq = freq;

zabs = abs( ztmp );

zphs = unwrap( angle( ztmp ) ) * 180.0 / pi;

gamma = log( ( 1.0 - sp(:,1).^2 + sp(:,2).^2 + sqrt( ( sp(:,1).^2 - sp(:,2).^2 + 1.0 ).^2 - ( 2.0 .* sp(:,1)

).^2 ) ) ./ ( 2.0 .* sp(:,2) ) ) ./ lng;

alpha = real( gamma(:) );

betta = unwrap( imag( gamma ) * lng ) / lng;

B.8 single_current_voltage.m

function

[I,V,z_horizontal,z_vertical,z_line_a]=single_current_voltage(C_oxide_a,C_sub_a,G_sub_a,R_line_

a,L_line_a,s,number_of_line_sections,load_impedance,source_impedance),

% Calculate horizontal and vertical impedance sections:

for i=1:number_of_line_sections,

z_vertical(i,:)=(1./(s.*C_oxide_a(i))) + parallel_impedance(G_sub_a(i),(1./(s.*C_sub_a(i))));

z_horizontal(i,:)=R_line_a(i) + s.*L_line_a(i);

136

end; % for-i

% Calculate impedance at nodes along interconnect line:

% /******calculate look-in impedance of last circuit section (with load impedance)******/

for i=1:length(z_vertical(1,:)),

z_line_a(1,i)=parallel_impedance( z_vertical(1,i) , load_impedance );

end; % for-i

% /******calculate look-in impedance of other circuit sections (with load impedance)******/

for i=2:number_of_line_sections,

for j=1:length(z_line_a(1,:)),

z_line_a(i,j)=parallel_impedance(z_vertical(i,j),(z_horizontal(i-1,j) + z_line_a(i-1,j)));

end; % for-j

end; % for-i

% /////******calculate currents and voltages at nodes along interconnect line

length************/////

% /*****calculate total current flowing into the circuit*****/

Vo=1; % Source voltage [V]

I_a_total(number_of_line_sections,:)=Vo./(z_line_a(number_of_line_sections,:) + source_impedance

+ z_horizontal(number_of_line_sections));

I(1,:)=I_a_total(number_of_line_sections,:); % Input current [A]

V(1,:)=Vo-I(1,:).*source_impedance;

% /*****calculate currents in other circuit legs*****/

for i=number_of_line_sections:-1:2,

I_vertical_a(i,:) = I_a_total(i,:)./(1 + z_vertical(i,:)./(z_horizontal(i-1,:) + z_line_a(i-1,:)));

V_a(i,:)=z_vertical(i,:).*I_vertical_a(i,:);

I_a_total(i-1,:)=I_a_total(i,:) - I_vertical_a(i,:);

end; % for-i

% /*****calculate last current leg and output current*****/

I_vertical_a(1,:)=I_a_total(1,:)./(1 + z_vertical(1,:)./load_impedance);

I(2,:)=I_a_total(1,:)-I_vertical_a(1,:);

V_a(1,:)=z_vertical(1,:).*I_vertical_a(1,:);

V(2,:)=V_a(1,:);

137

B.9 sparam_db_phase.m

function [ s11db, s11ph, s21db, s21ph ] = sparam_db_phase( sp );

s11db = 20.0 * log10( abs( sp( :, 1 ) ) );

s11ph = unwrap( angle( sp( :, 1 ) ) ) * 180.0 / pi;

s21db = 20.0 * log10( abs( sp( :, 3 ) ) );

s21ph = unwrap( angle( sp( :, 3 ) ) ) * 180.0 / pi;

B.10 stoindq.m

function [ind,qf,qr,ind1p]=stoindq(sInd,freq)

% Compute inductance and quality factor given sInd s-parameters acquired at freq (in Hz)

frequencies

%[ind,qf,qr,ind1p]=stoindq(sInd,freq)

w=2*pi*freq; %Hz

yInd=stoy(sInd);

ind=(-1./w.*imag(1./yInd(:,2)));

ind1p=imag(1./yInd(:,1))./w;

qf=-imag(yInd(:,1))./real(yInd(:,1));

qr=-imag(yInd(:,4))./real(yInd(:,4));

B.11 tline_RLC.m

e0 = 8.85e-12;

eV = 4.36;

eH = 4.49;

t = 0.36e-6; % thickness

h = 1.67e-6; % height

w = 2e-6; % width

length = 40e-6;

s = 6e-6; % space

effw = (1.68+0.8*(w*1e6-1.68))*1e-6; % 1.68<w<35

rs = 0.07;

r0 = rs/(effw*1e6); % ohm/um

Kf = 0.72*h/w+1;

l0 = 1.6*h/w/Kf; % nH/mm

138

cm1 = 1.31*(t/h)^0.073*(s/h+1.38)^(-2.22);

cm2 = 0.4*log(1+5.46*w/s)*(s/h+1.12)^(-0.81);

cm = e0*eV*(t/s+cm1+cm2);

cH = 2*cm;

cV = e0*eH*(effw/h+0.77+1.06*sqrt(sqrt(effw/h))+1.06*sqrt(t/h));

c0 = length*(cH+cV);

r1 = r0*length*1e6; % ohm

l1 = l0*length*1e3; % nH

c1 = c0*1e15; % fF

c2 = c1/2;

%v = 3e8;

%l2 = 1e9/(c0*v*v);

B.12 tlinerlcg.m

function [ r, l, c, g, z, gm ] = tlinerlcg( fr, s, lng );

z = sqrt( ( ( 1.0 + s(:,1).^1 ).^2 - s(:,2).^2 ) ./...

( ( 1.0 - s(:,1) ).^2 - s(:,2).^2 ) ) * 50.0;

gm = log( ( 1.0 - s(:,1).^2 + s(:,2).^2 +...

sqrt( ( s(:,1).^2 - s(:,2).^2 + 1.0 ).^2 - ( 2.0 .* s(:,1) ).^2 ) ) ./( 2.0 .* s(:,2) ) ) ./ lng;

%gm = log( ( 1.0 - s(:,1).^2 + s(:,2).^2 + 1* sqrt( ( s(:,1).^2 - s(:,2).^2 + 1.0 ).^2 - ( 2.0 .* s(:,1) ).^2 )

)./( 2.*s(:,2) ) )./lng;

r = real( gm(:) .* z(:) );

l = imag( gm(:) .* z(:) ) ./ ( 2.0 .* pi .* fr(:) );

c = imag( gm(:) ./ z(:) ) ./ ( 2.0 .* pi .* fr(:) );

g = imag( gm(:) ./ z(:) );

B.13 tlinerlcg_total.m

function [ r, l, c, g, z, gm ] = tlinerlcg_total( fr, s, lng );

z = sqrt( ( ( 1.0 + s(:,1) ).^2 - s(:,2).^2 ) ./...

( ( 1.0 - s(:,1) ).^2 - s(:,2).^2 ) ) * 50.0;

gm = log( ( 1.0 - s(:,1).^2 + s(:,2).^2 +...

sqrt( ( s(:,1).^2 - s(:,2).^2 + 1.0 ).^2 - ( 2.0 .* s(:,1) ).^2 ) ) ./ ( 2.0 .* s(:,2) ) ) ./ lng;

139

r = real( gm(:) .* z(:) ) * lng;

l = imag( gm(:) .* z(:) ) ./ ( 2.0 .* pi .* fr(:) ) * lng;

c = imag( gm(:) ./ z(:) ) ./ ( 2.0 .* pi .* fr(:) ) * lng;

g = imag( gm(:) ./ z(:) ) * lng;

B.14 s2rlgc.m

if test_ads_fid~=-1, % If an ads results file exists for this line case.

[spars_ads, freq_ads, type_ads, z0_ads] = gettouch(long_ads_file_name, 's' );

end; % if-then

%/******** tlinerlcg ************************/

freq_spectre = 1;

frl_spectre = freq_spectre * 1.0e9;

[ r_spectre, l_spectre, c_spectre, g_spectre, z_spectre, gm_spectre ] = tlinerlcg_total( frl_spectre,

spars_spectre, line_length*1e-6 );

s11_spectre = spars_spectre(:,1);

s12_spectre = spars_spectre(:,2);

s21_spectre = spars_spectre(:,3);

s22_spectre = spars_spectre(:,4);

s11_spectre_db = 20.0 * log10( abs( s11_spectre ) );

s11_spectre_ph = angle( s11_spectre ) * 180.0 / pi;

%s11_spectre_ph = unwrap( s11_spectre_ph );

s21_spectre_db = 20.0 * log10( abs( s21_spectre ) );

%s21_spectre_ph = angle( s21_spectre ) * 180.0 / pi;

%s21_spectre_ph = unwrap( s21_spectre_ph );

s21_spectre_ph = unwrap(angle( s21_spectre )) * 180.0 / pi;

140

Appendix C

Perl Program to do signal net electromigration and Joul-heating check.

C. 1 Program to check #!/bin/bsh -- #perl eval '\ if [ "X$CTEPERLBIN" = "X" ] ; then echo "$0: CTE environment is not initialized! Exiting ..." exit 1 else exec $CTEPERLBIN -S $0 $1+"$@" fi' if 0; require "dotsh.pl"; &dotsh ($ENV"CTERC", 'CTEQUIET=1'); system "ulimit -Sd unlimited"; system "ulimit -Ss unlimited"; $rmin=1e-09; $rmax=1e+09; if(!defined $ARGV[0] || !defined $ARGV[1] || !defined $ARGV[2] || !defined $ARGV[3] || !defined $ARGV[4]) print "\nERROR Missing In Put Parms\n"; print "USAGE: beol.pl rootcell rootcell.EXTRACT.astap net(v/g) rundir emPrjFile. \n\n"; exit 0; ################################################################################ $progname = 'beol.toppins.8ML.pl'; #Parm 0 -> cell name #Parm 1 -> Erie *.EXTRACT.astap file #Parm 2 -> NET (v | g) #Parm 3 -> Netlist Directory #Parm 4 -> EM Project File #Parm 5 -> VIA Check -vwt ################################################################################ $sectname = $ARGV[0]; $astap = $ARGV[1]; $net = $ARGV[2]; $rd = $ARGV[3]; $emprj = $ARGV[4]; $vw=$ARGV[5]; $outastap = "$rd/$sectname.asx"; %pat=(); %WL=(); $lg="$rd/net.summary.log"; $o="out"; $src_type="ALL_TOP_WIRE_NODES"; open(PRJ,"<$emprj") || die "*ERROR* Program $progname can not open input file $emprj.\n"; while(<PRJ>) @prjL=split;

141

if(/^SRC_TYPE/) @buf=split; $src_type=$buf[1]; if(/^TECH_SCALE/) @buf=split; $scale=$buf[1]; if(/^NUMBER_METAL_LEVELS/) @buf=split; $metal_levels=$buf[1]; if(/^NUMBER_VIA_LEVELS/) @buf=split; $via_levels=$buf[1]; if(/^M1/) @buf=split; $M1=$buf[1].$o; $m1bias=$buf[2]; $m1min=$buf[3]; $m1K=$buf[4]; $m1B=$buf[5]; if(/^M2/) @buf=split; $M2=$buf[1].$o; $m2bias=$buf[2]; $m2min=$buf[3]; $m2K=$buf[4]; $m2B=$buf[5]; if(/^M3/) @buf=split; $M3=$buf[1].$o; $m3bias=$buf[2]; $m3min=$buf[3]; $m3K=$buf[4]; $m3B=$buf[5]; if(/^M4/) @buf=split; $M4=$buf[1].$o; $m4bias=$buf[2]; $m4min=$buf[3]; $m4K=$buf[4]; $m4B=$buf[5]; if(/^M5/) @buf=split; $M5=$buf[1].$o; $m5bias=$buf[2]; $m5min=$buf[3]; $m5K=$buf[4]; $m5B=$buf[5];

142

if(/^M6/) @buf=split; $M6=$buf[1].$o; $m6bias=$buf[2]; $m6min=$buf[3]; $m6K=$buf[4]; $m6B=$buf[5]; if(/^M7/) @buf=split; $M7=$buf[1].$o; $m7bias=$buf[2]; $m7min=$buf[3]; $m7K=$buf[4]; $m7B=$buf[5]; if(/^M8/) @buf=split; $M8=$buf[1].$o; $m8bias=$buf[2]; $m8min=$buf[3]; $m8K=$buf[4]; $m8B=$buf[5]; if(/^V1/) @buf=split; $V1=$buf[1]; $v1nom=$buf[2]; $v1idc=$buf[3]; $v1ll1=$buf[4]; $v1ul1=$buf[5]; $v1K1=$buf[6]; $v1B1=$buf[7]; $v1ll2=$buf[8]; $v1ul2=$buf[9]; $v1K2=$buf[10]; $v1B2=$buf[11]; $deltaV1=$buf[12]; if(/^V2/) @buf=split; $V2=$buf[1]; $v2nom=$buf[2]; $v2idc=$buf[3]; $v2ll1=$buf[4]; $v2ul1=$buf[5]; $v2K1=$buf[6]; $v2B1=$buf[7]; $v2ll2=$buf[8]; $v2ul2=$buf[9]; $v2K2=$buf[10]; $v2B2=$buf[11]; $deltaV2=$buf[12]; if(/^V3/) @buf=split;

143

$V3=$buf[1]; $v3nom=$buf[2]; $v3idc=$buf[3]; $v3ll1=$buf[4]; $v3ul1=$buf[5]; $v3K1=$buf[6]; $v3B1=$buf[7]; $v3ll2=$buf[8]; $v3ul2=$buf[9]; $v3K2=$buf[10]; $v3B2=$buf[11]; $deltaV3=$buf[12]; if(/^V4/) @buf=split; $V4=$buf[1]; $v4nom=$buf[2]; $v4idc=$buf[3]; $v4ll1=$buf[4]; $v4ul1=$buf[5]; $v4K1=$buf[6]; $v4B1=$buf[7]; $v4ll2=$buf[8]; $v4ul2=$buf[9]; $v4K2=$buf[10]; $v4B2=$buf[11]; $deltaV4=$buf[12]; if(/^V5/) @buf=split; $V5=$buf[1]; $v5nom=$buf[2]; $v5idc=$buf[3]; $v5ll1=$buf[4]; $v5ul1=$buf[5]; $v5K1=$buf[6]; $v5B1=$buf[7]; $v5ll2=$buf[8]; $v5ul2=$buf[9]; $v5K2=$buf[10]; $v5B2=$buf[11]; $deltaV5=$buf[12]; if(/^V6/) @buf=split; $V6=$buf[1]; $v6nom=$buf[2]; $v6idc=$buf[3]; $v6ll1=$buf[4]; $v6ul1=$buf[5]; $v6K1=$buf[6]; $v6B1=$buf[7]; $v6ll2=$buf[8]; $v6ul2=$buf[9]; $v6K2=$buf[10]; $v6B2=$buf[11];

144

$deltaV6=$buf[12]; if(/^V7/) @buf=split; $V7=$buf[1]; $v7nom=$buf[2]; $v7idc=$buf[3]; $v7ll1=$buf[4]; $v7ul1=$buf[5]; $v7K1=$buf[6]; $v7B1=$buf[7]; $v7ll2=$buf[8]; $v7ul2=$buf[9]; $v7K2=$buf[10]; $v7B2=$buf[11]; $deltaV7=$buf[12]; if($src_type eq "TOP_PINS") $toppins = 1; system "print \"\n$progname started in top pin mode at: \" \`date\` >> $lg"; else $toppins = 0; system "print \"\n$progname started in top node mode at: \" \`date\` >> $lg"; system "print \"\nSource Type Mode : $src_type \" >> $lg"; $found=0; $foundVDD=0; $foundGND=0; # First Time Open ASTAP Just To Find Correct Pattern To Search On open(ASTAP,"<$astap") || die "*ERROR* Program $progname can not open input file $astap.\n"; while(<ASTAP>) if(/^R/) @line=split ("__",$_); @node=split (" ",$line[0]); if($node[1] eq "VDD!") $found=1; $foundVDD=1; $NET="VDD"; $DJ="This VDD Network Is Not Disjoint"; $ISLAND="vdd"; system "print \"$DJ\" >> $lg"; $pat$ISLANDCA="R.*, VDD!__.* - VDD!__.* = .* V CA..."; $pat$ISLANDRV="R.*, VDD!__.* - VDD!__.* = .* V ....."; $pat$ISLANDNW="R.*, VDD!__.* - VDD!__.* = .* N ....."; $pat$ISLANDRW="R.*, VDD!__.* - VDD!__.* = .* W ....."; $pat$ISLANDN_VDDl="R.*, VDD! - VDD!__.* = .* N ....."; $pat$ISLANDN_VDDr="R.*, VDD!__.* - VDD! = .* N ....."; $pat$ISLANDW_VDDl="R.*, VDD! - VDD!__.* = .* W ....."; $pat$ISLANDW_VDDr="R.*, VDD!__.* - VDD! = .* W .....";

145

$pat$ISLANDTV=".. VDD!.* TV" ; last; if($node[1] eq "GND!") $found=1; $foundGND=1; $NET="GND"; $DJ="This GND Network Is Not Disjoint"; $ISLAND="gnd"; system "print \"$DJ\" >> $lg"; $pat$ISLANDCA="R.*, GND!__.* - GND!__.* = .* V CA..."; $pat$ISLANDRV="R.*, GND!__.* - GND!__.* = .* V ....."; $pat$ISLANDNW="R.*, GND!__.* - GND!__.* = .* N ....."; $pat$ISLANDRW="R.*, GND!__.* - GND!__.* = .* W ....."; $pat$ISLANDN_GNDl="R.*, GND! - GND!__.* = .* N ....."; $pat$ISLANDN_GNDr="R.*, GND!__.* - GND! = .* N ....."; $pat$ISLANDW_GNDl="R.*, GND! - GND!__.* = .* W ....."; $pat$ISLANDW_GNDr="R.*, GND!__.* - GND! = .* W ....."; $pat$ISLANDTV=".. GND!.* TV" ; last; $nnode=substr($node[1],0,9); if ($nnode eq "VDD!_OPEN") $found=1; $foundVDD=1; #R29, GND!_OPEN0__1 - GND!_OPEN0__47 = 82924.8 /* N M1out */ $NET="VDD"; $DJ="This VDD Network Is Disjoint. Using Island $node[1] In PGA Network"; $ISLAND=$node[1]; if(! defined $pat$ISLANDCA) system "print \"$DJ\" >> $lg"; $pat$ISLANDCA="NA"; $pat$ISLANDRV="NA"; $pat$ISLANDNW="NA"; $pat$ISLANDRW="NA"; $pat$ISLANDTV="NA"; #R3556169, VDD!_OPEN38__769375 - VDD!_OPEN38__9827 = 0.0085 /* V CAnew 0.0256 CAcon 0.16 M1out 0.24 11160.9200 8694.3200 */ $pat$ISLANDCA="R.*, VDD!_OPEN[0-9]*__.* - VDD!_OPEN[0-9]*__.* = .* V CA..."; $pat$ISLANDRV="R.*, VDD!_OPEN[0-9]*__.* - VDD!_OPEN[0-9]*__.* = .* V ....."; $pat$ISLANDNW="R.*, VDD!_OPEN[0-9]*__.* - VDD!_OPEN[0-9]*__.* = .* N ....."; $pat$ISLANDRW="R.*, VDD!_OPEN[0-9]*__.* - VDD!_OPEN[0-9]*__.* = .* W ....."; $pat$ISLANDN_VDDl="R.*, VDD! - VDD!_OPEN[0-9]*__.* = .* N ....."; $pat$ISLANDN_VDDr="R.*, VDD!_OPEN[0-9]*__.* - VDD! = .* N ....."; $pat$ISLANDW_VDDl="R.*, VDD! - VDD!_OPEN[0-9]*__.* = .* W ....."; $pat$ISLANDW_VDDr="R.*, VDD!_OPEN[0-9]*__.* - VDD! = .* W ....."; $pat$ISLANDTV=".. VDD!_OPEN[0-9]*__.* TV" ; last; if ($nnode eq "GND!_OPEN") $found=1; $foundGND=1; $NET="GND"; $DJ="This GND Network Is Disjoint. Using Island $node[1] In PGA Network"; $ISLAND=$node[1]; if(!defined $pat$ISLANDCA)system "print \"$DJ\" >> $lg"; $pat$ISLANDCA="NA";

146

$pat$ISLANDRV="NA"; $pat$ISLANDNW="NA"; $pat$ISLANDRW="NA"; $pat$ISLANDTV="NA"; $pat$ISLANDCA="R.*, GND!_OPEN[0-9]*__.* - GND!_OPEN[0-9]*__.* = .* V CA..."; $pat$ISLANDRV="R.*, GND!_OPEN[0-9]*__.* - GND!_OPEN[0-9]*__.* = .* V ....."; $pat$ISLANDNW="R.*, GND!_OPEN[0-9]*__.* - GND!_OPEN[0-9]*__.* = .* N ....."; $pat$ISLANDRW="R.*, GND!_OPEN[0-9]*__.* - GND!_OPEN[0-9]*__.* = .* W ....."; $pat$ISLANDN_GNDl="R.*, GND! - GND!_OPEN[0-9]*__.* = .* N ....."; $pat$ISLANDN_GNDr="R.*, GND!_OPEN[0-9]*__.* - GND! = .* N ....."; $pat$ISLANDW_GNDl="R.*, GND! - GND!_OPEN[0-9]*__.* = .* W ....."; $pat$ISLANDW_GNDr="R.*, GND!_OPEN[0-9]*__.* - GND! = .* W ....."; $pat$ISLANDTV=".. GND!_OPEN[0-9]*__.* TV" ; #if(/^$pat$ISLANDRW/)print "$_\n"; last; close ASTAP; $MSG="Did Not Find ISLAND Information"; if($found==0) system "print \"$MSG\" >> $lg"; exit 8; $tv_xy=0; $ca_xy=0; $bar_vias=0; $vias=0; $v1=0; $v2=0; $v3=0; $v4=0; $v5=0; $v6=0; $v7=0; $badR=0; $bn=0; $n=0; $w=0; $w1=0; $w2=0; $w3=0; $w4=0; $w5=0; $w6=0; $w7=0; $w8=0; $nw1=0; $nw2=0; $nw3=0; $nw4=0; $nw5=0; $nw6=0; $nw7=0; $nw8=0;

147

$s1=0; $s2=0; $s3=0; $s4=0; $s5=0; $s6=0; $s7=0; $s8=0; $VDD1=0; $VDD2=0; $VDD1=0; $VDD3=0; $VDD4=0; $VDD5=0; $VDD6=0; $VDD7=0; $VDD8=0; # Second Time, Open ASTAP To Do Real Work $VT=0; open(ASTAP,"<$astap") || die "*ERROR* Program $progname can not open input file $astap.\n"; while(<ASTAP>) $list=$ISLAND; if(/^$pat$listTV/) ($com1, $node_info, $level, $xl, $yl, $com2) = split; ($net_info, $node) = split('__',$node_info); $WLTVLEV$tv_xy="TVout"; $WLTVSRC$tv_xy="E".$tv_xy."_tv,".$node."-GND=0"; $WLTVNODE$tv_xy=$node; $WLTVX$tv_xy=$xl; $WLTVY$tv_xy=$yl; $tv_xy++; # if(/^$pat$listCA/) # # ($r,$node1_info,$dash,$node2_info,$eq,$rval,$com1,$rtyp,$level,$area,$segl,$segl_w,$segh,$segh_w,$xl,$yl,$com2)=split; # ($net_info, $node) = split('__',$node2_info); # $WLCALEV$ca_xy="CA"; # $WLCANODE$ca_xy=$node; # $WLCAX$ca_xy=$xl; # $WLCAY$ca_xy=$yl; # $WLCAWM1$ca_xy=substr(($segh_w/$scale),0,6); # #:g/if($WLCAWM1$ca_xy<$M1min)$WLCAWM1$ca_xy=$M1mod; # $ca_xy++; # if(/^$pat$listRV/) #R24855, GND!_OPEN0__197 - GND!_OPEN0__297 = 0.001 /* V V1 0.099225 M1out 0.945 M2out 0.945 189.8050 16.4675 */ #R248420, VDD!__14213 - VDD!__14502 = 0.00025 /* V V1 0.893025 M1out 0.945 M2out 0.945 10773.4725 11122.4925 */

148

#R969357, VDD!_OPEN0__322522 - VDD!_OPEN0__322812 = 0.0026 /* V VKout 0.81 MKout 1.35 MQout 2.7 13521.6000 8241.7500 */ ($r, $node1_info, $dash, $node2_info, $eq, $rval,$com1, $rtyp, $lev, $area, $segl, $segl_w, $segh, $segh_w, $xl, $yl, $com2) = split; ($net1_info, $node1) = split('__',$node1_info); ($net2_info, $node2) = split('__',$node2_info); if($lev eq "CAnew") $WLCALEV$ca_xy="CA"; $WLCANODE$ca_xy=$node2; $WLCAX$ca_xy=$xl; $WLCAY$ca_xy=$yl; $WLCAWM1$ca_xy=substr(($segh_w/$scale),0,6); $ca_xy++; $rid_length = length($r)-1; $rid=substr($r,1,$rid_length); if($lev eq "$V1" || $lev eq "$V2" || $lev eq "$V3" || $lev eq "$V4" || $lev eq "$V5" || $lev eq "$V6" || $lev eq "$V7") $exact_rval=$rval; if($exact_rval<$rmin)$exact_rval=$rmin; $RL=length($exact_rval); if($RL>=12) $er=substr($exact_rval,1,11); else $er=$exact_rval; $r_length = length($rid)-1; $usa=$area/($scale*$scale); $WLVLEV$vias=$lev; $WLVRID$vias="R".substr($rid,0,$r_length)."_v"; $WLVNODE1$vias=$node1; $WLVNODE2$vias=$node2; $WLVVAREA$vias=substr($usa,0,6); $WLVER$vias=$er; $WLVEXTACTR$vias=$exact_rval; $WLVSEGL_LEV$vias=$segl; $WLVSEGL_WID$vias=substr(($segl_w/$scale),0,6); $WLVSEGH_LEV$vias=$segh; $WLVSEGH_WID$vias=substr(($segh_w/$scale),0,6); $WLVX$vias=substr(($xl/$scale),0,11); $WLVY$vias=substr(($yl/$scale),0,11); $vias++; if($lev eq "$V1")$MMIN=0.8;$rnom=$v1nom;$v1++; if($lev eq "$V2")$MMIN=0.9;$rnom=$v2nom;$v2++; if($lev eq "$V3")$MMIN=0.9;$rnom=$v3nom;$v3++; if($lev eq "$V4")$MMIN=0.9;$rnom=$v4nom;$v4++; if($lev eq "$V5")$MMIN=0.9;$rnom=$v5nom;$v5++; if($lev eq "$V6")$MMIN=0.9;$rnom=$v6nom;$v6++; if($lev eq "$V7")$MMIN=0.9;$rnom=$v7nom;$v7++; $Nvias=($rnom/$rval); $nvias=int($Nvias); $LMW=($segl_w/$scale); $xl=$xl/$scale;

149

$yl=$yl/$scale; $vwt="$rd/viaTometal.txt"; if($vw eq "-vwt" && $nvias==1 && $LMW>$MMIN) if($VT==0) open(VWT,"> $vwt") || die "*ERROR* Program $progname can not open output file $vwt.\n"; else open(VWT,">> $vwt") || die "*ERROR* Program $progname can not open output file $vwt.\n"; printf VWT "LEV: %s rnom: %s rval: %s nvias: %s Nvias %s Mbelow: %s Mw: %.2f Vxl: %.2f Vyl: %.2f \n",$lev,$rnom,$rval,$Nvias,$nvias,$segl,$LMW,$xl,$yl; close VWT; $VT++; # close if(/$pat$listRV/) if(/^$pat$listNW/) ($r, $node1_info, $dash, $node2_info, $eq, $rval, $com1, $rtyp, $level, $com2) = split; ($net1_info, $node1) = split('__',$node1_info); ($net2_info, $node2) = split('__',$node2_info); if(!defined($node1) || !defined($node2)) $bn++; if(!defined($node1)) system "print \"\nFor $r, Node1 is undef in ERIE.astap, leaving out of netlist >> $lg"; if(!defined($node2)) system "print \"\nFor $r, Node2 is undef in ERIE.astap, leaving out of netlist >> $lg"; else if($level eq "$M1")$nw1++; if($level eq "$M2")$nw2++; if($level eq "$M3")$nw3++; if($level eq "$M4")$nw4++; if($level eq "$M5")$nw5++; if($level eq "$M6")$nw6++; if($level eq "$M7")$nw7++; if($level eq "$M8")$nw8++; $n++; if($rval<$rmin)$rval=$rmin; if($rval>$rmax)next; $rid_length = length($r)-2; $rid=substr($r,1,$rid_length); $WLNWLEV$n=$lev; $WLNWRID$n="R".$rid."_n"; $WLNWNODE1$n=$node1; $WLNWNODE2$n=$node2; $WLNWRVAL$n=$rval; if(/^$pat$listRW/) # R58116, VDD!__20054 - VDD!__20055 = 0.000725928 /* W M4out 0.687 468 0.27 468 7.9425 */

150

# R17287, GND!_OPEN0__12870 - GND!_OPEN0__12871 = 0.000456919 /* W M1out 1.6086 0.925 0.7 5.825 0.7 */ ($r, $node1_info, $dash, $node2_info, $eq, $rval, $com1, $rtyp, $level, $wb, $Xcl, $Ycl, $Xclh, $Ych, $com2) = split; ($net1_info, $node1) = split('__',$node1_info); ($net2_info, $node2) = split('__',$node2_info); if($level eq "$M1") $bias=$m1bias; $wub=($wb-2*$bias); $WLWSRC$M1$s1="E".$s1."_tv,".$node1."-GND=0"; $WLWSRC$M1X$s1=substr($Xcl/$scale,0,12); $WLWSRC$M1Y$s1=substr($Ycl/$scale,0,12); $WLWSRC$M1NODE$s1=$node1; $s1++; $WLWSRC$M1$s1="E".$s1."_tv,".$node2."-GND=0"; $WLWSRC$M1X$s1=substr($Xclh/$scale,0,12); $WLWSRC$M1Y$s1=substr($Ych/$scale,0,12); $WLWSRC$M1NODE$s1=$node2; $s1++; $w1++; if($level eq "$M2") $bias=$m2bias; $wub=($wb-2*$bias); $WLWSRC$M2$s2="E".$s2."_tv,".$node1."-GND=0"; $WLWSRC$M2X$s2=substr($Xcl/$scale,0,12); $WLWSRC$M2Y$s2=substr($Ycl/$scale,0,12); $WLWSRC$M2NODE$s2=$node1; $s2++; $WLWSRC$M2$s2="E".$s2."_tv,".$node2."-GND=0"; $WLWSRC$M2NODE$s2=$node2; $WLWSRC$M2X$s2=substr($Xclh/$scale,0,12); $WLWSRC$M2Y$s2=substr($Ych/$scale,0,12); $s2++; $w2++; if($level eq "$M3") $bias=$m3bias; $wub=($wb-2*$bias); $WLWSRC$M3$s3="E".$s3."_tv,".$node1."-GND=0"; $WLWSRC$M3X$s3=substr($Xcl/$scale,0,12); $WLWSRC$M3Y$s3=substr($Ycl/$scale,0,12); $WLWSRC$M3NODE$s3=$node1; $s3++; $WLWSRC$M3$s3="E".$s3."_tv,".$node2."-GND=0"; $WLWSRC$M3X$s3=substr($Xclh/$scale,0,12); $WLWSRC$M3Y$s3=substr($Ych/$scale,0,12); $WLWSRC$M3NODE$s3=$node2; $s3++; $w3++; if($level eq "$M4") $bias=$m4bias; $wub=($wb-2*$bias); $WLWSRC$M4$s4="E".$s4."_tv,".$node1."-GND=0"; $WLWSRC$M4X$s4=substr($Xcl/$scale,0,12);

151

$WLWSRC$M4Y$s4=substr($Ycl/$scale,0,12); $WLWSRC$M4NODE$s4=$node1; $s4++; $WLWSRC$M4$s4="E".$s4."_tv,".$node2."-GND=0"; $WLWSRC$M4X$s4=substr($Xclh/$scale,0,12); $WLWSRC$M4Y$s4=substr($Ych/$scale,0,12); $WLWSRC$M4NODE$s4=$node2; $s4++; $w4++; if($level eq "$M5") $bias=$m5bias; $wub=($wb-2*$bias); $WLWSRC$M5$sj="E".$s5."_tv,".$node1."-GND=0"; $WLWSRC$M5X$s5=substr($Xcl/$scale,0,12); $WLWSRC$M5Y$s5=substr($Ycl/$scale,0,12); $WLWSRC$M5NODE$s5=$node1; $s5++; $WLWSRC$M5$s5="E".$s5."_tv,".$node2."-GND=0"; $WLWSRC$M5X$s5=substr($Xclh/$scale,0,12); $WLWSRC$M5Y$s5=substr($Ych/$scale,0,12); $WLWSRC$M5NODE$s5=$node2; $s5++; $w5++; if($level eq "$M6") $bias=$m7bias; $wub=($wb-2*$bias); $WLWSRC$M6$s6="E".$s6."_tv,".$node1."-GND=0"; $WLWSRC$M6X$s6=substr($Xcl/$scale,0,12); $WLWSRC$M6Y$s6=substr($Ycl/$scale,0,12); $WLWSRC$M6NODE$s6=$node1; $s6++; $WLWSRC$M6$s6="E".$s6."_tv,".$node2."-GND=0"; $WLWSRC$M6X$s6=substr($Xclh/$scale,0,12); $WLWSRC$M6Y$s6=substr($Ych/$scale,0,12); $WLWSRC$M6NODE$s6=$node2; $s6++; $w6++; if($level eq "$M7") $bias=$m7bias; $wub=($wb-2*$bias); $WLWSRC$M7$s7="E".$s7."_tv,".$node1."-GND=0"; $WLWSRC$M7X$s7=substr($Xcl/$scale,0,12); $WLWSRC$M7Y$s7=substr($Ycl/$scale,0,12); $WLWSRC$M7NODE$s7=$node1; $s7++; $WLWSRC$M7$s7="E".$s7."_tv,".$node2."-GND=0"; $WLWSRC$M7X$s7=substr($Xclh/$scale,0,12); $WLWSRC$M7Y$s7=substr($Ych/$scale,0,12); $WLWSRC$M7NODE$s7=$node2; $s7++; $w7++; if($level eq "$M8")

152

$bias=$m8bias; $wub=($wb-2*$bias); $WLWSRC$M8$s8="E".$s8."_tv,".$node1."-GND=0"; $WLWSRC$M8X$s8=substr($Xcl/$scale,0,12); $WLWSRC$M8Y$s8=substr($Ycl/$scale,0,12); $WLWSRC$M8NODE$s8=$node1; $s8++; $WLWSRC$M8$s8="E".$s8."_tv,".$node2."-GND=0"; $WLWSRC$M8X$s8=substr($Xclh/$scale,0,12); $WLWSRC$M8Y$s8=substr($Ych/$scale,0,12); $WLWSRC$M8NODE$s8=$node2; $s8++; $w8++; $rid_length = length($r)-1; $rid=substr($r,1,$rid_length); if($rval<$rmin)$rval=$rmin; ($level,$str)=split("o",$lev); $str=$net1_info=$rtyp=$dash=$net2_info=$com1=$com2=$eq="\0"; $rID_length = length($rid)-1; $rID=substr($rid,0,$rID_length); $WLWLEV$w=$level; $WLWRID$w="R".$rID."_w"; $WLWNODE1$w=$node1; $WLWNODE2$w=$node2; $WLWRVAL$w=$rval; $WLWWIDTH$w=substr($wub/$scale,0,12); $WLWXCL$w=substr($Xcl/$scale,0,12); $WLWYCL$w=substr($Ycl/$scale,0,12); $WLWXCH$w=substr($Xclh/$scale,0,12); $WLWYCH$w=substr($Ych/$scale,0,12); $w++; #close if(/^$pat$listRW/) if($toppins == 1) #----------------------------------------------------- toppins if( ($foundVDD==1 && (/^$pat$listN_VDDl/ || /^$pat$listN_VDDr/ ))|| ($foundGND==1 && (/^$pat$listN_GNDl/ || /^$pat$listN_GNDr/)) ) ($r, $node1_info, $dash, $node2_info, $eq, $rval,$com1, $rtyp, $level, $com2) = split; if($node1_info eq "VDD!" || $node1_info eq "GND!") ($net1, $node2) = split('__',$node2_info); $node1 = "VDD_SRC"; else ($net2, $node1) = split('__',$node1_info); $node2 = "VDD_SRC"; if($level eq "$M1") $bias=$m1bias; $wub=($wb-2*$bias); $WLWVDD$M1VDD="E1_VDD, VDD_SRC-GND=0"; $WLWVDD$M1NODE$VDD1="VDD_SRC"; $VDD1++; $nw1++;

153

if($level eq "$M2") $bias=$m2bias; $wub=($wb-2*$bias); $WLWVDD$M2VDD="E2_VDD, VDD_SRC-GND=0"; $WLWVDD$M2NODE$VDD2="VDD_SRC"; $VDD2++; $nw2++; if($level eq "$M3") $bias=$m3bias; $wub=($wb-2*$bias); $WLWVDD$M3VDD="E3_VDD, VDD_SRC-GND=0"; $WLWVDD$M3NODE$VDD3="VDD_SRC"; $VDD3++; $nw3++; if($level eq "$M4") $bias=$m4bias; $wub=($wb-2*$bias); $WLWVDD$M4VDD="E4_VDD, VDD_SRC-GND=0"; $WLWVDD$M4NODE$VDD4="VDD_SRC"; $VDD4++; $nw4++; if($level eq "$M5") $bias=$m5bias; $wub=($wb-2*$bias); $WLWVDD$M5VDD="E5_VDD, VDD_SRC-GND=0"; $WLWVDD$M5NODE$VDD5="VDD_SRC"; $VDD5++; $nw5++; if($level eq "$M6") $bias=$m6bias; $wub=($wb-2*$bias); $WLWVDD$M6VDD="E6_VDD, VDD_SRC-GND=0"; $WLWVDD$M6NODE$VDD6="VDD_SRC"; $VDD6++; $nw6++; if($level eq "$M7") $bias=$m7bias; $wub=($wb-2*$bias); $WLWVDD$M7VDD="E7_VDD, VDD_SRC-GND=0"; $WLWVDD$M7NODE$VDD7="VDD_SRC"; $VDD7++; $nw7++; if($level eq "$M8") $bias=$m8bias; $wub=($wb-2*$bias); $WLWVDD$M8VDD="E8_VDD, VDD_SRC-GND=0"; $WLWVDD$M8NODE$VDD8="VDD_SRC"; $VDD8++; $nw8++;

154

if(!defined($node1) || !defined($node2)) $bn++; if(!defined($node1)) system "print \"\nFor $r, Node1 is undef in ERIE.astap, leaving out of netlist >> $lg"; if(!defined($node2)) system "print \"\nFor $r, Node2 is undef in ERIE.astap, leaving out of netlist >> $lg"; else if($rval<$rmin)$rval=$rmin; if($rval>$rmax)next; $rid_length = length($r)-2; $rid=substr($r,1,$rid_length); $WLNWLEV$n=$level; $WLNWRID$n="R".$rid."_n"; $WLNWNODE1$n=$node1; $WLNWNODE2$n=$node2; $WLNWRVAL$n=$rval; $n++; if( ($foundVDD==1 && (/^$pat$listW_VDDl/ || /^$pat$listW_VDDr/ ))|| ($foundGND==1 && (/^$pat$listW_GNDl/ || /^$pat$listW_GNDr/)) ) ($r, $node1_info, $dash, $node2_info, $eq, $rval, $com1, $rtyp, $level, $wb, $Xcl, $Ycl, $Xclh, $Ych, $com2) = split; if($node1_info eq "VDD!" || $node1_info eq "GND!") ($net1, $node2) = split('__',$node2_info); $node1 = "VDD_SRC"; $Xc=$Xcl; $Yc=$Ycl; else ($net2, $node1) = split('__',$node1_info); $node2 = "VDD_SRC"; $Xc=$Xch; $Yc=$Ych; if($level eq "$M1") $bias=$m1bias; $wub=($wb-2*$bias); $WLWVDD$M1VDD="E1_VDD, VDD_SRC-GND=0"; $WLWVDD$M1X$VDD1=substr($Xc/$scale,0,12); $WLWVDD$M1Y$VDD1=substr($Yc/$scale,0,12); $WLWVDD$M1NODE$VDD1="VDD_SRC"; $VDD1++; $w1++; if($level eq "$M2") $bias=$m2bias; $wub=($wb-2*$bias); $WLWVDD$M2VDD="E2_VDD, VDD_SRC-GND=0"; $WLWVDD$M2X$VDD2=substr($Xc/$scale,0,12); $WLWVDD$M2Y$VDD2=substr($Yc/$scale,0,12); $WLWVDD$M2NODE$VDD2="VDD_SRC";

155

$VDD2++; $w2++; if($level eq "$M3") $bias=$m3bias; $wub=($wb-2*$bias); $WLWVDD$M3VDD="E3_VDD, VDD_SRC-GND=0"; $WLWVDD$M3X$VDD3=substr($Xc/$scale,0,12); $WLWVDD$M3Y$VDD3=substr($Yc/$scale,0,12); $WLWVDD$M3NODE$VDD3="VDD_SRC"; $VDD3++; $w3++; if($level eq "$M4") $bias=$m4bias; $wub=($wb-2*$bias); $WLWVDD$M4VDD="E4_VDD, VDD_SRC-GND=0"; $WLWVDD$M4X$VDD4=substr($Xc/$scale,0,12); $WLWVDD$M4Y$VDD4=substr($Yc/$scale,0,12); $WLWVDD$M4NODE$VDD4="VDD_SRC"; $VDD4++; $w4++; if($level eq "$M5") $bias=$m5bias; $wub=($wb-2*$bias); $WLWVDD$M5VDD="E5_VDD, VDD_SRC-GND=0"; $WLWVDD$M5X$VDD5=substr($Xc/$scale,0,12); $WLWVDD$M5Y$VDD5=substr($Yc/$scale,0,12); $WLWVDD$M5NODE$VDD5="VDD_SRC"; $VDD5++; $w5++; if($level eq "$M6") $bias=$m6bias; $wub=($wb-2*$bias); $WLWVDD$M6VDD="E6_VDD, VDD_SRC-GND=0"; $WLWVDD$M6X$VDD6=substr($Xc/$scale,0,12); $WLWVDD$M6Y$VDD6=substr($Yc/$scale,0,12); $WLWVDD$M6NODE$VDD6="VDD_SRC"; $VDD6++; $w6++; if($level eq "$M7") $bias=$m7bias; $wub=($wb-2*$bias); $WLWVDD$M7VDD="E7_VDD, VDD_SRC-GND=0"; $WLWVDD$M7X$VDD7=substr($Xc/$scale,0,12); $WLWVDD$M7Y$VDD7=substr($Yc/$scale,0,12); $WLWVDD$M7NODE$VDD7="VDD_SRC"; $VDD7++; $w7++; if($level eq "$M8") $bias=$m8bias; $wub=($wb-2*$bias);

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$WLWVDD$M8VDD="E8_VDD, VDD_SRC-GND=0"; $WLWVDD$M8X$VDD8=substr($Xc/$scale,0,12); $WLWVDD$M8Y$VDD8=substr($Yc/$scale,0,12); $WLWVDD$M8NODE$VDD8="VDD_SRC"; $VDD8++; $w8++; $rid_length = length($r)-1; $rid=substr($r,1,$rid_length); if($rval<$rmin)$rval=$rmin; ($level,$str)=split("o",$lev); $str=$net1_info=$rtyp=$dash=$net2_info=$com1=$com2=$eq="\0"; $rID_length = length($rid)-1; $rID=substr($rid,0,$rID_length); $WLWLEV$w=$level; $WLWRID$w="R".$rID."_w"; $WLWNODE1$w=$node1; $WLWNODE2$w=$node2; $WLWRVAL$w=$rval; $WLWWIDTH$w=substr($wub/$scale,0,12); $WLWXCL$w=substr($Xcll/$scale,0,12); $WLWYCL$w=substr($Ycl/$scale,0,12); $WLWXCH$w=substr($Xclh/$scale,0,12); $WLWYCH$w=substr($Ych/$scale,0,12); $w++; #---------------------------------------------------- end of toppins #close while close ASTAP; open(OUTASTAP,">$outastap") || die "*ERROR* Program $progname can not open output file $outastap.\n"; $TOPinfo="$rd/tv.info"; if($tv_xy !=0)open(TOPINFO,">$TOPinfo") || die "*ERROR* Program $progname can not open output file $TOPinfo.\n"; $viaout = "$rd/via.frl"; if($vias !=0)open(VIAOUTGD,">$viaout") || die "*ERROR* Program $progname can not open input file $viaout.\n"; $wout = "$rd/wmetal.frl"; if($w !=0)open(WOUTGD,">$wout") || die "*ERROR* Program $progname can not open output file $wout.\n"; $vsrc=0; $isrc=0; $vr=0; $wr=0; $nwr=0; # CONTACTS $cainfo = "$rd/ca.info"; if($ca_xy !=0)

157

open(CAINFO,"> $cainfo") || die "*ERROR* Program $progname can not open output file $cainfo.\n"; for($isrc=0;$isrc<$ca_xy;$isrc++) printf CAINFO "%.5f %.5f %s %.2f\ \n",$WLCAX$isrc,$WLCAY$isrc,$WLCANODE$isrc,$WLCAWM1$isrc; else system "print \"ERROR There is no contact.\" >> $lg"; exit 8; close CAINFO; # TOP VIAS $totVias=$vias+$bar_vias; if($tv_xy !=0) # then we are working at chip level, proceed normally if($w8+$nw8 !=0) for($vsrc=0;$vsrc<$tv_xy;$vsrc++) printf OUTASTAP "%s\n",$WLTVSRC$vsrc; printf TOPINFO "%.5f %.5f %s \n",$WLTVX$vsrc,$WLTVY$vsrc,$WLTVNODE$vsrc; for($vr=0;$vr<$vias;$vr++) $L=$WLVLEV$vr; printf OUTASTAP "%s, %s-%s=%s\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$WLVEXTACTR$vr; printf VIAOUTGD pack ("A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$L,$WLVVAREA$vr,$WLVER$vr,$WLVSEGL_LEV$vr,$WLVSEGL_WID$vr,$WLVSEGH_LEV$vr,$WLVSEGH_WID$vr,$WLVX$vr,$WLVY$vr); for($wr=0;$wr<$w;$wr++) $L=$WLWLEV$wr; printf OUTASTAP "%s, %s-%s=%s\n",$WLWRID$wr,$WLWNODE1$wr,$WLWNODE2$wr,$WLWRVAL$wr; printf WOUTGD pack ("A12 A12 A12 A15 A15 A15 A15 A15\n",$WLWRID$wr,$WLWRVAL$wr,$L,$WLWWIDTH$wr,$WLWXCL$wr,$WLWYCL$wr,$WLWXCH$wr,$WLWYCH$wr); for($nwr=0;$nwr<$n;$nwr++) # $L=$WLNWLEV$nwr; printf OUTASTAP "%s, %s-%s=%s\n",$WLNWRID$nwr,$WLNWNODE1$nwr,$WLNWNODE2$nwr,$WLNWRVAL$nwr;

158

system "print \"===> Source Level (Real C4) : TV\" >> $lg"; system "print \"===> #c4=$tv_xy, #ca=$ca_xy \" >> $lg"; system "print \"===> TotalVias=$totvias, Vias=$vias, BarVias=$bar_vias\" >> $lg"; system "print \"===> # $V1=$v1 # $V2=$v2 # $V3=$v3 # $V4=$v4 # $V5=$v5 # $V6=$v6 # $V7=$v7\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> # $M1=$w1, # $M2=$w2, # $M3=$w3, # $M4=$w4, # $M5=$w5, # $M6=$w6, # $M7=$w7, # $M8=$w8\" >> $lg"; system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1 $nw2 on $M2 $nw3 on $M3 $nw4 on $M4 $nw5 on $M5 $nw6 on $M6 $nw7 on $M7 $nw8 on $M8\" >> $lg"; system "print \"\n$progname ended at: \" \`date\` >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; exit(0); else system "print \"\nERROR C4 floating. No $M8.\" >> $lg"; system "print \"\n$progname ended at: \" \`date\` >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; exit(8); else # we are working at macro level, must find top metal level and ground it #--------------------------------------------------------------------- LM/M8 top if($w8+$nw8 != 0 && $v7 !=0) # make LM level gnd if($toppins == 0) system "print \"===> Source Type: $src_type Source Level (new C4) : $M8\" >> $lg"; system "print \"===> #c4=$s8, #ca=$ca_xy \" >> $lg"; for($vsrc=0;$vsrc<$s8;$vsrc++) printf OUTASTAP "%s\n",$WLWSRC$M8$vsrc; printf TOPINFO "%.4f %.4f %s \n",$WLWSRC$M8X$vsrc,$WLWSRC$M8Y$vsrc,$WLWSRC$M8NODE$vsrc; else if($VDD8==0) system "print \"ERROR No VDD pin on top level metal, $M8.\" >> $lg"; exit 3; else system "print \"===> Source Type: $src_type Source Level (new C4) : $M8\" >> $lg";

159

system "print \"===> #Top level=$M8 #Top pins=$VDD8, #ca=$ca_xy \" >> $lg"; printf OUTASTAP "%s\n",$WLWVDD$M8VDD; for($vsrc=0;$vsrc<$VDD8;$vsrc++) printf TOPINFO "%.4f %.4f %s \n",$WLWVDD$M8X$vsrc,$WLWVDD$M8Y$vsrc,$WLWVDD$M8NODE$vsrc; system "print \"===> TotalVias=$totvias, Vias=$vias, BarVias=$bar_vias\" >> $lg"; system "print \"===> # $V1=$v1 # $V2=$v2 # $V3=$v3 # $V4=$v4 # $V5=$v5 # $V6=$v6 # $V7=$v7\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> # $M1=$w1, # $M2=$w2, # $M3=$w3, # $M4=$w4, # $M5=$w5, # $M6=$w6, # $M7=$w7, # $M8=$w8\" >> $lg"; for($vr=0;$vr<$vias;$vr++) $L=$WLVLEV$vr; printf OUTASTAP "%s, %s-%s=%s\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$WLVEXTACTR$vr; printf VIAOUTGD pack ("A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$L,$WLVVAREA$vr,$WLVER$vr,$WLVSEGL_LEV$vr,$WLVSEGL_WID$vr,$WLVSEGH_LEV$vr,$WLVSEGH_WID$vr,$WLVX$vr,$WLVY$vr); for($wr=0;$wr<$w;$wr++) $L=$WLWLEV$wr; printf OUTASTAP "%s, %s-%s=%s\n",$WLWRID$wr,$WLWNODE1$wr,$WLWNODE2$wr,$WLWRVAL$wr; printf WOUTGD pack ("A12 A12 A12 A15 A15 A15 A15 A15\n",$WLWRID$wr,$WLWRVAL$wr,$L,$WLWWIDTH$wr,$WLWXCL$wr,$WLWYCL$wr,$WLWXCH$wr,$WLWYCH$wr); for($nwr=0;$nwr<$n;$nwr++) # $L=$WLNWLEV$nwr; printf OUTASTAP "%s, %s-%s=%s\n",$WLNWRID$nwr,$WLNWNODE1$nwr,$WLNWNODE2$nwr,$WLNWRVAL$nwr; system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1 $nw2 on $M2 $nw3 on $M3 $nw4 on $M4 $nw5 on $M5 $nw6 on $M6 $nw7 on $M7 $nw8 on $M8\" >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; system "print \"\n$progname ended at: \" \`date\` >> $lg"; exit(0); #--------------------------------------------------------------------- FW/M7 top if($w7+$nw7 != 0 && $v6 !=0) # make fw level gnd if($toppins == 0)

160

system "print \"===> Source Type: $src_type Source Level (new C4) : $M7\" >> $lg"; system "print \"===> #c4=$s7, #ca=$ca_xy \" >> $lg"; for($vsrc=0;$vsrc<$s7;$vsrc++) printf OUTASTAP "%s\n",$WLWSRC$M7$vsrc; printf TOPINFO "%.4f %.4f %s \n",$WLWSRC$M7X$vsrc,$WLWSRC$M7Y$vsrc,$WLWSRC$M7NODE$vsrc; else if($VDD7==0) system "print \"ERROR No VDD pin on top level metal, $M7.\" >> $lg"; exit 3; else system "print \"===> Source Type: $src_type Source Level (new C4) : $M7\" >> $lg"; system "print \"===> #Top level=$M7 #Top pins=$VDD7, #ca=$ca_xy \" >> $lg"; printf OUTASTAP "%s\n",$WLWVDD$M7VDD; for($vsrc=0;$vsrc<$VDD7;$vsrc++) printf TOPINFO "%.4f %.4f %s \n",$WLWVDD$M7X$vsrc,$WLWVDD$M7Y$vsrc,$WLWVDD$M7NODE$vsrc; system "print \"===> TotalVias=$totvias, Vias=$vias, BarVias=$bar_vias\" >> $lg"; system "print \"===> # $V1=$v1 # $V2=$v2 # $V3=$v3 # $V4=$v4 # $V5=$v5 # $V6=$v6\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> # $M1=$w1, # $M2=$w2, # $M3=$w3, # $M4=$w4, # $M5=$w5, # $M6=$w6, # $M7=$w7\" >> $lg"; for($vr=0;$vr<$vias;$vr++) $L=$WLVLEV$vr; printf OUTASTAP "%s, %s-%s=%s\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$WLVEXTACTR$vr; printf VIAOUTGD pack ("A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$L,$WLVVAREA$vr,$WLVER$vr,$WLVSEGL_LEV$vr,$WLVSEGL_WID$vr,$WLVSEGH_LEV$vr,$WLVSEGH_WID$vr,$WLVX$vr,$WLVY$vr); for($wr=0;$wr<$w;$wr++) $L=$WLWLEV$wr; printf OUTASTAP "%s, %s-%s=%s\n",$WLWRID$wr,$WLWNODE1$wr,$WLWNODE2$wr,$WLWRVAL$wr; printf WOUTGD pack ("A12 A12 A12 A15 A15 A15 A15 A15\n",$WLWRID$wr,$WLWRVAL$wr,$L,$WLWWIDTH$wr,$WLWXCL$wr,$WLWYCL$wr,$WLWXCH$wr,$WLWYCH$wr); for($nwr=0;$nwr<$n;$nwr++)

161

# $L=$WLNWLEV$nwr; printf OUTASTAP "%s, %s-%s=%s\n",$WLNWRID$nwr,$WLNWNODE1$nwr,$WLNWNODE2$nwr,$WLNWRVAL$nwr; system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1 $nw2 on $M2 $nw3 on $M3 $nw4 on $M4 $nw5 on $M5 $nw6 on $M6 $nw7 on $M7\" >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; system "print \"\n$progname ended at: \" \`date\` >> $lg"; exit(0); #--------------------------------------------------------------------- B1/M6 top if($w6+$nw6 != 0 && $v5 !=0) # make b1 level gnd if($toppins == 0) system "print \"===> Source Type: $src_type Source Level (new C4) : $M6\" >> $lg"; system "print \"===> #c4=$s6, #ca=$ca_xy \" >> $lg"; for($vsrc=0;$vsrc<$s6;$vsrc++) printf OUTASTAP "%s\n",$WLWSRC$M6$vsrc; printf TOPINFO "%.4f %.4f %s \n",$WLWSRC$M6X$vsrc,$WLWSRC$M6Y$vsrc,$WLWSRC$M6NODE$vsrc; else if($VDD6==0) system "print \"ERROR No VDD pin on top level metal, $M6.\" >> $lg"; exit 3; else system "print \"===> Source Type: $src_type Source Level (new C4) : $M6\" >> $lg"; system "print \"===> #Top level=$M6 #Top pins=$VDD6, #ca=$ca_xy \" >> $lg"; printf OUTASTAP "%s\n",$WLWVDD$M6VDD; for($vsrc=0;$vsrc<$VDD6;$vsrc++) printf TOPINFO "%.4f %.4f %s \n",$WLWVDD$M6X$vsrc,$WLWVDD$M6Y$vsrc,$WLWVDD$M6NODE$vsrc; system "print \"===> TotalVias=$totvias, Vias=$vias, BarVias=$bar_vias\" >> $lg"; system "print \"===> # $V1=$v1 # $V2=$v2 # $V3=$v3 # $V4=$v4 # $V5=$v5\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> # $M1=$w1, # $M2=$w2, # $M3=$w3, # $M4=$w4, # $M5=$w5, # $M6=$w6\" >> $lg"; for($vr=0;$vr<$vias;$vr++)

162

$L=$WLVLEV$vr; printf OUTASTAP "%s, %s-%s=%s\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$WLVEXTACTR$vr; printf VIAOUTGD pack ("A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$L,$WLVVAREA$vr,$WLVER$vr,$WLVSEGL_LEV$vr,$WLVSEGL_WID$vr,$WLVSEGH_LEV$vr,$WLVSEGH_WID$vr,$WLVX$vr,$WLVY$vr); for($wr=0;$wr<$w;$wr++) $L=$WLWLEV$wr; printf OUTASTAP "%s, %s-%s=%s\n",$WLWRID$wr,$WLWNODE1$wr,$WLWNODE2$wr,$WLWRVAL$wr; printf WOUTGD pack ("A12 A12 A12 A15 A15 A15 A15 A15\n",$WLWRID$wr,$WLWRVAL$wr,$L,$WLWWIDTH$wr,$WLWXCL$wr,$WLWYCL$wr,$WLWXCH$wr,$WLWYCH$wr); for($nwr=0;$nwr<$n;$nwr++) # $L=$WLNWLEV$nwr; printf OUTASTAP "%s, %s-%s=%s\n",$WLNWRID$nwr,$WLNWNODE1$nwr,$WLNWNODE2$nwr,$WLNWRVAL$nwr; system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1 $nw2 on $M2 $nw3 on $M3 $nw4 on $M4 $nw5 on $M5 $nw6 on $M6\" >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; system "print \"\n$progname ended at: \" \`date\` >> $lg"; exit(0); #--------------------------------------------------------------------- M5 top if($w5+$nw5 != 0 && $v4 !=0) # make m5 level gnd if($toppins == 0) system "print \"===> Source Type: $src_type Source Level (new C4) : $M5\" >> $lg"; system "print \"===> #c4=$s5, #ca=$ca_xy \" >> $lg"; for($vsrc=0;$vsrc<$s5;$vsrc++) printf OUTASTAP "%s\n",$WLWSRC$M5$vsrc; printf TOPINFO "%.4f %.4f %s \n",$WLWSRC$M5X$vsrc,$WLWSRC$M5Y$vsrc,$WLWSRC$M5NODE$vsrc; else if($VDD5==0) system "print \"ERROR No VDD pin on top level metal, $M5.\" >> $lg"; exit 3;

163

else system "print \"===> Source Type: $src_type Source Level (new C4) : $M5\" >> $lg"; system "print \"===> #Top level=$M5 #Top pins=$VDD5, #ca=$ca_xy \" >> $lg"; printf OUTASTAP "%s\n",$WLWVDD$M5VDD; for($vsrc=0;$vsrc<$VDD5;$vsrc++) printf TOPINFO "%.4f %.4f %s \n",$WLWVDD$M5X$vsrc,$WLWVDD$M5Y$vsrc,$WLWVDD$M5NODE$vsrc; system "print \"===> TotalVias=$totvias, Vias=$vias, BarVias=$bar_vias\" >> $lg"; system "print \"===> # $V1=$v1 # $V2=$v2 # $V3=$v3 # $V4=$v4\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> # $M1=$w1, # $M2=$w2, # $M3=$w3, # $M4=$w4, # $M5=$w5\" >>$lg"; for($vr=0;$vr<$vias;$vr++) $L=$WLVLEV$vr; printf OUTASTAP "%s, %s-%s=%s\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$WLVEXTACTR$vr; printf VIAOUTGD pack ("A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$L,$WLVVAREA$vr,$WLVER$vr,$WLVSEGL_LEV$vr,$WLVSEGL_WID$vr,$WLVSEGH_LEV$vr,$WLVSEGH_WID$vr,$WLVX$vr,$WLVY$vr); for($wr=0;$wr<$w;$wr++) $L=$WLWLEV$wr; printf OUTASTAP "%s, %s-%s=%s\n",$WLWRID$wr,$WLWNODE1$wr,$WLWNODE2$wr,$WLWRVAL$wr; printf WOUTGD pack ("A12 A12 A12 A15 A15 A15 A15 A15\n",$WLWRID$wr,$WLWRVAL$wr,$L,$WLWWIDTH$wr,$WLWXCL$wr,$WLWYCL$wr,$WLWXCH$wr,$WLWYCH$wr); for($nwr=0;$nwr<$n;$nwr++) # $L=$WLNWLEV$nwr; printf OUTASTAP "%s, %s-%s=%s\n",$WLNWRID$nwr,$WLNWNODE1$nwr,$WLNWNODE2$nwr,$WLNWRVAL$nwr; system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1 $nw2 on $M2 $nw3 on $M3 $nw4 on $M4 $nw5 on $M5\" >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; system "print \"\n$progname ended at: \" \`date\` >> $lg"; exit(0); #--------------------------------------------------------------------- M4 top if($w4+$nw4 != 0 && $v3 !=0) # make m4 level gnd if($toppins == 0)

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system "print \"===> Source Type: $src_type Source Level (new C4) : $M4\" >> $lg"; system "print \"===> #c4=$s4, #ca=$ca_xy \" >> $lg"; for($vsrc=0;$vsrc<$s4;$vsrc++) printf OUTASTAP "%s\n",$WLWSRC$M4$vsrc; printf TOPINFO "%.4f %.4f %s \n",$WLWSRC$M4X$vsrc,$WLWSRC$M4Y$vsrc,$WLWSRC$M4NODE$vsrc; else if($VDD4==0) system "print \"ERROR No VDD pin on top level metal, $M4.\" >> $lg"; exit 3; else system "print \"===> Source Type: $src_type Source Level (new C4) : $M4\" >> $lg"; system "print \"===> #Top level=$M4 #Top pins=$VDD4, #ca=$ca_xy \" >> $lg"; printf OUTASTAP "%s\n",$WLWVDD$M4VDD; for($vsrc=0;$vsrc<$VDD4;$vsrc++) printf TOPINFO "%.4f %.4f %s \n",$WLWVDD$M4X$vsrc,$WLWVDD$M4Y$vsrc,$WLWVDD$M4NODE$vsrc; system "print \"===> TotalVias=$totvias, Vias=$vias, BarVias=$bar_vias\" >> $lg"; system "print \"===> # $V1=$v1 # $V2=$v2 # $V3=$v3\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> # $M1=$w1, # $M2=$w2, # $M3=$w3, # $M4=$w4\" >> $lg"; for($vr=0;$vr<$vias;$vr++) $L=$WLVLEV$vr; printf OUTASTAP "%s, %s-%s=%s\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$WLVEXTACTR$vr; printf VIAOUTGD pack ("A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$L,$WLVVAREA$vr,$WLVER$vr,$WLVSEGL_LEV$vr,$WLVSEGL_WID$vr,$WLVSEGH_LEV$vr,$WLVSEGH_WID$vr,$WLVX$vr,$WLVY$vr); for($wr=0;$wr<$w;$wr++) $L=$WLWLEV$wr; printf OUTASTAP "%s, %s-%s=%s\n",$WLWRID$wr,$WLWNODE1$wr,$WLWNODE2$wr,$WLWRVAL$wr; printf WOUTGD pack ("A12 A12 A12 A15 A15 A15 A15 A15\n",$WLWRID$wr,$WLWRVAL$wr,$L,$WLWWIDTH$wr,$WLWXCL$wr,$WLWYCL$wr,$WLWXCH$wr,$WLWYCH$wr); for($nwr=0;$nwr<$n;$nwr++) # $L=$WLNWLEV$nwr;

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printf OUTASTAP "%s, %s-%s=%s\n",$WLNWRID$nwr,$WLNWNODE1$nwr,$WLNWNODE2$nwr,$WLNWRVAL$nwr; system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1 $nw2 on $M2 $nw3 on $M3 $nw4 on $M4\" >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; system "print \"\n$progname ended at: \" \`date\` >> $lg"; exit(0); #--------------------------------------------------------------------- M3 top if($w3+$nw3 != 0 && $v2 !=0) # make m3 level gnd if($toppins == 0) if($s3==0) system "print \"ERROR No VDD pin on top level metal, $M3.\" >> $lg"; exit 3; else system "print \"===> Source Type: $src_type Source Level (new C4) : $M3\" >> $lg"; system "print \"===> #c4=$s3, #ca=$ca_xy \" >> $lg"; for($vsrc=0;$vsrc<$s3;$vsrc++) printf OUTASTAP "%s\n",$WLWSRC$M3$vsrc; printf TOPINFO "%.4f %.4f %s \n",$WLWSRC$M3X$vsrc,$WLWSRC$M3Y$vsrc,$WLWSRC$M3NODE$vsrc; else if($VDD3==0) system "print \"ERROR No VDD pin on top level metal, $M3.\" >> $lg"; exit 3; else system "print \"===> Source Type: $src_type Source Level (new C4) : $M3\" >> $lg"; system "print \"===> #Top level=$M3 #Top pins=$VDD3, #ca=$ca_xy \" >> $lg"; printf OUTASTAP "%s\n",$WLWVDD$M3VDD; for($vsrc=0;$vsrc<$VDD3;$vsrc++) printf TOPINFO "%.4f %.4f %s \n",$WLWVDD$M3X$vsrc,$WLWVDD$M3Y$vsrc,$WLWVDD$M3NODE$vsrc;

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system "print \"===> TotalVias=$totvias, Vias=$vias, BarVias=$bar_vias\" >> $lg"; system "print \"===> # $V1=$v1 # $V2=$v2\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> # $M1=$w1, # $M2=$w2, # $M3=$w3\" >> $lg"; for($vr=0;$vr<$vias;$vr++) $L=$WLVLEV$vr; printf OUTASTAP "%s, %s-%s=%s\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$WLVEXTACTR$vr; printf VIAOUTGD pack ("A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$L,$WLVVAREA$vr,$WLVER$vr,$WLVSEGL_LEV$vr,$WLVSEGL_WID$vr,$WLVSEGH_LEV$vr,$WLVSEGH_WID$vr,$WLVX$vr,$WLVY$vr); for($wr=0;$wr<$w;$wr++) $L=$WLWLEV$wr; printf OUTASTAP "%s, %s-%s=%s\n",$WLWRID$wr,$WLWNODE1$wr,$WLWNODE2$wr,$WLWRVAL$wr; printf WOUTGD pack ("A12 A12 A12 A15 A15 A15 A15 A15\n",$WLWRID$wr,$WLWRVAL$wr,$L,$WLWWIDTH$wr,$WLWXCL$wr,$WLWYCL$wr,$WLWXCH$wr,$WLWYCH$wr); for($nwr=0;$nwr<$n;$nwr++) # $L=$WLNWLEV$nwr; printf OUTASTAP "%s, %s-%s=%s\n",$WLNWRID$nwr,$WLNWNODE1$nwr,$WLNWNODE2$nwr,$WLNWRVAL$nwr; system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1 $nw2 on $M2 $nw3 on $M3\" >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; system "print \"\n$progname ended at: \" \`date\` >> $lg"; exit(0); #--------------------------------------------------------------------- M2 top if($w2+$nw2 != 0 && $v1 !=0) # make m2 level gnd if($toppins == 0) if($s2==0) system "print \"ERROR No VDD pin on top level metal, $M2.\" >> $lg"; exit 3; else system "print \"===> Source Type: $src_type Source Level (new C4) : $M2\" >> $lg"; system "print \"===> #c4=$s2, #ca=$ca_xy \" >> $lg"; $w=$w-$w2; $src=$s2; for($vsrc=0;$vsrc<$s2;$vsrc++)

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printf OUTASTAP "%s\n",$WLWSRC$M2$vsrc; printf TOPINFO "%.4f %.4f %s \n",$WLWSRC$M2X$vsrc,$WLWSRC$M2Y$vsrc,$WLWSRC$M2NODE$vsrc; else if($VDD2==0) system "print \"ERROR No VDD pin on top level metal, $M2.\" >> $lg"; exit 3; else system "print \"===> Source Type: $src_type Source Level (new C4) : $M2\" >> $lg"; system "print \"===> #Top level=$M2 #Top pins=$VDD2, #ca=$ca_xy \" >> $lg"; printf OUTASTAP "%s\n",$WLWVDD$M2VDD; for($vsrc=0;$vsrc<$VDD2;$vsrc++) printf TOPINFO "%.4f %.4f %s \n",$WLWVDD$M2X$vsrc,$WLWVDD$M2Y$vsrc,$WLWVDD$M2NODE$vsrc; system "print \"===> TotalVias=$totvias, Vias=$vias, BarVias=$bar_vias\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> # $V1=$v1\" >> $lg"; system "print \"===> # $M1=$w1, # $M2=$w2\" >> $lg"; for($vr=0;$vr<$vias;$vr++) $L=$WLVLEV$vr; printf OUTASTAP "%s, %s-%s=%s\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$WLVEXTACTR$vr; printf VIAOUTGD pack ("A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12\n",$WLVRID$vr,$WLVNODE1$vr,$WLVNODE2$vr,$L,$WLVVAREA$vr,$WLVER$vr,$WLVSEGL_LEV$vr,$WLVSEGL_WID$vr,$WLVSEGH_LEV$vr,$WLVSEGH_WID$vr,$WLVX$vr,$WLVY$vr); for($wr=0;$wr<$w;$wr++) $L=$WLWLEV$wr; printf OUTASTAP "%s, %s-%s=%s\n",$WLWRID$wr,$WLWNODE1$wr,$WLWNODE2$wr,$WLWRVAL$wr; printf WOUTGD pack ("A12 A12 A12 A15 A15 A15 A15 A15\n",$WLWRID$wr,$WLWRVAL$wr,$L,$WLWWIDTH$wr,$WLWXCL$wr,$WLWYCL$wr,$WLWXCH$wr,$WLWYCH$wr); for($nwr=0;$nwr<$n;$nwr++) # $L=$WLNWLEV$nwr; printf OUTASTAP "%s, %s-%s=%s\n",$WLNWRID$nwr,$WLNWNODE1$nwr,$WLNWNODE2$nwr,$WLNWRVAL$nwr;

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system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1 $nw2 on $M2\" >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; system "print \"\n$progname ended at: \" \`date\` >> $lg"; exit(0); #--------------------------------------------------------------------- M1 top if($w1+$nw1 != 0) # only have m1 in layout. this is a no run situation system "print \"===> Error: The nestlist only contains $M1. This is a NORUN situation.\" >> $lg"; system "print \"===> Source Type: $src_type Source Level (new C4) : $M2\" >> $lg"; system "print \"===> #Top level=$M1 #Top pins=$VDD1, #ca=$ca_xy \" >> $lg"; system "print \"===> TotalVias=$totvias, Vias=$vias, BarVias=$bar_vias\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> # $M1=$w1\" >> $lg"; system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1\" >> $lg"; system "print \"\n$progname ended at: \" \`date\` >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; exit(5); else # no m1 wire resistance extracted system "print \"===> Error: No Wire Resistance Was Extracted. May need to adjust beol ERIE contact spacing parmeters.\" >> $lg"; system "print \"===> TotalWires=$w\" >> $lg"; system "print \"===> NonwireResistors=$n, Bad_NonwireResistors=$bn\" >> $lg"; system "print \"===> Nonwire Resistors $nw1 on $M1\" >> $lg"; system "print \"\n$progname ended at: \" \`date\` >> $lg"; close OUTASTAP; close TOPINFO; close VIAOUTGD; close WOUTGD; exit(6);

C.2 #!/usr/bin/perl eval '\ if [ "X$CTEPERLBIN" = "X" ] ; then echo "$0: CTE environment is not initialized! Exiting ..." exit 1 else

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exec $CTEPERLBIN -S $0 $1+"$@" fi' if 0; require "dotsh.pl"; &dotsh ($ENV"CTERC", 'CTEQUIET=1'); system "ulimit -Sd unlimited"; system "ulimit -Ss unlimited"; $progname = "sna.beol.pl"; if(!defined $ARGV[0] || !defined $ARGV[1] || !defined $ARGV[2]|| !defined $ARGV[3]) print "\nERROR Missing In Put Parms\n"; print "USAGE: $progname cellname cellname.erie_netlist rundir biasFile\n\n"; exit 1; $cellname = $ARGV[0]; #Parm 0 -> cell name $netlist = $ARGV[1]; #Parm 1 -> Erie *.eire_netlist file $rd = $ARGV[2]; #Parm 2 -> Netlist Directory $biasFile=$ARGV[3]; #Parm 3 -> EM Project File $min_width = "$rd/$cellname.mw"; #Output file, minimum width per net $geometry = "$rd/$cellname.geo"; #Output file, geometry info of each wire $via_bbox = "$rd/$cellname.bbox"; $log = "$rd/$cellname.sna.log"; $WNET = 0; $wireLayer = 0; $viaLayer = 0; open(LOG,">$log") || die "Error: Program $progname can not open input file $netlist.\n"; $time = localtime; printf LOG "Info: Program $progname started at: $time\n\n"; open(BIAS,"<$biasFile") || die "*ERROR* Program $progname can not open input file $emprj.\n"; while(<BIAS>) if(/RESNOMBIAS/) ($key, $layer, $dash, $bias) = split; if($dash != "-") next; $wireLayer++; $WLAYER$wireLayer = $layer; $W$layerR = 0; $W$layerBIAS = $bias; if(/VIARES/) ($key, $layer, $res) = split; $viaLayer++; $VLAYER$viaLayer = $layer; $V$layerR = 0; $V$layerRES = $res; close BIAS; $wirePattern = "R.*, .*__.* = .* W .*"; $wireResistor = "R.*, .*__.* - .*__.* = .* W .*"; $wireVddL="R.*, VDD! - VDD!__.* = .* W .....";

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$wireVddR="R.*, VDD!__.* - VDD! = .* W ....."; $wireGndL="R.*, GND! - GND!__.* = .* W ....."; $wireGndR="R.*, GND!__.* - GND! = .* W ....."; $viaPattern = "R.*, .*__.* = .* V .*"; $viaResistor = "R.*, .*__.* - .*__.* = .* V .*"; $viaVddL="R.*, VDD! - VDD!__.* = .* V ....."; $viaVddR="R.*, VDD!__.* - VDD! = .* V ....."; $viaGndL="R.*, GND! - GND!__.* = .* V ....."; $viaGndR="R.*, GND!__.* - GND! = .* V ....."; open(NETLIST,"<$netlist") || die "Error: Program $progname can not open input file $netlist.\n"; while(<NETLIST>) # R118, net0113__24 - net0113__25 = 0.0573333 /* W PCout 0.03 1.18 4 1.395 4 */ # <W level width x0 y0 x1 y1> (centerline coords) if(/^$wirePattern/) ($rName, $node1, $dash, $node2, $equal, $rValue, $com1, $rType, $layer, $area, $lowerLevel, $lowerWidth, $highLevel, $highWidth, $xl, $yl, $com2) = split; if(/^$wireResistor/) ($netName, $subnode1) = split('__', $node1); if(/^$wireVddL/ || /^$wireVddR/) $netName = "VDD"; if(/^$wireGndL/ || /^$wireGndR/) $netName = "GND"; $rName = substr($rName, 0, length($rName)-1); $width = $width-2*$W$layerBIAS; #------------ counter-bias "Erie width" $W$layerR++; $existNet = 0; if($WNET != 0) for($i=1; $i<=$WNET; $i++) if($W$i eq $netName) $existNet = 1; if($existNet) $existLayer = 0; for($j=1; $j<=$W$netNameLAYER; $j++) if($W$netName$j eq $layer) $existLayer = 1; if($existLayer) #------------ wire, old net and layer $W$netName$layerR++; if($width < $W$netName$layerMINW) $W$netName$layerMINW = $width; $W$netName$layerMINR = $rName; else #------------ wire, old net, new layer $W$netNameLAYER++; $layerIndex = $W$netNameLAYER; $W$netName$layerIndex = $layer; $W$netName$layerMINW = $width; $W$netName$layerMINR = $rName; $W$netName$layerR = 1;

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else #------------ wire, new net and layer $WNET++; $netIndex = $WNET; $W$netIndex = $netName; $W$netNameLAYER = 1; $layerIndex = $W$netNameLAYER; $W$netName$layerIndex = $layer; $W$netName$layerMINW = $width; $W$netName$layerMINR = $rName; $W$netName$layerR = 1; $rIndex = $W$netName$layerR; $W$netName$layer$rIndex = $rName; $W$rNameR = $rValue; $W$rNameW = $width; $W$rNameN1 = $node1; $W$rNameN2 = $node2; if($yl == $yh) #------------ horizontal wire $W$rNameXL = $xl; #------------ xl, yl, xh, yh are center line coordinates $W$rNameYL = $yl-$width/2; #------------ XL, YL, XH, YH are bonding box coordinates $W$rNameXH = $xh; $W$rNameYH = $yh+$width/2; else #------------ vertical wire $W$rNameXL = $xl-$width/2; $W$rNameYL = $yl; $W$rNameXH = $xh+$width/2; $W$rNameYH = $yh; # R543, VDD!__2336 - VDD! = 0.0396 /* V CAnew 0.0261 PCout 0.06 M1out 0.1 3.15500 3.51000 */ # <V level area lowseglev lowsegwid hiseglev hisegwid viaxl viayl> # if(/^$viaResistor/ || /^$viaVddL/ || /^$viaVddR/ || /^$viaGndL/ || /^$viaGndR/) if(/^$viaPattern/) ($rName, $node1, $dash, $node2, $equal, $rValue, $com1, $rType, $layer, $area, $lowerLevel, $lowerWidth, $highLevel, $highWidth, $xl, $yl, $com2) = split; $rName = substr($rName, 0, length($rName)-1); if(/^$viaResistor/) ($netName, $subnode1) = split('__', $node1); if(/^$viaVddL/ || /^$viaVddR/) $netName = "VDD"; if(/^$viaGndL/ || /^$viaGndR/) $netName = "GND"; $V$layerR++; $existNet = 0; if($VNET != 0) for($i=1; $i<=$VNET; $i++) if($V$i eq $netName) $existNet = 1;

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if($existNet) $existLayer = 0; for($j=1; $j<=$V$netNameLAYER; $j++) if($V$netName$j eq $layer) $existLayer = 1; if($existLayer) #------------ via, old net and layer $V$netName$layerR++; else #------------ via, old net, new layer $V$netNameLAYER++; $layerIndex = $V$netNameLAYER; $V$netName$layerIndex = $layer; $V$netName$layerR = 1; else #------------ via, new net and layer $VNET++; $netIndex = $VNET; $V$netIndex = $netName; $V$netNameLAYER = 1; $layerIndex = $V$netNameLAYER; $V$netName$layerIndex = $layer; $V$netName$layerR = 1; $rIndex = $V$netName$layerR; $V$netName$layer$rIndex = $rName; $V$rNameR = $rValue; $V$rNameA = $area; $V$rNameN1 = $node1; $V$rNameN2 = $node2; $V$rNameLL = $lowerLevel; $V$rNameHL = $highLevel; $V$rNameLW = $lowerWidth; $V$rNameHW = $highWidth; $V$rNameXL = $xl; $V$rNameYL = $yl; close NETLIST; $time = localtime; if($WNET == 0 && $VNET==0) print LOG "Warning: Program $progname did not find any net in Erie's netlist file $netlist\n"; print LOG "Info: Program $progname ended at $time"; exit 2; else $net = $WNET + $VNET; print LOG "Info: Program $progname found $net nets in $netlist\n\n";

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open(MIN_W,">$min_width") || die "Error: Program $progname can not open output file $min_width.\n"; for($netIndex=1; $netIndex<=$WNET; $netIndex++) #---------------- output minimum width per net $netName = $W$netIndex; printf MIN_W "%s\t", $netName; for($layerIndex=1; $layerIndex<= $W$netNameLAYER; $layerIndex++) $layer = $W$netName$layerIndex; printf MIN_W "%s\t%.5f\t%s\t", $layer, $W$netName$layerMINW, $W$netName$layerMINR; printf MIN_W "\n", $netName; close MIN_W; open(GEO,">$geometry")|| die "Error: Program $progname can not open output file $geometry.\n"; for($netIndex=1; $netIndex<=$WNET; $netIndex++) #---------------- output wire geometry $netName = $W$netIndex; for($layerIndex=1; $layerIndex<= $W$netNameLAYER; $layerIndex++) $layer = $W$netName$layerIndex; $rTotal = $W$netName$layerR; for($rIndex=1; $rIndex <= $rTotal; $rIndex++) $rName = $W$netName$layer$rIndex; printf GEO "%s\t%s\t%s\t%s\t%s\t%.5f\t%.5f\t%.5f\t%.5f\t%.5f\t%.5f\n", $netName, $layer, $W$rNameN1, $W$rNameN2, $rName, $W$rNameR, $W$rNameW, $W$rNameXL, $W$rNameYL, $W$rNameXH, $W$rNameYH; close GEO; open(BBOX,">$via_bbox")|| die "Error: Program $progname can not open output file $geometry.\n"; for($netIndex=1; $netIndex<=$VNET; $netIndex++) #---------------- output via geometry $netName = $V$netIndex; for($layerIndex=1; $layerIndex<= $V$netNameLAYER; $layerIndex++) $layer = $V$netName$layerIndex; $rTotal = $V$netName$layerR; for($rIndex=1; $rIndex <= $rTotal; $rIndex++) $rName = $V$netName$layer$rIndex; printf BBOX "%s\t%s\t%s\t%s\t%s\t%.5f\t%.5f\t%s\t%.5f\t%s\t%.5f\t%.5f\t%.5f\t\n", $netName, $layer, $V$rNameN1, $V$rNameN2, $rName, $V$rNameR, $V$rNameA, $V$rNameLL, $V$rNameLW, $V$rNameHL, $V$rNameHW, $V$rNameXL, $V$rNameYL;

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close BBOX; for($i=1; $i<=$wireLayer; $i++) $layer = $WLAYER$i; if($W$layerR != 0) printf LOG "Info: $W$layerR wires on $layer level.\n"; else printf LOG "Warning: There is no wire on $layer level.\n"; printf LOG "\n"; for($j=1; $j<=$viaLayer; $j++) $layer = $VLAYER$j; if($V$layerR != 0) printf LOG "Info: $V$layerR vias on $layer level.\n"; else printf LOG "Warning: There is no via on $layer level.\n"; $time = localtime; printf LOG "\nInfo: Program $progname ended at: $time\n"; close LOG; exit 0; C.3 #!/usr/bin/perl -w use strict; eval '\ if [ "X$CTEPERLBIN" = "X" ] ; then echo "$0: CTE environment is not initialized! Exiting ..." exit 1 else exec $CTEPERLBIN -S $0 $1+"$@" fi' if 0; require "dotsh.pl"; &dotsh ($ENV"CTERC", 'CTEQUIET=1'); system "ulimit -Sd unlimited"; system "ulimit -Ss unlimited"; if(!defined $ARGV[0] || !defined $ARGV[1] || !defined $ARGV[2]|| !defined $ARGV[3]) print "\nERROR Missing In Put Parms\n"; print "USAGE: $0 cellname einstlt_dir erie_dir run_dir em.sna.PrjFile\n\n"; exit(5);

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#--------------------------------------- # Section 1 global variables and flow #--------------------------------------- my $cellname = $ARGV[0]; #Parm 0 -> cell name my $einstlt_dir = $ARGV[1]; #Parm 1 -> EinsTLT directory my $erie_dir = $ARGV[2]; #Parm 2 -> Erie directory my $run_dir = $ARGV[3]; #Parm 3 -> Working directory my $projectFile = $ARGV[4]; #Parm 4 -> SNA EM Project File my $einstlt_early = "$einstlt_dir/$cellname.nets.early"; #Input file, EinsTLT .net.early file my $einstlt_late = "$einstlt_dir/$cellname.nets.late"; #Input file, EinsTLT .net.late file my $einstlt_nets = "$einstlt_dir/$cellname.nets"; my $einstlt_phase = "$einstlt_dir/$cellname.phase"; #Input file, EinsTLT phase file my $erie_netlist = "$erie_dir/$cellname.erie_netlist"; #Input file, Erie extracted netlist my $min_width = "$run_dir/$cellname.mw"; #Input file, minimum width per net my $geometry = "$run_dir/$cellname.geo"; #Input file, geometry info of each wire my $via_bbox = "$run_dir/$cellname.bbox"; #Input file, bounding box of vias my $report = "$run_dir/$cellname.sna.filter.report"; #Output file, report file my $log = "$run_dir/$cellname.sna.filter.log"; #Output file, log file my $vdd = 1.10; # could be a parameter in project file my @nets = (); my @layers = (); my @badNets = (); my @badIdcNets = (); my @badIrmsNets = (); my (%netLayers, %mw); my (%cap, %tau, %freq, %sf, # parameter hash, key is net name %clocks, # frequency hash, key is clock phase %Idc, %Irms, # current hash, key is bad net name %IdcForm, %IrmsForm, %IdcMin, %IrmsMin # formula hash, key is layer name ); open(LOG,">$log") || die "Error: Program $0 can not write to $log.\n"; my $time = localtime(); printf LOG "Info: Program $0 started at: $time\n\n"; ReadProjectFile(); # get formulas for Idc and Irms limit per layer ReadPhaseFile(); # get frequency per net ReadNetsFile(); # get load capacitance and current duration per net #ReadMinWidth(); # get minimum width per net CheckNetIdcIrms(); # chech Idc and Irms per net ReportBadNet(); # report em violations $time = localtime(); printf LOG "\nInfo: Program $0 ended at: $time\n";

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close LOG; exit(0); #--------------------------------------- # Section 2 read input files #--------------------------------------- sub ReadProjectFile my ($layer, @columns); open(PROJ, $projectFile) || die "Program $0 failed to open $projectFile.\n"; #M1 0.516*(W-0.038) 4.44*(W-0.038)*sqrt(2.11+3.81/(W-0.038) 0.027 2.00 while(<PROJ>) s/TBD/1000/g; # set big limit if "TBD" s/W/\$width/g; @columns = split; $layer = shift @columns; push @layers, $layer; ($IdcForm$layer, $IrmsForm$layer, $IdcMin$layer, $IrmsMin$layer) = @columns; close(PROJ); sub ReadPhaseFile my ($clock, $Tl, $Tt, $period); my $start = 0; open(PHASE,"<$einstlt_phase") || die "Error: Program $0 failed to open $einstlt_phase.\n"; #DESIGN_CYCLE_TIME 166 #*Release Level: 3.2 and Compiled: Thu Oct 12 23:34:04 2000 #*--------------------------------------------- #DCDC 0 83 166 while(<PHASE>) last if (/^\*-10/ && $start == 1); if(/^DESIGN_CYCLE_TIME/) ($clock, $period) = split; $clocksdefault = 1.0 / $period; next; if(/^\*-10/ && $start == 0) $start = 1; next; if($start == 1) ($clock, $Tl, $Tt, $period) = split; if($period != 0.0) $clocks$clock = 1.0 / $period; else $clocks$clock = 1e+9; next; close PHASE;

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sub ReadNetsFile my ($clock, $edge, $tau, $freq, $net, @items); my $foundDash = 0; my $foundDot = 0; my $firstPhase = 1; open(NETS,"<$einstlt_nets") || die "Error: Program $0 failed to open $einstlt_nets.\n"; #Driver_Pin Out CLoad Pin_Cap Limit Cnear Cfar Res Ceff CELL PWR Func Net #----------------------------------------------------------------------------------------------------------------------------------- #I2@I1@N1:d 1 107.50 7.50 2000.00 0.00 107.50 0.02250 - cr_invert_hln_19.74_9.75 out #......................ATr......ATf......SLwr......SLwf......SLKr......SLKf......................................................... #Mext@L 43.95 43.85 24.49 17.84 16.53 16.23 #Pext@L 43.95 43.85 24.49 17.84 16.53 16.23 #Bext@L 43.95 43.85 24.49 17.84 16.53 16.23 while(<NETS>) if(/^-10/) $foundDash = 1; $foundDot = 0; next; if($foundDash) @items = split; $net = $items[@items-1]; unshift @nets, $net; $cap$net = $items[2]; # load capacitance per net $sf$net = 0.25; # default switching factor $freq$net = $clocksdefault; # default frequency $tau$net = 1.0 / $freq$net; # default current duration $foundDash = 0; if(/^\.10/) $foundDot = 1; next; if($foundDot) @items = split; if($items[0] =~ /(\+|-)/) $sf$net = 2.0; # if clock, set switching factor to 2 chop($items[0]); else $items[0] =~ s/(@.*$)//; $freq = $clocks$items[0]; # get phase frequency

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# use same freq for Idc and Irms ? $tau = $items[3]*$items[4]/($items[3]+$items[4]) + 0.01; # equivalent tau if($firstPhase == 1) $freq$net = $freq; $tau$net = $tau; $firstPhase = 0; else if($freq$net/$tau$net < $freq/$tau) # choose the biggest freq/tau $freq$net = $freq; $tau$net = $tau; # end if($foundDot) close NETS; sub ReadMinWidth my ($net, $layer, @items); open(MW, $min_width)|| die "Error: Program $0 failed to open $min_width.\n"; #b_clk M1 0.03500 R401 M2 0.03500 R40 while(<MW>) # read each line @items = split; $net = shift @items; # first one in line is net name @layers = (); while(@items !=0) $layer = shift @items; # layer per net $mw$net$layer = shift @items; # minimum wire width per layer push @ $netLayers$net , $layer; shift @items; #--------------------------------------- # Section 3 process data #--------------------------------------- sub CheckNetIdcIrms foreach my $net (@nets) my $badDC = 0; my $badRMS = 0; my $Idc = $cap$net * ($sf$net/2) * $freq$net * $vdd; # calculate Idc per net

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my $Irms = $cap$net * $vdd * sqrt(2.0 / 3.0 * $sf$net * $freq$net / $tau$net); # calculate Irms per net foreach my $layer (@layers) if($Idc > $IdcMin$layer) $badDC = 1; # report an Idc violation; if($Irms > $IrmsMin$layer) $badRMS = 1; # report an Irms violation; # end of checking all layers per net #--------------------------------------- needs min_width per net info --------------------- # my @layers = $netLayers$net; # get real layers per net # foreach my $layer (@layers) # # if($Idc > $IdcMin$layer ) # # my $width = $mw$net$layer; # my $IdcLimit = eval IdcForm$layer; # calculate real Idc limit based on min width # if($Idc > $IdcLimit) # # $badDC = 1; # push @ $Idc$netLAYER , $layer, $Idc; # # # if($Irms > $IrmsMin$layer ) # # my $width = $mw$net$layer; # my $IrmsLimit = eval IdcForm$layer; # calculate real Irms limit based on min width # if($Irms > $IrmsLimit) # # $badRMS = 1; # push @ $Irms$netLAYER , $layer, $Irms; # # # # end of checking all layers per net #------------------------------------------------------------------------------------------- if($badDC) push @badIdcNets, $net; $Idc$net = $Idc; if($badRMS) push @badIrmsNets, $net; $Irms$net = $Irms; if($badRMS || $badDC) push @badNets, $net; # end of checking all nets #--------------------------------------- # Section 4 summary report #---------------------------------------

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sub ReportBadNet my ($net, $Idc, $Irms, $cap); my $total = @nets; my $badDC = @badIdcNets; my $badRMS = @badIrmsNets; my $dc = "$cellname.sna.filter.dc"; # file that only has bad Idc nets names my $rms = "$cellname.sna.filter.rms"; # file that only has bad Irms nets names print "\nTotal Nets Checked: $total\n"; print "\nBad Idc nets: $badDC\tBad Irms nets: $badRMS\n"; printf LOG "\nTotal Nets Checked: $total\n"; printf LOG "\nPossible $badDC nets that violates Idc limit:\n"; open(DC, ">$dc") || die "Error: Program $0 can not write to $dc.\n"; foreach my $net (@badIdcNets) printf DC "%s\t", $net; $Idc = $Idc$net; printf LOG "\nNet: $net\tIdc: %.4f\n", $Idc; $cap = $Idc / ($sf$net*$freq$net*$vdd); printf LOG "Possible fix by changing Cload to %.3f\n", $cap; printf LOG "For M1, possible fix by changing wire width to %.3f\n",CalculateIdcWidth(0.516, 0.038, $Idc) ; printf LOG "For M2, M3, and M4, possible fix by changing wire width to %.3f\n", CalculateIdcWidth(0.729, 0.043, $Idc); printf LOG "For B1 and B2, possible fix by changing wire width to %.3f\n", CalculateIdcWidth(1.61, 0.08, $Idc); printf LOG "For EA and EB, possible fix by changing wire width to %.3f\n", CalculateIdcWidth(2.90, 0.09, $Idc); printf LOG "For IA and IL, possible fix by changing wire width to %.3f\n", CalculateIdcWidth(6.42, 0.09, $Idc); printf LOG "For LB, possible fix by changing wire width to %.3f\n", CalculateIdcWidth(1.63, 0.06, $Idc); close DC; open(RMS, ">$rms") || die "Error: Program $0 can not write to $rms.\n"; printf LOG "\n\nPossible $badRMS nets that violates Irms limit:\n"; foreach my $net (@badIrmsNets) printf RMS "%s\t", $net; $Irms = $Irms$net; printf LOG "\nNet: $net\tIrms: %.4f\n", $Irms; $cap = $Irms / $vdd / sqrt($sf$net * $freq$net / $tau$net); printf LOG "Possible fix by changing Cload to %.3f\n", $cap; printf LOG "For M1, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.038, 2.11, 3.81, $Irms, 4.44); printf LOG "For M2, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.043, 1.30, 3.45, $Irms, 3.09); printf LOG "For M3, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.043, 0.90, 3.13, $Irms, 2.99); printf LOG "For M4, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.043, 0.69, 2.91, $Irms, 2.82);

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printf LOG "For B1, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.08, 0.53, 2.87, $Irms, 3.99); printf LOG "For B2, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.08, 0.40, 2.63, $Irms, 6.19); printf LOG "For EA, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.09, 0.28, 2.50, $Irms, 8.22); printf LOG "For EB, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.09, 0.23, 2.36, $Irms, 8.22); printf LOG "For IA, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.09, 0.14, 2.22, $Irms, 11.9); printf LOG "For IL, possible fix by changing wire width to %.3f\n", CalculateIrmsWidth( 0.09, 0.10, 1.99, $Irms, 11.9); close RMS; sub CalculateIdcWidth # Idc = a(w-delta) my ($a, $delta, $Idc) = @_; return($Idc/$a + $delta); sub CalculateIrmsWidth # Irms = d*(w-delta)*sqrt(a+b/(w-delta)) my ($delta, $a, $b, $Irms, $d) = @_; return($delta + (sqrt($b*$b + 4.0*$a*$Irms*$Irms/$d/$d) - $b) / (2.0*$a)); #-------------------------------------------- # Signal Net Electromigration Analysis # First Part, Filter out potential bad nets