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JFET and OpAmp
Pyroelectric detectors of InfraTec use for the first signal processing stage Junction Field Effect Transistors (JFET) and CMOS Operational Amplifiers (OpAmp) built-in in the detector housing. Specifications are adapted for high-impedance pyroelectric elements.
1 Standard JFET – For single and multi color detectors
Features Very low voltage and current noise
High input impedance
Full performance from low-voltage power supply, down to 2.5 V
Low Gate leakage current for improved system accuracy
Absolute maximum ratings Gate-Source / Gate-Drain voltage: -50 V
Power dissipation: 50 mW
Specifications (TA = 25 °C unless otherwise noted)
Parameter Symbol Test Condition Min Typ Max UnitStatic
Gate-Source Breakdown Voltage -V(BR)GSS IG = -1 µA, VDS = 0 V 50 60 V
Gate-Source Cutoff Voltage -VGS(off) ID = 0.1 µA, VDS = 15 V 0.4 1.5Saturation Drain Current IDSS VDS = 15 V, VGS = 0 V 0.5 1.5 mA
Gate Reverse Current -IGSS VDS = 0 V, VGS = -30 V, TA = 25 °C 2 pA
VDS = 0 V, VGS = -30 V, TA = 150 °C 100 nAGate Operating Current -IG ID = 0.1 mA, VDG = 15 V 2
pADrain Cutoff Current ID(off) VDS = 15 V, VGS = -5 V 50Gate-Source Forward Voltage VGS(F) IG = 1 mA, VDS = 0 V 0.7 V
Dynamic Common-Source Forward Transconductance
gfs VDS = 15 V, VGS = 0 V, f = 1 kHz
0.8 2.2 2.4 mS
Common-Source Output Transconductance
gos 15 µS
Drain-Source On-Resistance rDS(on) VDS = 0 V, VGS = 0 V, f = 1 kHz 1,700 Common-Source Input Capacitance
Ciss VDS = 15 V, VGS = 0 V, f = 1 MHz
3.5 7pF
Common-Source Reverse Transfer Capacitance
Crss 1.2 3
Equivalent Input Noise Voltage en VDS = 10 V, VGS = 0 V, f = 1 kHz 6 nV/Hz
1
JFET and OpAmp
Standard JFET Specifications (TA = 25 °C unless otherwise noted)
10
0
8
6
4
2
0 –5–4–3–2–1
5
4
1
3
2
0
Drain Current and Transconductancevs. Gate-Source Cutoff Voltage
VGS(off) – )V(egatloVffotuCecruoS-etaG
IDSS @V DS = 10 V,V GS = 0 Vgfs @V DS = 10 V,V GS = 0 Vf = 1 kHz
gfs
IDSS
gfs
– Forward
Transconductance(m
S)
I DSS
– Sa
tura
tion
Dra
in C
urre
nt (m
A)
0.1 pA
1 pA
10 pA
100 pA
1 nA
10 nA
810 12 03426
Gate Leakage Current
VDG – Drain-Gate Voltage (V)
IGSS @ 125 C
IGSS @ 25 C
TA = 125 C
TA = 25 C
500 mA
500 mA
ID = 100 mA
ID = 100 mAI G–
Gat
e Le
akag
e (A
)
© 2001 Vishay Siliconix
11.010.0
2
1.6
0.8
0.4
0
Common-Source Forward Transconductancevs. Drain Current
ID – Drain Current (mA)
TA = –55 C
125 C
VGS(off) = –1.5 V
1.2
VDS = 10 Vf = 1 kHz
25 C
g fs
– Fo
rwar
dTr
ansc
ondu
ctan
ce(m
S)
500
0 –0.3–0.2–0.1 –0.4 –0.5
400
300
200
100
0
Transfer Characteristics
VGS – Gate-Source Voltage (V)
TA = –55 C
125 C
VGS(off) = –0.7 V VDS = 10 V
25 C
I D–
Dra
in C
urre
nt(
µA)
k001k100101 10 k
20
16
12
8
4
0
Equ iva lent Inpu t No ise Vo ltage vs. F requency
f – Frequency (Hz)
VDS = 10 V
ID = 100 mA
ID = IDSS
en–
Noi
seVo
ltage
nV/
Hz
11.00.01
200
160
120
80
40
0
ID – Drain Current (mA)
AV
gfs RL1 RLgos
RL10 VID
Assume V DD = 15 V, V DS = 5 V
VGS(off ) = –0.7 V
–1.5 V
Circuit Voltage Gain vs. Drain Current
A V–
Volta
ge G
ain
2
JFET and OpAmp
2 Special JFET – Design for single and multi color detectors (on request)
Benefits Reliable operation at high temperature or increased ionizing radiation
Disadvantage related to standard JFET Lower gain; higher output impedance
Features Ultra high input impedance
Low Gate leakage current for improved system accuracy
Absolute maximum ratings Gate-Source / Gate-Drain voltage: -50 V
Power dissipation: 50 mW
Specifications (TA = 25 °C unless otherwise noted)
Parameter Symbol Test Condition Min Typ Max UnitStatic
Gate-Source Breakdown Voltage -V(BR)GSS IG = -1 µA, VDS = 0 V 40 50 V
Gate-Source Cutoff Voltage -VGS(off) ID = 0.1 µA, VDS = 15 V 0.4 1.5Saturation Drain Current IDSS VDS = 15 V, VGS = 0 V 30 90 µA
Gate Reverse Current -IGSS VDS = 0 V, VGS = -20 V, TA = 25 °C 1 pA
VDS = 0 V, VGS = -20 V, TA = 150 °C 2.5 nAGate Operating Current -IG ID = 0.1 mA, VDG = 15 V 0.2
pADrain Cutoff Current ID(off) VDS = 15 V, VGS = -5 V 0.2 10Gate-Source Forward Voltage VGS(F) IG = 1 mA, VDS = 0 V 0.7 V
Dynamic Common-Source Forward Transconductance
gfs VDS = 15 V, VGS = 0 V, f = 1 kHz
70 175 210 µS
Common-Source Output Transconductance
gos
3 µS
Drain-Source On-Resistance rDS(on) VDS = 0 V, VGS = 0 V, f = 1 kHz 18 kCommon-Source Input Capacitance
Ciss VDS = 15 V, VGS = 0 V, f = 1 MHz
2 3pF
Common-Source Reverse Transfer Capacitance
Crss 0.9 1.5
Equivalent Input Noise Voltage en VDS = 10 V, VGS = 0 V, f = 1 kHz 15 nV/Hz
3
JFET and OpAmp
Special JFET Specifications (TA = 25 °C unless otherwise noted)
© 2001 Vishay Siliconix
4
JFET and OpAmp
3 OpAmp2 – CMOS very low power OpAmp for single and multi color detectors
LME-335, /-337, /-341, /-345, /-351, /-353, /-392, /-553, /-541, /-551; LIM-052, /-054, /-162, /-262; LMM-242, /-244; LFP-3041L-337; LFP-3950-337; LFP-80105-337 Features Single [(4.5 ... 16) V] and split supply [(±2.2 ... ±8) V] operation
Low supply current; very low input bias current
Rail-to-Rail output swing; high voltage gain
Absolute maximum ratings Supply voltage (V+ - V-): 16V
Differential input voltage: ± supply voltage
Voltage at output pin: (V-) -0.3 V ... (V+) +0.3 V
Current at input pin: ±5 mA
Current at output pin: ±30 mA
Current at power supply pin: ±40 mA
Power dissipation: 10 mW
Specifications (TA = 25 °C; V+ = 5 V; V- = -5 V; RL > 1 MΩ unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit
Static Input Offset Voltage VOS 200 1500 µVInput Bias Current IB 1 60 pAInput Offset Current IOS 0.5 60 pACommon Mode Rejection Ratio CMRR -5.0 V VIC 2.7 V 75 88 dBInput Common-Mode VoltageRange
VICR -5
to 4-5.3
to 4,2V
Large Signal Voltage Gain AV RL = 1 M 3000 V/mV
RL = 100 k 45 650 V/mV
positive peak Output Swing
negative peak
VO
RL = 1 M to Gnd RL = 100 k to Gnd
4.98
V4,9 4.93
RL = 1 M to Gnd RL = 100 k to Gnd
-4.99 -4.85 -4.91
Supply Current IS VO = 0V, No Load 80 125 µADynamic
Slew Rate SR VO = ± 1.9V, RL = 100 k, CL =100pF
70 120 V/ms
Gain-Bandwidth Product GBW 210 kHzPhase Margin m 63 Deg
Equivalent Input Noise Voltage Vn f = 1 kHz 19 nV/HzEquivalent Input Noise Current In f = 1 kHz 0.6 fA/Hz
5
JFET and OpAmp
OpAmp2 Specifications
10
5
30
025 45 65 85II
Ba
nd
IIO
–In
pu
tB
ias
an
dIn
pu
tO
ffs
et
Cu
rre
nts
–p
A
20
15
25
INPUT BIAS AND INPUT OFFSET CURRENTS†
vsFREE-AIR TEMPERATURE
35
105 125
IIB
IIO
VDD± = ±2.5 VVIC = 0VO = 0RS = 50 Ω
TA – Free-Air Temperature – °C
I IB
I IO
IDD
–S
up
ply
Cu
rre
nt
–u
A
SUPPLY CURRENT†
vsSUPPLY VOLTAGE
| VDD ± | – Supply Voltage – V
I DD
Aµ
120
80
40
00 1 2 3 4 5
160
200
240
6 7 8
TA = 25°C
TA = 125°C
VO = 0No Load
TA = –55°C
TA = –40°C
EQUIVALENT INPUT NOISE VOLTAGEvs
FREQUENCY
f – Frequency – Hz
VN
–E
qu
iva
len
tIn
pu
tN
ois
eV
olt
ag
e–
nv
//H
zn
V/
Hz
Vn
40
20
10
0
60
30
50
101 102 103 104
VDD± = ±5 VRS = 20 ΩTA = 25°C
© 2001 Texas Instruments Incorporated
0.6
0.4
0.2
00 1 2 3
VO
L–
Lo
w-L
ev
elO
utp
utV
olt
ag
e–
V
0.8
1
LOW-LEVEL OUTPUT VOLTAGE‡
vsLOW-LEVEL OUTPUT CURRENT
1.2
4 5
VIC = 0VIC = 1.25 V
VIC = 2.5 V
VDD = 5 VTA = 25°C
V OL
IOL – Low-Level Output Current – mA
VO
H–
Hig
h-L
ev
elO
utp
utV
olt
ag
e–
V
HIGH-LEVEL OUTPUT VOLTAGE†‡
vsHIGH-LEVEL OUTPUT CURRENT
| IOH| – High-Level Output Current – µA
V OH
3
2
1
00 200 400
4
5
600 800
VDD = 5 V
TA = –40°C
TA = 25°C
TA = 125°C
TA = –55°C
Dif
fere
nti
alG
ain
–V
/m
V
DIFFERENTIAL GAIN‡
vsLOAD RESISTANCE
RL – Load Resistance – kΩ
104
103
102
10
1 101 102 103
VO (PP) = 2 VTA = 25°C
VDD = ±5 V
VDD = 5 V
om
–P
ha
se
Ma
rgin
φm
f – Frequency – Hz
LARGE-SIGNAL DIFFERENTIAL VOLTAGEAMPLIFICATION AND PHASE MARGIN†
vsFREQUENCY
AV
D–
La
rge
-Sig
na
lDif
fere
nti
al
AV
D Vo
lta
ge
Am
pli
fic
ati
on
–d
B
20
80
60
40
0
–20
–40103 104 105 106 107
180°
135°
90°
45°
0°
–45°
–90°
Gain
VDD = 5 VRL = 50 kΩCL= 100 pFTA = 25°C
Phase Margin
om
–P
ha
se
Ma
rgin
PHASE MARGINvs
LOAD CAPACITANCE
CL – Load Capacitance – pF
mφ
101 102 103 105
75°
60°
45°
30°
15°
0°
Rnull = 200 Ω
Rnull = 500 Ω
Rnull = 50 Ω
Rnull = 0
TA = 25°C
Rnull = 10 Ω
104
50 kΩ
50 kΩ
VDD –
VDD+Rnull
CL
VI+–
Rnull = 100 Ω
Ga
inM
arg
in–
dB
GAIN MARGINvs
LOAD CAPACITANCE
CL – Load Capacitance – pF
20
10
5
0
15
101 102 103 105
Rnull = 100 Ω
TA = 25°C
Rnull = 50 Ω
104
Rnull = 500 Ω
Rnull = 200 Ω
Rnull = 0
Rnull = 10 Ω
6
JFET and OpAmp
4 OpAmp3 – CMOS very low power OpAmp for use in single supply detectors and low current detectors
LME-336, /-346, /-352, LIE-235, /-241, /-245, /-251 Features Single supply [(2.7 ... 10) V] operation and split supply [(±1.35 … ±5) V] operation
Ultra Low supply current; low input bias current
Rail-to-Rail output swing; high voltage gain
Absolute maximum ratings Single-Supply voltage (V+ - V-/GND): 10V
Differential input voltage: ± supply voltage
Voltage at output pin: (V-) -0.3 V ... (V+) +0.3 V
Current at output pin: ±50 mA
Current at power supply pin: ±50 mA
Power dissipation: 10 mW (RL≥10kOhm)
Specifications (TA = 25 °C; V+ = 3 V; V- = 0 V; RL > 10 kΩ unless otherwise noted)
Parameter Symbol Test Condition Min Typ Max UnitStatic
Input Offset Voltage VOS 0.47 3 mVInput Bias Current IB 1 60 pAInput Offset Current IOS 0.5 60 pACommon Mode Rejection Ratio CMRR 0.0 V VIC 1.7 V 65 83 dBInput Common-Mode Voltage Range
VICR 0
to 20
to 2,2 V
Large Signal Voltage Gain AV RL = 1 M 600 V/mV
RL = 10 k 3 7 V/mV
positive peak Output Swing
negative peak
VO
RL = 1 M to Gnd RL = 10 k to Gnd
2.94
V2.85
RL = 1 Mto V+ RL = 10 k to V+
0.015 0,15
Supply Current IS VO = +1.5 V, No load 11 25 µADynamic
Slew Rate SR VO = 1.1 to 1.9V (RL = 10 k, CL =100pF to 1.5V)
10 25 V/ms
Gain-Bandwidth Product GBW 56 kHzPhase Margin m 56 DegEquivalent Input Noise Voltage Vn f = 1 kHz 22 nV/√HzEquivalent Input Noise Current In f = 1 kHz 0.6 fA/√Hz
7
JFET and OpAmp
OpAmp3 Specifications
IIB
an
dII
O–
Inp
ut
Bia
sa
nd
Inp
ut
Off
se
tC
urr
en
ts–
pA
INPUT BIAS AND INPUT OFFSET CURRENTS†
vsFREE-AIR TEMPERATURE
I IB
I IO
TA – Free-Air Temperature – °C
50
40
20
10
0
90
30
25 45 65 85
70
60
80
100
105 125
IIB
IIO
VDD± = ±2.5 VVIC = 0VO = 0RS = 50 Ω
–H
igh
-Le
ve
lOu
tpu
tVo
lta
ge
–V
HIGH-LEVEL OUTPUT VOLTAGE†‡
vsHIGH-LEVEL OUTPUT CURRENT
V OH
| IOH | – High-Level Output Current – µA
2
1.5
1
00 200 400
2.5
3
600 800
VDD = 3 V
TA = –40°C
0.5
TA = 25°C
TA = 85°C
TA = 125°C
–L
ow
-Lev
elO
utp
utV
olt
ag
e–
V
LOW-LEVEL OUTPUT VOLTAGE†‡
vsLOW-LEVEL OUTPUT CURRENT
V OL
IOL – Low-Level Output Current – mA
0.4
0.2
1.2
00 1 2 3
0.8
0.6
1
1.4
4 5
TA = 85°C
TA = – 40°C
TA = 25°C
TA = 125°C
VDD = 3 VVIC = 1.5 V
© 2001 Texas Instruments Incorporated
–M
ax
imu
mP
ea
k-t
o-P
ea
kO
utp
utV
olt
ag
e–
V
f – Frequency – Hz
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE‡
vsFREQUENCY
VO
(PP
)
4
2
1
5
3
0
RI = 10 kΩTA = 25°C
VDD = 5 V
VDD = 3 V
102 103 104
–S
ho
rt-C
irc
uit
Ou
tpu
tCu
rre
nt
–m
A
SHORT-CIRCUIT OUTPUT CURRENTvs
SUPPLY VOLTAGE
I OS
VDD – Supply Voltage – V
10
6
2
2 3 4 5
14
16
6 7 8
12
8
4
0
–2
VID = –100 mV
VID = 100 mV
VO = VDD/2VIC = VDD/2TA = 25°C
LARGE-SIGNAL DIFFERENTIALVOLTAGE AMPLIFICATION†‡
vsFREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
–L
arg
e-S
ign
alD
iffe
ren
tia
lVo
lta
ge
AV
DA
mp
lifi
ca
tio
n–
V/m
V
– 50 –25 0 25 50 75 100
RL = 10 kΩ
RL = 1 MΩ
103
102
101
1
VDD = 3 VVIC = 1.5 VVO = 0.5 V to 2.5 V
52157–
–E
qu
ival
entI
np
utN
ois
eV
olt
age
–
f – Frequency – Hz
EQUIVALENT INPUT NOISE VOLTAGE†
vsFREQUENCY
Vn
nV
/H
z
40
30
20
0
60
50
10
VDD = 3 VRS = 20 ΩTA = 25°C
70
80
101 102 103 104
–S
up
ply
Cu
rren
t–
Aµ
I DD
VDD – Supply Voltage – V
SUPPLY CURRENT†
vsSUPPLY VOLTAGE
VO = VDD/2VIC = VDD/2No Load
TA = 25°C
TA = 85°C
TA = –40°C
15
10
5
0 2 4 6
20
25
30
8 100
–U
nit
y-G
ain
Ba
nd
wid
th–
kH
z
UNITY-GAIN BANDWIDTHvs
LOAD CAPACITANCE
CL – Load Capacitance – pF
B1
60
10
40
0
80
50
70
20
30
101 102 103 104 105
TA = 25°C
106
8