jes7 2 1 - ESRGroups J. Electrical Systems 7-2 (2011): 131-148 Regular paper Study of a new DC voltage equalising circuit for Five-Level Neutral Point

* Corresponding author: R. Chibani, E-mail: [email protected] 1 Laboratoire de commande des processus ECOLE NATIONALE POLYTECHNIQUE. 10, Rue Hassen BADI. ELHarrach BP182. ALGER. ALGERIE [email protected] ; [email protected] Copyright © JES 2011 on-line : journals/esrgroups.org/jes

Rédha. CHIBANI 1 ElMadjid.

BERKOUK 1 Mohamed

Seghir. BOUCHERIT1

J. Electrical Systems 7-2 (2011): 131-148

Regular paper

Study of a new DC voltage equalising circuit for Five-Level Neutral Point Clamped-Voltage Source Inverter

This paper presents a new clamping bridge to solve capacitor balancing problems in Five-Level Neutral-Point-Clamped Voltage Source Inverter (NPC VSI) and realise the equalisation in the DC capacitor voltage. The voltage balancing circuit consists of four bidirectional switches and two inductances. This solution avoids capacitor unbalancing problem, leads to a simpler implementation and presents high equalization efficiency and increases the reliability of the drive system. Simulation results show the effectiveness of our method. The cascade studied is a two two-level PWM rectifier- five-level NPC VSI- Permanent Magnet Synchronous Machine. Keywords: Multilevel inverter, Neutral Point Clamped, Voltage Source Inverter, Sliding mode, DC capacitor voltage unbalance, Clamping bridge.

1. Introduction The general trend in power electronic devices has been to switch power semiconductors at increasingly high frequency in order to minimize harmonics and reduce passive components sizes. However, the increase in switching frequency increases the switching losses, which become especially significant at high power levels. One of the several methods for decreasing switching losses is the multilevel inverter. This kind of converter offers a high number of switching state so that the inverter output voltage can be stepped in smaller increment. The multilevel inverters are considered today as the most suitable power converters for high voltage capability and high power quality demanding applications with voltage operation above classic semiconductor limits, lower common-mode voltages, near-sinusoidal outputs, together with small dv/dt’s. The multilevel converter has found widespread applications in industry. They can be used for pipeline pumps in the petrochemical industry, fans in the cement industry, pumps in water pumping stations, traction applications in the transportation industry, steel rolling mills in the metals industry, grid integration of renewable energy sources, reactive power compensation and other applications. Multilevel inverter systems are generally classified as diode-clamping inverters, cascade inverters, and flying-capacitor inverters. Among multilevel inverters, the three-level diode-clamped inverter, which is called the neutral-point clamped (NPC) inverter, has been commonly used [1]. But the NPC inverter has a major disadvantage that there will be voltage unbalance in DC capacitors (expense of the divergence of DC capacitor voltages resulting in the collapse of one and rise of the other). This may result in poor quality voltage outputs, affecting the control performance and causing a violation in the safe operating limits leading to inverter malfunctioning. However, it is difficult to control real power flow for balancing the neutral-point (NP) potential. The causes of NP potential drift can be non uniform switching device or DC link

R. CHIBANI et al: Study of a new DC voltage equalising circuit for ...

132

capacitor characteristics or fluctuation due to the irregular and unpredictable charging and discharging in each capacitor [2] [3] [4]. The voltage across the capacitor may grow or decay so that the NP voltage fails to keep the half of the DC link voltage. Therefore, an excessive high voltage may be applied to the switching devices of DC link capacitors and this affects the converter performance due to the generation of uncharacteristic harmonics and the presence of overvoltages across the semiconductor switches. Therefore, the choice of appropriate modulation techniques and the development of advanced neutral point potential control techniques are necessary to overcome the NP potential problems. Some solutions have been proposed, which are based on redundant switching configurations [1] [5-14] or on the addition of zero-sequence voltage components to the output voltage [6]. However, all these methods seem to be not always useful in no-load or low-load operations, when the supplied current tends to zero. In real systems, no-load conditions determine almost always the loss of DC-link capacitors voltages balance, owing to converter non ideality. Unfortunately, these methods modify the output voltage waveform. As the number of inverter-level increases, the problem of capacitor balancing becomes more complex and the solution very drastic. The unbalance DC voltage problem can also be solved by separate DC sources [3] or by adding electronic circuitry. In [15-17], clamping bridges based on transistors and resistors are proposed as a solution to this problem. Disadvantages of this method are the requirement for large power dissipating resistors, high current switches, and thermal management requirements. This method is best suited for systems that are charged often with small currents. This paper deals with a new clamping bridge for the DC capacitor voltage equalisation. It has been proposed to compensate DC-link capacitor voltages fluctuations in a NPC VSI that permits to achieve a correct capacitors voltages sharing, when conventional balancing methods fail. In order to stabilize these DC voltages, we propose in this paper to study the cascade constituted by two three- phase two-level PWM rectifier-clamping bridge - five-level NPC VSI - Permanent Magnet Synchronous Machine. 2. Five-level cascade The global scheme of the cascade is given on the figure 1.

Figure 1. Structure of the cascade proposed


133

2.1. Five-level NPC-VSI modelling The general structure of the three-phase five-level NPC voltage source inverter is shown on the figure 2. It is composed by 24 pairs transistor-diode. Every leg of this inverter includes eight pairs, four on the upper half leg and four on the lower one. The optimal control law is given below:

51 kk BB =

42 kk BB =

63 kk BB = (1)

3217 .. kkkk BBBB =

6548 .. kkkk BBBB =

ksB is the control signal of ksTD . ksTD represents every pair transistor-diode by one bi-directional switch. The voltage of the three-phase A, B, C relatively to the middle point M and using the half leg connection functions b

kMF are given by VXM with x = point A, B or C. )].().([)].().([ 3843017211 ckcc

bkckcc

bkkM UFUUFUFUUFV ++−++= (2)

The input currents of the three-phase five-level inverter using the load currents are given by the following relations:

3312211111 ... iFiFiFi bbbd ++=

3312211112 ... iFiFiFi bbbd

′+

′+

′=

3302201103 ... iFiFiFi bbbd

′+

′+

′=

3302201104 ... iFiFiFi bbbd ++= (3)

43213210 ddddd iiiiiiii −−−−++=

Figure 2. General structure of the three-phase five-level NPC VSI


134

2.2. Control strategy of the inverter This strategy uses four bipolar carriers ( 1pU , 2pU , 3pU , 4pU ). It is characterised by two parameters m the index modulation and r the modulation rate. The algorithm of this strategy can be summarised as follows: Step 1: Determination of the intermediate voltages If 1prefk UV > then ckM UV +=1

If 1prefk UV < then 01 =kMV

If 2prefk UV > then ckM UV 22 +=

If 2prefk UV < then ckM UV +=2

If 3prefk UV > then 03 =kMV (4)

If 3prefk UV < then ckM UV −=3

If 4prefk UV > then ckM UV −=4

If 4prefk UV < then ckM UV 24 −=

Step 2: Determination of the output voltage

4321 kMkMkMkMkM VVVVV +++= (5)

3. Permanent Magnet Synchronous Machine modelling

The model of PMSM without damper winding has been developed on rotor reference frame as follows [15][16][17][18]:

q

d

UU

=sLRLd

LsLR

qs

qds

+−+

..

ωω

.q

d

ii

+tK.

0ω

(6)

The electric torque is stated as:

qdqdqtem iiLLiKC .).(. −+= (7)

ωω .).( KCCsJ rem −−= (8) Control of PM motors is performed using field oriented control for the operation of synchronous motor as a DC motor. For the PM synchronous machine used, we develop the algorithm di =0 (Fig3). When the d axis current is equal to zero, the block diagram of the q axis becomes similar to that of a DC machine and the speed can be controlled by using a sliding mode controller which generates the q axis voltage. We use a current regulator for the d and q axes [15][17].


135

Figure 3. Permanent Magnet Synchronous Machine speed control scheme based on sliding

mode 4. Two-level PWM current rectifier modelling and control The general structure of the two-level PWM current rectifier is given on the figure 4.

Figure 4. Structure of one two-level PWM current rectifier

4.1. Modelling of the two-level PWM rectifier The optimal control of this two-level PWM rectifier is (k=1,2,3):

rkrk BB 01 = (9) The voltage equations are given by (10) where resV are the source voltage, resi the line

current, and xV the rectifier input voltage (x=F,G,H), respectively and R and L are respectively the input resistance and the input inductance:

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡+

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

++

+=

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

H

G

F

res

res

res

res

res

res

VVV

iii

LpRLpR

LpR

VVV

3

2

1

3

2

1

000000

(10)

The input voltages of the two-level PWM rectifier are defined as follows:


136

redrrrF UFFFV ).2(31

312111 −−=

redrrrG UFFFV ).2(31

311121 −−= (11)

redrrrH UFFFV ).2(31

112131 −−=

The rectifier output current is given as follows:

331221111 resrresrresrred iFiFiFI ++= (12) 4.2. Control of the two-level PWM current rectifiers 4.2.1. Voltage feedback control Each phase k (k=1,2 or 3) of the three-phase network feeding the rectifiers considered can be represented by a R,L circuit. reskV is the voltage of one phase k of the three-phase

network and kV is the voltage of the leg k of the rectifier. The voltage loop imposes the effective value of the network reference current corresponding to the power exchanged between the network and the continue load (fig5).

Figure 5. Control algorithm of the output DC voltage of the two-level PWM current

rectifier.

For the voltage loop modelling, we use the instantaneous power conservation principle. In this principle, inP is the input power of the rectifier and outP the output one.

).21..(

3

1

22∑

=−−=

k

reskreskreskreskin dt

dILIRIVP (13)

).().( 222111 cchccchcout iiUiiUP +++= (14) If we suppose the sinusoidal currents of the network in phase with the corresponding

voltages reskV and we neglect the rectifier losses and the Joule effect in the network

resistors R , we can write: redcer IUIVP ..2..3 == (15)


137

rV and eI are the amplitude of the phase voltage and current respectively

Then c

erred U

IVI

.2..3

= (16)

We define the next values as follows:

221 cc

cUU

U+

=

221 cc

cii

i+

= (17)

221 chch

chii

i+

=

cchred iiI += We want to regulate the voltage cU of the rectifier. For that, we choose for sliding surface:

crefc UUS −= (18) Its derivative is:

••

= cUS (19)

CiI

U chredc

−=

• (20)

CiU

IVU chc

erc /).2

..3( −=• (21)

The condition 0. <

•

SS insures the attractibility of the trajectory towards the sliding surface. For that, we choose: SkSsignkS .)(. 21 −−=

• (22)

The output of the sliding mode controller gave: Rectifier n°1

r

cachcrefcacrefcaea V

UiUUkUUsignkCI.3

.2].)).()(..([ 21 −−+−−= (23)

Rectifier n°2

r

cbchcrefcbcrefcbeb V

UiUUkUUsignkCI

.3.2

].)).()(..([ 21 −−+−−= (24)

4.2.2. Current feedback control


138

We control the network current of the phase 1 and 2 by a sliding mode regulator. The algorithm of this current loop is given on the figure 6. In this scheme, the transfer function

)( pH is expressed as follows:

pLRVIpH resk

.1)(+

== (25)

Figure 6. Control algorithm of the network current iresk of the two-level PWM rectifier.

From the network equations we have:

111 .. resresAres ILIRVV•

+=−

222 .. resresBres ILIRVV•

+=− (26)

cgA UNV .1=

cgB UNV .2= (27) We choose the following sliding surfaces

111 refres IIS −=

222 refres IIS −= (28) To satisfy the attractibility condition, we choose:

1211111 .)(. SkSsignkS −−=•

2222122 .)(. SkSsignkS −−=•

(29)

)3

).1.(2.cos(...2 πωω −−−=

•• ktIIS ereskk

with 3,2,1=k We obtain: Rectifier n°1:

cerefres

refresresresg

UtILIIkL

IIsignkLIRVN

.2/)].cos(....2)(.

)(...[

1121

1111111

ωω−−

+−+−=

(30)


139

cerefres

refresresresg

UtILIIkL

IIsignkLIRVN

.2/)].cos(....2)(.

)(...[

2222

2212222

ωω−−

+−+−=

Rectifier n°2:

cerefres

refresresresg

UtJLJJkL

JJsignkLJRUM

.2/)].cos(....2)(.

)(...[

1121

1111111

ωω−−

+−+−=

(31)

cerefres

refresresresg

UtJLJJkL

JJsignkLJRUM

.2/)].cos(....2)(.

)(...[

2222

2212222

ωω−−

+−+−=

5. Clamping bridge In this section, a clamping bridge control is introduced to balance the four DC input voltages, avoid NP potential drift and improve the performances of the speed control of the permanent magnet synchronous machine. Several publications have discussed ways to solve this balancing problem in three-level NPC-VSI [5-14]. The multitude of proposals (selection of appropriate voltage vectors) implemented to ensure DC voltage balancing can be broadly divided into two categories. In the first category based on space vector realization, redundant switching states of the converter are used while in the second category using carrier-based pulse width modulation (PWM) scheme, a zero sequence voltage signal is added to the modulation signals. In some schemes using zero sequence voltage to balance DC capacitor voltages, knowledge of load power factor (or direction of instantaneous power flow) is required which is difficult to implement under transient conditions, and in others, measurements of both capacitor voltages and load currents (magnitudes or polarities) are required. Unfortunately, these methods modify the output voltage waveform. Also, as the number of inverter-level increases, the problem of capacitor balancing becomes more complex and the solution very drastic. By using a separate supply for each DC-link level, the balancing issues are solved [3]. However, this solution is expensive especially for more then three-level. Another solution consists of adding electronic circuitry. In [13] and [14], clamping bridges based on transistors and resistors (dissipative method) are proposed as a solution to this problem. Advantages are low cost and low complexity. Disadvantages are high energy losses, high current switches and costly design thermal management requirements for large values. This method is best suited for systems that are charged often with small currents. In order to remedy to the unbalance problem, we suggest a solution which consists in establishing a bridge balancing between the rectifier and the intermediate filter (fig 7). The aim of this use is to limit and stabilise variations of the input DC voltages of the inverter.


140

Figure 7. Structure of the clamping bridge

The capacitor voltage equalization clamping bridge scheme has many advantages such as higher equalization efficiency and a modular design approach. As shown in Figure 7, switches T1 , T2 , T3 and T4 are MOSFET; diodes D1 , D2 , D3 , D4 are continued flow diodes; L1 and L2 is the energy storage inductors; C1 , C2 , C3 , C4 are four adjacent series cells, respectively. The basic operational principle is as follows:

* When Uc1>Uc2, a drive signal is given to the switches, and switch T2 is turned off and T1 is turned on. While T1 is on, capacitor C1, switch T1 and inductor L1 forms a loop circuit, whose current is Ic1 . The part of energy of capacitor C1 transfers to inductor L1 . While T1 is off, capacitor C2 , inductor L1 and the diode D2 forms a loop circuit, whose current is Ic2 . The energy of inductor L1 transfers to capacitor C2 . * When Uc1 <Uc2 , switch T1 is turned off and T2 is turned on. The energy transfers from C2 to C1 until the voltages of the two capacitors are same. * When Uc3>Uc4, a drive signal is given to the switches, and switch T4 is turned off and T3 is turned on. While T3 is on, capacitor C3, switch T3 and inductor L2 forms a loop circuit, whose current is Ic3. The part of energy of capacitor C3 transfers to inductor L2 . While T3 is off, capacitor C4 , inductor L2 and the diode D3 forms a loop circuit, whose current is Ic2 . The energy of inductor L2 transfers to capacitor C3 . * When Uc3 <Uc4 , switch T3 is turned off and T4 is turned on. The energy transfers from C3 to C4 until the voltages of the two capacitors are same.

The balancing algorithm searches to efficiently remove energy from a strong capacitor and transfer that energy into a weak one until the capacitor voltage is equalized across all capacitors. A. Switch control strategy of the clamping bridge Step 1: Deduction of the sign of the differences.


141

We use the following equations:

(32)

(33) Step 2: Deduction of the command of the transistors

(34)

6. Simulation results

Figure 8. Reference voltages and bipolar carriers

Figure 9. Output voltage VA for m=6, r=0.8 and f=50Hz

)()(. 122121

cdcLcc iiii

dtUUdC −−+=

−

)()(. 343243

dccLcc iiii

dtUUdC −−+=

−

1;0 1221 ==⇒< TTUU cc

0;1 4343 ==⇒> TTUU cc

1;0 4334 ==⇒< TTUU cc

0;1 1212 ==⇒> TTUU cc


142

Figure 10. Harmonic spectrum of the voltage VA for m=9 and r=0.8.

Figure 11. Harmonic spectrum of the voltage VA for m=12 and r=0.8

Figure 12. Harmonic spectrum of the voltage VA for m=15 and r=0.8


143

Figure 13. Characteristics of the voltage VA for m=6

Voltage Uca and its reference Vres1 , ires1 and its reference

Voltage Ucb and its reference Ures1 , jres1 and its reference

Figure 14. Output DC voltage, Network voltage and current of the two-level PWM current

rectifier


144

Voltages Uc1 and Uc3 Voltages Uc2 and Uc4

Figure 15. DC input voltages of the five-level NPC-VSI without using the clamping bridge

Speed Electromagnetic torque

Current id Current iq

Figure 16. Performances of the Permanent Magnet Synchronous Machine without using the Clamping bridge


145

Voltages Uc1 and Uc2 Voltages Uc3 and Uc4

Figure 17. DC input voltages of the five-level NPC-VSI by using the clamping bridge

Speed and its reference Electromagnetic torque

d axis current (id) q axis current (iq) Figure 18. Input DC voltages and PMSM performances obtained by using Clamping bridge


146

6.1. Results interpretation The figure 8 shows the reference voltages and the four bipolar carriers used for this strategy. The figures 9 to 12 give the output voltage VA and its harmonic spectrum for a modulation index m=6 (fig9), m=9 (fig10), m=12 (fig11) and m=15 (fig12) and a modulation rate r=0.8. The frequency is 50 Hz. We notice that in the four cases, the harmonics gather by families centred around frequencies multiple of 4.m.f. Because of the symmetry to the quarter of the period presented by the voltage VA, we obtain only odd harmonics. The most important harmonics gather around the first family. The modulation rate r lets linear adjusting of fundamental magnitude from r=0 to r=1 and the harmonics rate decreases when r increases (Figure13). For evaluating the performances of the Clamping bridge proposed, two simulations are presented. The first one propose to study a two two-level PWM current rectifier – Five-level NPC VSI – Permanent Magnet Synchronous Machine. This study shows particularly the problem of the instability of the input DC voltages of the five-level NPC VSI and its consequence on the performances of the PMSM speed control. The figure 14 shows the voltage Uca and Ucb and their references obtained by controlling the two-level PWM rectifiers by sliding mode control function. Those voltages follow perfectly their references (200V). The network currents ires1 of the upper rectifier is in phase with the network voltage Vres1. The network current jres1 of the lower rectifier is in phase with the network voltage Ures1. The parameters of the net are: R=0.25Ω ; L=10mH. On the figure 15, we show perfectly the problem of the unbalance of the four DC voltages of the intermediate capacitors bridge. The voltages Uc2 and Uc4 are decreasing and the voltages Uc1 and Uc3 are increasing. The parameters of the capacitors are: C1=C2=C3=C4= 20µF The figure 16 shows the consequences of the DC voltages drift on the characteristics of the Permanent Magnet Synchronous Machine. The speed follows its reference (400rad/s) but the undulations on the electromagnetic torque and different currents (id, iq) are very important due to the unbalance problem of the four input DC voltages. The parameters of the PM synchronous machine are: Ld=Lq=3.2mH; Rs=1Ω; p=3; Φf=0.13N.m/A; J=6.10-4 kg.m²; Fc=9,5.10-5 N.m.s/rad. Those results show the importance of the stability of the input DC voltages of the inverter to have good performances for the speed control of the PM synchronous machine. On the second simulation we introduce the clamping bridge proposed in the precedent cascade on the Figure 1 in order to show the different input DC capacitor voltage equalization performances. We can see on the figure 17 that the four voltages (Uc1, Uc2, Uc3 and Uc4) stabilise around the desired value (200V) and the DC link capacitor voltages are equalized. By using this technique of stabilisation, we can remark on the figure 18 that the undulations on the performances (Torque and currents id and iq) of the PMSM disappear and those performances are improved by using the inductive Clamping bridge. The parameters of the Clamping bridge are: L1= 1mH L2=1mH.


147

The afore-presented results confirm that the clamping bridge is able to equalize DC link capacitor voltages and stabilize the different DC voltages around the desired value. The performances of speed control of the PMSM are then ameliorating. 7. Conclusion The present contribution intends to demonstrate that permanent magnet synchronous machine control based on sliding mode control when applied with a two-level PWM current rectifier – Five-level PWM NPC-VSI may contribute both for functional performances improvement and attenuation of some technological limitations. With a high number of semi-conducting devices, current and voltage quality are improved and weight reduced by avoiding heavy filters. The input DC voltages are generated by a five-level PWM current rectifier controlled by sliding mode function control. By this study, we have particularly shown the problem of the stability and its effect on the speed control of PMSM and the input DC voltages sources of the inverter. In the last part of this paper, we propose a simple solution to stabilise the four DC voltages by using a new clamping bridge composed by four switches (pair transistor-diode) and two inductances. This technique permit an economic and simple electronic implementation, whereas in the space vector modulation control the computational burden, the complexity of the algorithms and the number of instructions are drastic especially when the number of levels of the inverter is greater than three. This nondissipative equalization design has many advantages such as high equalization efficiency due to the nondissipative current diverter, bidirectional energy transferring capability, and a modular design. Another advantage of this system is that no closed-loop control is needed and the process is self-limiting: when voltage equalization is complete, the switching of the capacitors consumes minimal energy. This method compares with the dissipative method and it is characterized by the low energy loss and the high equalizing speed in the process of charging and discharging. References [1] A.Nabae, I.Takahashi, and H.Akagi, A New Neutral-point-clamped PWM Inverter, IEEE Transactions on

Industrial Applications, 17(5), 1981, 518-523. [2] S.Ogasawara, and H.Akagi, Analysis of variation of neutral point potential in neutral point clamped voltage

source PWM inverters, Conference record IEEE-IAS Annual Meeting, 1993, 965-970. [3] H.Menzies, P.Steimer, and J.K.Steinke, Five-level GTO inverters for large induction motor drives, Conference

record IEEE-IAS Annual Meeting, 1993, pp. 595-601. [4] S.Koaro, P.Lezana, M.Anguio and J.Rodriguez, Multicarrier PWM DC-Link ripple forward compensation for

multilevel inverters, IEEE Transactions Power Electronics, 23(1), 2008, pp. 52-56. [5] A.Beig, G.Narayanan and V.T.Ranganathan, Modified SVPWM Algorithm for Three-Level VSI With

Synchronized and Symmetrical Waveforms, IEEE Transactions on Industrial Electronics, 54(1), 2007, 486-494.

[6] N.Celanovic and D.Borojevic, A comprehensive study of neutral point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters, IEEE Transactions on Power Electronic, 15, 2000, 242–249.

[7] P.K.Chaturvedi, J.Shailendra and P.Agrawal, A study of Neutral point potential and common mode voltage control in multilevel SPWM technique, Fifteenth National systems conference, Bombay, 2008, 518-523.


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[8] P.Purkiat and R.S.Sriamakavacham, A new generalized space vector modulation algorithm for Neutral-point-clamped Multilevel converters, Progress in Electromagnetics Research Symposium Cambridge, USA, March 26-29, 2006, pp 330-335.

[9] A.Bendre, S.Krstic, J.Vander Meer and G.Venkataramanan, Comparative evaluation of modulation algorithms for Neutral-Point-Clamped converters, IEEE Transactions on Industry Applications, 41(2), 2005, 634-643.

[10] Z.Pan, F.Z.Peng, K.A.Corzine, V.R.Stefanovic, J.M.Leuthen and S.Gataric, Voltage balancing control of Diode Clamped Multilevel Rectifier/Inverter systems, IEEE Transactions on Industry Applications, 41(6), 2005, 1698-1706.

[11] A.Bendre, G.Venkataramanan, D.Rosene and V.Srinivasan, Modelling and design of Neutral-Point voltage regulator for a three-level Diode–Clamped inverter using multiple-carrier modulation, IEEE Transactions on Industrial Electronics, 53(3), 2006, 718-726.

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[16] R.Chibani, E.M.Berkouk, , M.S.Boucherit, Lyapunov control of three-level PWM rectifiers to equilibrate input DC voltages of five-level NPC-VSI, International Review of Electrical Engineering, l2(1), 2007, 36-49.

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[18] R.Krishnan, Electric Motor Drives: Modelling, Analysis & Control, Prentice Hall, 2006.

Documents

jes7 2 1 - ESRGroups J. Electrical Systems 7-2 (2011): 131-148 Regular paper Study of a new DC voltage equalising circuit for Five-Level Neutral Point