JCET Low Cost High DensityJCET Low Cost High DensityPackaging Solutiong g

March 2015March 2015

Jiangsu Changjiang Elec. Tech.

$1 000

$850

$1,000

N ti l Hi h D it

SJsemi

$714

National High DensityPackaging LabChina IC Packaging Alliance

Chuzhou C9

$545 $611

SSE IPOC3 (IC)

Suqian C8

NO.4

$338 $356

$350 JCET

JCAP (B i & WLP)

C5 (SiP) WW OSAT Ranking

NO.7

NO.6

$54 $82 $133 Jiangyin Transistor Factory

(Bumping & WLP)Cu Pillar

MIS NO.8

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1972 1995 2000 2002 2003 2007 2008 2009 2010 2011 2012 2013 2014

Snapshot of FactoryJCET C3

JCET HQ

C8(Suqian) C9 (Chuzhou)

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Production Line

4

Factory Expansion in 2015

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Contents

Desire for Low Cost

PKG Interconnection - Bump

PKG Interconnection - Wire

PKG Base - Substrate

Low Cost Solutions

JCET Turnkey Services

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y

Desire for Low Cost

Wh d l t “l t” th t i ?

•Desire for “lower cost” is stronger and stronger in semiconductor packaging though market driven force was shifted from computer to communications, and now IoT and wearables.

Why do we select “low cost” as the topic ?

•“Advanced technology” doesn’t mean “high volume”•To provide premium packaging service in competitive cost to our customers is our mission.

What is the definition of “low cost” in this industry?

•We have known the definition of Low cost well but we may not think it right. Low cost should be thought as a relative concept instead of absolute concept.

•“Low cost” doesn’t mean “ low end technology”

What is the definition of low cost in this industry?

• Low cost doesn t mean low-end technology

How should we calculate cost?

•We should calculate cost at the level of system instead of the level of package.

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Back to Basics

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PKG Interconnection - Bump

Solder Bump Cu Pillar Bump

Bump Type Solder Bump Cu Pillar Bump

Bump on Pad Bump on Trace

Bump Type Solder Bump Cu Pillar Bump

Min. Bump Pitch >150um > 50um and 110um in Mass Prod.

Substrate Layer # 4 2

Surface Finish SOP OSP

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Surface Finish SOP OSP

Cost Factor 1 0.5

PKG Interconnection - Bump

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PKG Interconnection - Wire

Price (USD per OZ)

G ld C Sil

Electrical Conductivity(10E6 Simens/m)

Wire Material Cost Saving Comparing to Au Wire

0 95

PdCuAu Wire Alloy (Silver)

1170

0.164 16

Gold Copper Silver

44.258.5 62.1

Gold Copper Silver

0.8

0.85

0.9

0.95

Gold Copper Silver

Electrical Resistivity(10E-8 Ohm.m) Thermal Conductivity Thermal Expansion Coef

Gold Copper Silver

0.75

0.7 0.8 0.9 1 1.2

2.31.7 1.6

( )

Gold Copper Silver

317 401 420

(W/m.k)

Gold Copper Silver

14.1 17 19

Thermal Expansion Coef.(10E-6 k-1 from 0 to 100C)

Gold Copper Silver

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Gold Copper Silver Gold Copper Silver Gold Copper Silver

PKG Interconnection - Wire

JCET SiP Center ships more than 60Mu/month WB products to our customers at present, including p p gBGA and LGA.

80% of FBGA are using Alloy (Ag) wire, the 15% are Cu wire (PdCu & PdCuAu) product , the rest 5% are Au wire product. p

80% of WB LGA are Cu wire (PdCu & PdCuAu) product and the rest are Au wire product.

Assembly yield of WB product is above 99.9%. Cu wire bonding on 28nm wafer was qualified and

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gbrought into mass production at 1H of 2014.

Substrate SelectionWafer Node 60nm and above 40nm 28nm 16nm

Die Size 7x7~9x9mm 5x5~7x7mm 5x5~7x7mm ~5x5mm

Bump Pitch 150um 110um 95um 80um

HigherHigher Cost

Fan-out/eWLBSAP

MSAP MIS

ETS

FinerCoreless

SAP

50/50 40/40 35/35 30/30 25/25 20/20 15/15

TentingMIS

Pitch

10/10um

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50/50 40/40 35/35 30/30 25/25 20/20 15/15 10/10um

Substrate Selection

2L MSAP Substrate

2L MIS Substrate

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(Film Mold + Cu)

Substrate Selection

Key Cost Points: 4L SAP Substrate Low CTE Core Low CTE Core CUF

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Substrate Selection

K C t P i tKey Cost Points: 3L Coreless Substrate Low CTE PP CUF CUF

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Note: Crack shown on above SEM was caused by Ion milling.

Substrate Selection

K C t P i tKey Cost Points: 3L ETS Substrate Low CTE PP MUF

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MUF

Substrate Selection

Key Cost Points: 3L MIS Substrate (Film mold + Cu) Only

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( ) y MUF

Substrate Selection

Key Cost Points: 4L Hybrid Package Low CTE PP Low CTE PP MUF

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Low Cost Solution for FC•Low Cost Design & Technology •Low Cost Supply Chain •Economy of Scale

Low Cost Package Solution

12 inch silicon wafer Chip probe before bumping

BOL(BOT) Mass Reflow

1L or 2L Substrate Standard core/preprag material

Low Cost Technology

Chip probe before bumping Without PI ReP (Non-PI) Electroplated Bump: Cu Pillar

Mass Reflow MUF

Standard core/preprag material Wider Trace Pitch Mechanical Drill Plated Through Hole Liquid Type Solder Mask Solder Mask RegistrationChi + PKG + PCB C d i Solder Mask Registration OSP Tenting or MSAP Substrate Coreless Substrate UHD Strip (Wider Strip)

SiP/St k Di

• Chip + PKG + PCB Co-design• Low Cost doesn’t mean low

performance, system level simulation is essential for insurance of performance

• “Low cost + Stable Performance” may be better than “Higher cost + High

SiP/Stack Die Optimized Ball Layout for 4 or 6

layer PCB Design

g gperformance” in emerging market considering smartphone is cheaper and cheaper plus life time is shorter and shorter.

•Wafer Fab: SMIC•Wafer Bumping: JCAP, SJsemi

A bl d T t JCET

Low Cost Supply Chain Capable of supporting all type of devices (Good for Customer Centralized management) Turnkey Service from design to ship (Plenty experiences of on-site design support ) Low cost solution (play major role in low cost supply chain)

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•Assembly and Test: JCET(p y j pp y )

Sufficient capacity (economy of scale)

Realize Low Cost Solutions

Low Cost

Co-Design

Engineers

C ltCulture

S tSystem

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Turnkey ServicesProject Phases Process Characterization

and VerificationFunctionality Verification and

Reliability TestProduct and Process Optimization in LVM

HVM Production and Cost Reduction

Focus Data Collection/Verification(Test Vehicle)

Functionality and Reliability (Engineering Prototype)

Production Yield, Process Cycle Time

Production Cost, Yield, CT(Test Vehicle) (Engineering Prototype) Process Cycle Time

Turnkey Services • Solution Proposal and Planning• Test Vehicle Design• Process Characterization• Test Vehicle Measurement• Reliability Test

• AP RDL/Bump Design• Package Design• Test Board Design• 1st Silicon Characterization• Wafer Bumping

• Design Optimization• Process Optimization• Test Program Optimization

• Cost Reduction Proposal• Yield Improvement• CT Improvement• Test Time Optimization

Reliability Test Wafer Bumping• Wafer Probing after bump• Assembly• Test program development• Marking, Packing, Shipping

Qual. Assurance • Simulation Model Set Up • Lead Scan • O/S Test • O/S TestQual. Assurance Simulation Model Set Up• Simulation Model Verification• Failure Analysis

Lead Scan• O/S Test• Final Test• Reliability Test• Failure Analysis• Support on System Level Test

O/S Test• Final Test• Lead Scan• Failure Analysis

O/S Test• Final Test• Lead Scan• Failure Analysis

Design & Simulation

Engineering Prototype

Wafer Bumping &

Assembly Final Test Failure Analysis

Material (MIS Substrate)

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Probing

Summary - We Are Ready

Strive to BeCustomer Centric Low Cost Solution Time to Market Turnkey Services

Strive to BeThe Best

Our professional team has truly heart of customer centric and plenty experiences of customer services

W l l i d l j l i l i d l h i We propose low cost solution and play major role in low cost semiconductor supply chain

We are close to both wafer fab and product end users, and we deliver services in short cycle time

We provide turnkey services from design to drop shipment

We are capable of supporting a broad range of processors, modules and controllers, which is for customer’s centralized management We are capable of supporting a broad range of processors, modules and controllers, which is for customer s centralized management

We have sufficient capacity for large volume production orders

We have automated process control and monitoring system to minimize human interference in production

We have mature QA system across all sites for error proof

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We are young, we have dreams to realize and we strive to be the best in our customer’s supply chain

谢 谢！Thank youy