JAZiO ™ Incorporated JAZiO

JAZiO™ Incorporated1

PlatformPlatform20002000

JAZiOJAZiO™™

IncorporatedIncorporatedwww.JAZiO.comwww.JAZiO.com

Digital Signal Switching Technology



Agenda:

• What is JAZiO?

• What’s Wrong with Traditional Methods of Signal Switching?

• The JAZiO Solution



What is JAZiO?• JAZiO, Inc is a small San Jose-based

company that invents and licenses technology

• The first technology offered is Digital Signal Switching

• This technology works with any user defined protocol, allowing complete product differentiation



Traditional Signal Driving

All information is transmitted during tRF

(1/3 of bit time)

The rest of the bit time is just wasted!

One bittime

Next bittime

tRF tSU tHD

Sharp Edges Cause:

Ground Bounce!Cross Talk!

Ringing!EMI!

High Power!



Traditional Signal Sensing

Single ended: Not suitable for high speed

Differential: Great!, but 2x the pins

Pseudo differential: A compromise



Pseudo Differential Signal SensingOne bit

timeNext bit

time

Sensing Level

VREFSwitching

Level 0.8V

Sensing level about1/3 of switching levelThe rest of the switching

level is just wasted!

Large switching levels cause:

Ground Bounce!Cross Talk!

Ringing!High Power!



Traditional Signal SwitchingResults in large, fast edges (high slew rate)

From Signal Integrity Corner, Be Afraid, Be Very Afraid By Eric Bogatin, www.bogatinenterprises.com

Why is this important????

• There are two kinds of designers, those that have signal integrity problems, and those that will

• It is predominantly the rise time that influences the magnitude of signal integrity problems in a system.



Why Does this Matter?• Moore’s law: Silicon technology doubles

every 18 months• Moron’s law: Non-silicon technology

doubles every 18 years• Therefore transmitting data between chips

(across motherboard, over cables, down backplane, etc) becomes the performance bottleneck of the entire system



What is Needed?• A system with edges that take most of the bit time• A system with small signal levels similar to true

differential sensing• A system with 1 pin per signal

How???



JAZiO Solution• JAZiO has invented a system which

– Achieves very high performance – Has edges which can take the whole bit time– Uses differential sensing with very low signal

levels– Yet has only 1 pin per data signal



What’s the Secret? A Re-think• For each data signal, there is either a change or no-

change from the previous bit time• Traditional systems are good on no-change but bad

on change• JAZiO looks for change first and then adjusts if no-

change occurs• For JAZiO the decision binary is change or no-

change rather than “high” or “low” relative to VREF



JAZiO Solution

SteeringLogic

DataOutput

VTR

DataInput

VTR

B

A Dual Comparators are used

In cases 1 and 6 Comparator A makes a differential comparisonIn cases 2 and 5 Comparator B makes a differential comparisonIn the other four cases Data Input does not change

Data is driven coincidentally with Voltage/Timing References

DataInput

VTR

VTR

One Bit Time

Provide alternating Voltage/Timing References switching at the data rate

Next Bit Time

8 different combinations of VTR and Data Input

712

3

4 8

56



Steering Logic

The trick is to know how to select between Comparators A and B and what to do when Data Input does not change



Steering Logic

• Generate Steering Logic signals (SL and SL)• Use them with Data Output from previous Bit

Time to select between Comparators A and B

SL

SL

DataOutput

XORin

inout

XORin

in

out

Data Input

VTR

VTR A

B

VTR

VTR

VTR



DataOutput

SL

Initializationor

Receiver Enable

SL

VTR

VTRDataInput

DataInput

XOR

XOR

55 Transistors Per Bit



Time Domain

Decision is made in the Time Domain rather voltage domain

VTR

DataInput

First Look forchange

Determine no-change and

switch toComparator B

0.5V

SL

SL

DataOutput

XORin

inout

XORin

in

out

Data Input

VTR

VTR A

B

VTR

VTR

VTR



AYes

JAZiO™ Receiver OperationA

Rail to Rail

Rail to Rail

0 1 1 0 0 1

SL

SL

XOR-B

DataOutput

in

in

in

inout

out

Data Input

VTR

VTR

B

VTR

VTR

VTR

XOR-A

Rail to Rail

DataInput

DataOutput

Initialize

VTRVTR

Comparator Selected

Change?

SL

SL

CompBCompA

XOR-A

XOR-B

YesB A

YesYes No No

Both Comparators have Signal in

No-change Case



The No-Change Case

But!The handoff from ComparatorA to B is smooth since both of them want to drive Data Outputhigh

After the handoff, Comparator Bis ready to make the nextdifferential comparison

Since Comparator A is selected itshigh value causes Data Output to remain high

DataOutput

XOR-B

in

in

in

inout

outXOR-A SL

SL

Comparator A is selected and as the differential on its inputs disappears the outputremains high temporarily

However, Comparator B is gaining a differential and itsOutput becomes a solid high

VTR

DataInput

VTR

B

A

(High)

Bit Time 3

But eventually the XORs will switchAnd Comparator B will be selected



18 JAZiO™ ReceiversD

ata

Inp

ut

0

Bit

s 1-

7

VT

RS

L

SL

VT

R

Dat

a O

utp

ut

0

SIG

NA

LS

FR

OM

P

AD

S

XO

R

XO

R

XO

R

XO

R XO

R

XO

R XO

R

XO

R

Dat

a In

pu

t 8

Dat

a In

pu

t 9

Dat

a In

pu

t 17

Dat

a O

utp

ut

8

Dat

a O

utp

ut

9

Dat

a O

utp

ut

17

Bit

s 10

-16



Performance

~5 bittimes

Same SlewRate

0.5VJAZiO

JAZiO is ~5 times faster

1/3 bittime

One bittime

0.8VTraditionalApproach



Power• JAZiO has lower switching levels and lower termination

voltage• Instead of 1.8 to 1.0V use 1.0 to 0.5V ~1/3 the Power• Slow edges Lower current, smaller drivers • Only one pin per signal is used• One transition per data bit• No encoding

JAZiO is ~1/3 the power



Robustness• JAZiO works best with slow edges (use the entire

Bit Time!)• JAZiO works with small transition levels

(differential sensing)• JAZiO is entirely common-mode• Works with any appropriate Termination Scheme

(Series, Parallel, Single, Dual, Source and even none in some applications)

JAZiO is very robust and easy to use



Data Rate vs Slew Rate Comparison

• Slower edges

• Lower switching levels

• Reduced slew rate

0.5 1.0 1.5 2.0 2.5 3.0 3.5

Slew Rate (V/nS)

Dat

a R

ate

per

Pin

(b

/S)

10M

100M

1G

10G

EDO-33

SDRAM-66

SDRAM-100 DDR

RDRAM

JAZiO™

JAZiO™

JAZiO™

Better

Higher Performance at Lower Power with Higher Robustness



Where Can JAZiO Be Used?• DRAM

• SRAM

• Front Side Bus

• Backplane

• Communications

• On-chip Bus

• Etc



How Can JAZiO Be Used?• JAZiO is “essentially” an Open Standard• All technology is publicly visible• Anyone can see it, study it, simulate it, design

it in, build test chips, build prototypes, etc• Just don’t sell products without licensing it• JAZiO is working with JEDEC/AMI2 and is

currently offering a license fee of $200K with royalty of 0.3% for DRAMs



Conclusion• JAZiO uses lower levels and slower edges• Achieves high performance, low power, high

robustness• JAZiO technology is fundamentally different

from traditional methods– Time domain rather than voltage domain– Look for change first– Change vs No-change rather than High or Low

• JAZiO is available to everyone at low cost and applies to any application

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JAZiO ™ Incorporated JAZiO