January 22, 1999 SciFi L1 Trigger Review

1DD Analog HardwareAnalog Hardware

• Front-end Board (CTT_FE)– Transmit (and split) the VLPC signal to the Multi-chip Modules

– Discriminate the analog signals from the VLPC with the SIFT chip

– Sort, buffer and Xmit the discriminated signals to the CTT_Digital

– Transfer analog signal from the SIFT to the SVX2e

– Digitize the analog signals with the SVX2e, an eight bit ADC• for CFT fibers, 8 bits per channel• for PS fibers dual, overlapped 8 bits per channel (effective 11 bits).

– Supply an L3 readout for the digitized signals

– Supply an L3 readout for the ADC signals

– Supply the Bias voltage for the VLPC chips in each cassette and monitor the current drawn

– Supply temperature monitoring for the VLPC cassette and control local heaters to trim the VLPC temperatures within the cassette

January 22, 1999 SciFi L1 Trigger Review

2DD FE BoardsFE Boards

• Need 4 FE board types– CFT/CPS Right-hand board– CFT/CPS Left-hand board– FPS/CPS Stereo Right-hand board– FPS/CPS Stereo Left-hand board

• Design & build 2 board types– CFT/CPS ‘Ambidextrous’ board– FPS/CPS Stereo ‘Ambidextrous’ board

January 22, 1999 SciFi L1 Trigger Review

3DD CFT/CPS FE boardCFT/CPS FE board

• Used for– 80 boards - CFT/CPS Axial

– 16 boards - FPS Forward Layer

– 75 boards - CFT Stereo • Modified for NO charge split

• Cin:Apse connectors along bottom – 480 CFT input channels

– 32 CPS Axial channels• 64 inputs after charge split

• Back plane connections on both ends• Output to Digital boards -

– 480 CFT Discriminator Outputs - ‘Home’

– 188 CFT Discriminator Outputs - ‘Neighbor’

– 64 CPS Discriminator Outputs - North/South & High/Low

January 22, 1999 SciFi L1 Trigger Review

4DD PS FE boardPS FE board

• Used for– 16 boards - FPS Back Layer

– 10 boards - CPS Stereo • Modified for charge split

• Cin:Apse connectors along bottom – 512 CPS Axial channels - to 1024 after charge split

• Back plane connections on both ends• Output to Digital board -

– 512 PS Discriminator Outputs - ‘High Threshold’

– 512 PS Discriminator Outputs - ‘Low Threshold’

January 22, 1999 SciFi L1 Trigger Review

5DD Front End Basic LayoutFront End Basic Layout

MCM

TQFP

1.48 in

3.42

in

.20 in

.23

in

TQFP TQFP

TQFP

MCM

TQFP

1.48 in

3.42

in

.20 in

.23

in

TQFP TQFP

TQFP

MCM

TQFP

1.48 in

3.42

in

.20 in

.23

in

TQFP TQFP

TQFP

MCM

TQFP

1.48 in

3.42

in

.20 in

.23

in

TQFP TQFP

TQFP

MCM

TQFP

1.48 in

3.42

in

.20 in.2

3 in

TQFP TQFP

TQFP

MCM

TQFP

1.48 in

3.42

in

.20 in

.23

in

TQFP TQFP

TQFP

MCM

TQFP

1.48 in

3.42

in

.20 in

.23

in

TQFP TQFP

TQFP

MCM

TQFP

1.48 in

3.42

in

.20 in

.23

in

TQFP TQFP

TQFP

AREA RESERVED FOR CIN:APSE CONNECTORS

AREA RESERVED FOR CHARGE SPLIT NETWORK

AM

UX

AM

UX

AM

UX

AM

UX

AM

UX

AM

UX

AM

UX

AM

UX

PASSIVES

PASSIVES

PASSIVES

PASSIVES

PASSIVES

PASSIVES

PASSIVES

PASSIVES

PASSIVES PASSIVES PASSIVES PASSIVES PASSIVES PASSIVES PASSIVES PASSIVES

January 22, 1999 SciFi L1 Trigger Review

6DD Analog CircuitAnalog Circuit

HD Connector

MCM

Resistor

Resistor

Resistor

Resistor

Analog Circuit for 4 Channels

Analog Circuit I

VLPC

Bias Supply

- 6V

AnalogGND

Signal Return

Protection Resistor

Signal

AnalogGND

Circuit schematic for an analog FE board.

This illustration shows four circuits, on the FE board the VLPC circuits are connected into groups of 64 channels.

Each group has a common BIAS supply on the board and a

shared trace into the cassette.

the common bias supply circuit is also the common signal return.

The 64 individual signal lines are

also bias return lines.

For charge splitting the single capacitor shown coupling the signal into the MCM is replaced with a charge division network

January 22, 1999 SciFi L1 Trigger Review

7DD PS Charge SplittingPS Charge Splitting

• The charge from the VLPC is split 3 ways with most of the charge dumped through the drain capacitor.

• Minimum value of Cdrain = 25pF due to cable capacitance,

• Since C1 and C2 are much smaller than Cdrain the charge division is proportional to C1(2) / C1+C2+Cdrain

• Splitting is Cd:Chigh:Clow

– CPS - (80:16:4)% :: (50:15:4)pF

– FPS - (82.5:13.0:4.5)% :: (50:12:4)pF

• FPS forward layer split– FPS - (15:70:15)% :: (0:117:25)pF

– We DON’T know how to make this work. Needs to be re-thought.

C1

VLPC Bias

ProtectionResistor

VLPCC2

Cdrain

PS_Splitter

January 22, 1999 SciFi L1 Trigger Review

8DD Multi-chip Module Multi-chip Module FeaturesFeatures

72 Inputs in two blocks of 36

Each MCM contains 4 SIFT chips and one SVX chip.

The SIFT chips share common controls as two pairs.

The control consists of the discriminator gain range setting

threshold voltage

the analog output gain range setting.

SIFT channels 2 through 19 are used. The outer two channels are grounded

and serve as guard channels.

The SVX2e chip has 72 of 128 channels bonded.

The bonded channels are for the most part every other channel.

SIFT - 1A

SIFT - 2A

SIFT - 1B

SIFT - 2B

Control A

Control B

SVX

72 Inputs

18 Inputs

V-Outs

file: MCM

January 22, 1999 SciFi L1 Trigger Review

9DD L3 Readout SystemL3 Readout System

• Cartoon of the L3 Read Out. – The MCM's on each FE board

are linked into two, eight SVX chips long, read out strings.

– Each two strings are linked via a 50 conductor copper cable to a Sequencer board located in a crate nearby on the Platform.

– The sequencer takes the data from two strings and puts it onto a single glass link and sends it to the VRB.

– The VRB is read out by the VBD and into the DAQ system.

FE

Se

qu

en

ce

r

VRB

50-ConCopper

1GBitGlass

MCMVB

D

PS_L3

January 22, 1999 SciFi L1 Trigger Review

10DD SIFT ChipSIFT Chip

• Custom chip for D0– .8um - 3 metal HP

cmos

• 18/20 channels

• individual trigger pick offs

• 70ns charge integration time

• two analog gain ranges

– 0.4 & 0.2 gain to SVX

• active matching to SVX input zero point

• two discriminator gain ranges

January 22, 1999 SciFi L1 Trigger Review

11DD SIFT ClocksSIFT Clocks

• Clock timings for the SIFT

• RESET Cycle

– SVX is Reset

– SIFT preamp is reset: PRST

– SIFT discr. is reset: DRST

– This readout scheme requires abort gaps in the Tevatron for reset purposes.

• ACQUISITION Cycles

– PRST every crossing

– S/H enables Dicr. output

– LATCH records digital outs

– S/H also samples analog

– READ transfers charge

• All clocks are generated on FE from Crossing signal

– Accuracy 5ns abs.

Title:(SIFT_CLK)Creator:(Vellum: LaserWriter 8 8.5.1)Preview:This EPS picture was not savedwith a preview included in it.Comment:This EPS picture will print to aPostScript printer, but not toother types of printers.

January 22, 1999 SciFi L1 Trigger Review

12DD Threshold Stability Threshold Stability

• Discriminator reset is not needed each cycle

• charge input over many cycles shows no threshold drift

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 5 10 15 20 25 30

Pipe line

Vth

(V

)

January 22, 1999 SciFi L1 Trigger Review

13DD Analog TransferAnalog Transfer

• SIFT->SVX charge transfer is linear.

• The Gain selection switch provides a x2 difference.

• The dynamic range is more than 450 fC.

y = 0.193*x - 2.4

y = 0.388*x - 16.6

0

20

40

60

80

100

0 100 200 300 400 500

Qin (fC)

Qsv

x (

fC)

January 22, 1999 SciFi L1 Trigger Review

14DD FPS OccupancyFPS Occupancy

January 22, 1999 SciFi L1 Trigger Review

15DD

0

50

100

150

200

250

300

0 100 200 300 400 500 600 700

Qin (fC)

SV

X C

ou

nts

P2

P6

P10

P13

P16

P20

P23