Sandia Microelectronics Development

Microelectronics Technologies Department Sandia National Laboratories, Albuquerque, NM 871 85-1 087

<".: Harry T. Weaver , .

JAN 3 1 t397 Abstract

An overview of the operations of Sandia's Microelectronics Development Lab (MDL) is presented. The primary purpose of the MDL is to develop radiation hardened IC, but techniques used for IC processing have been applied to a variety of related technologies such as micromechanics, smart sensors, and packaging.

Introduction

A primary assignment for Sandia National Labs is the development of electrical sub systems and systems used in national security applications. Embedded in this activity is the procurement of special purpose microelectronics integrated circuits (IC). While the preferred procurement procedure is always direct purchase of IC from commercial sources, experience has shown that needed IC for very specialized applications are not always available. Generally, radiation hardening is the main issue, but historical examples also include non volatile memories, specific microprocessors, and classified designs. Examples of systems that use Sandia IC include Galileo, Magellan, MILSTAR, and a variety of weapons. Although the number of IC in each delivery is relatively small they represent tens of thousands of parts using 6 different technologies.

This paper focuses on Sandia's IC fabrication capability, the center piece of which is the Microelectronics Development Laboratory (MDL), a state-of-art Class 1 clean room in which technologies are developed and IC fabricated. Not covered in any detail is the extensive microelectronics infrastructure, ranging from basic research on materials to product certification. Hardware within this infrastructure includes about 20 mentor design work stations, an Advent 50 MHz tester, a Sentry 21 tester, and several HP82000 units that support failure analysis as well as circuit testing. In addition, we have a variety of radiation sources, including wafer level testers, full IC certification systems, and an extensive failure analysis

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laboratory. Software systems include SPICE, SABER, COMPASS, Mentor, and SYNOPSYS. There is also a collection of process, device, and reliability assessment models.

Sandia's long term strategy for advancing its microelectronics technologies can be partitioned as follows. First, the physical entities required to operate the MDL are maintained. The building is reconfigurable and should be capable of supporting technology advances for more than a decade. Second, an IC technology close to manufacturing state of art must be exercised through product fabrication. The proximity of Sandia's most advanced technology to that of the commercial world is determined by requiring that the MDL is attractive to equipment vendors. This is a diminishing-return problem where moving too close to commercial world IC levels is prohibitively expensive, but falling too far behind leads to obsolescence. Third, establish partnerships with equipment vendors under which engineering data on equipment is exchanged for equipment. The engineering data ranges from basic plasma models to operations data from marathon runs using specific pieces of equipment. The partnerships help offset recapitalization costs, but as importantly, provide Sandia engineers and scientists with a link to commercial technologies and know-how.

Facilities

The MDL is a three story complex totaling about 175,000 sq. ft. (Fig. 1). It houses 33,000 sq. ft. of clean room space, 12,500 sq. ft. of which is Class 1. The clean room is organized in a reconfigurable bay-chase arrangement, each bay being independently air supplied. This feature allows both advanced R&D involving new materials and baseline IC processes to operate within the same complex. It is particularly important to equipment development where a given reactor can change from a research vehicle requiring extensive modifications to a member of the baseline equipment set without being physically moved.

DISCLAIMER

Portions of this document may be illegible in electronic image products. U e s are produced from the best available original document. #

DISCLAIMER

This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, make any warranty, express or implied, or assumes any legal liabili- ty or responsibility for the accuracy, completeness, or usefulness of any information, appa- ratus, product, or proces disdased, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily collstitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof. The views and opinions of authors expressed herein do not necessar- tly state or reflect those of the United States Government or any agency thereof.

are carried out on integrated micromechanics, where each lot of this technology requires about 450 steps.

Figure 1 - The Microelectronics Development Laboratory (MDL) is a Class 1 clean room dedicated to IC development for defense programs at Sandia National Labs.

The deionized water loop capacity is 250 gal. per min. at 55 psi, generating 150 gal. per min. of waste during purification. Temperature and humidity are controlled within 0.1 C and I%, respectively, in the photolith bays and about a factor of ten more relaxed elsewhere. High purity gas systems, neutralization stations, chemical storage, etc. follow standard clean room procedures.

Complete sets of fabrication equipment configured for 150 mm wafers support baseline CMOS and derivative technologies at 1.0 and 0.5 pm design rules. The equipment set includes 2 G-line and 2 I-line steppers. More advanced processing is accomplished on “short loops” which are run using a partial equipment set configured for 200 mm wafers using a deep UV stepper for the fine line features. Advanced packaging and other specialty projects often employ a contact aligner, to allow for large area exposures. This aligner is located in an isolated bay to allow for potential contaminants occurring in new materials used in some of our special projects.

The MDL operates 2 shifts per day, 5 days per week. The second shift is not fully staffed and technology engineers are on call during this period. Its operation prevents processing bottlenecks and significantly increases through-put for baseline technologies. Product flow is controlled using the commercial software “Workstream” operating on a DEC alpha processor. Under these conditions more than 45,000 processing steps per year are executed. This is equivalent to about 180 full flow lots (250 stepsllot). Most MDL steps (about 60%) go into shorter lot runs for process, equipment, or technology development. However, at the other extreme, about 15% of the steps

Ill. Technologies

Baseline processing within the MDL is based on two distinct CMOS technologies, a 5 V, 0.5 pm, 3 level metal technology for high density IC and a full flow CMOS, 2 pm, single level metal technology for integrating sensors or micromachines with IC logic functions. In addition to the baselines, process modules are continuously under development. These include micromachining, fabrication of various types of sensors, and large area processing. Combinations of these elements with the CMOS baselines can provide a variety of products such as radiation hardened digital and analog IC, non volatile memories, smart sensors, smart micromachines, and smart packages.

Figure 2 shows the distribution of processing steps among baseline and development areas. Engineering time distributes somewhat differently, depending on the maturity of the technology, but the figure gives a good approximation of the work distribution within the MDL.

Figure 2 - Diagram showing MDL lot moves by technology area.

CMOS-6: The Sandia 0.5 pm CMOS is based on an IBM technology [I] that includes retrograde n-wells, self aligned silicides, tungsten studs, chemical mechanical polishing (CMP) for planarization [2], and three levels of metal. Figure 3 shows a crossection micrograph from a SRAM. Our design rules are somewhat relaxed with drawn gate lengths and contacts of 0.6 pm and metal pitch of 1.85 pm. These dimensions conform to requirements for the commercial COMPASS standard

cell family that is used as a design avenue to the MDL. The CMOS-6 technology uses local oxidation for isolation and is not radiation hardened. Our highest density circuit demonstrated to date is a 256 kbit SRAM with which defect densities of below 1 cm* were obtained. Most of our mask sets, including this memory, are heavily covered with test structures that provide data on the line status and allow equipment evaluation.

Figure 3 - Cross-section of CMOS-6 SRAM showing metal studs and 0.5 pm transistor gates.

By replacing LOCOS with shallow trench isolation and adding cross-coupled resistors within latches [3] we have radiation hardened the CMOS-6 technology. At present the trench is filled with one version of a hardened field oxide [4], but our intent is to evolve the filler material and optimize both processing simplicity and hardness. Within our SRAM cell we have about 9 squares available for polysilicon resistors. Simulations, coupled with experiments on our CMOS-6 technology [3], show that a total resistance of about 80 kQ will provide SEU immunity to above 0.80 pC/pm. Sheet resistances of between 10 and 15 kWsq will accomplish this.

CMOS-5: The baseline CMOS-5 uses our G-line steppers for the 2 pm minimum feature sizes of this technology. Although CMOS-5 has been used in miscellaneous technologies, our primary use of this technology is the integration of micromachines with logic. Under development is a hybrid of CMOS-6 and CMOS-5 which will be used for analog functions and non volatile memories. CMOS-5 uses deposited hardened field oxides for isolation and a single level of metal. The advanced version, CMOS-5X, uses 1 vm

features, shallow trench isolation and chemical mechanical polishing for double level metal. Micromachining: Over the past 3 or 4 years Sandia has developed a 3 level polysllicon micromachining technology and integrated it with our CMOS-5 technology [5]. By providing multiple poly levels the MDL can fabricate very sophisticated mechanical designs. Examples include actuator driven gears, pop up mirrors, and mechanical mazes for coded locks. Figure 4 shows a gear driven pop up mirror.

Figure 4 - Micro machine actuator driving a system for a pop-up mirror.

gear

Integration of micromachines with CMOS is complicated by the machines’ large vertical dimensions and the high temperatures required for controlling mechanical properties of polysilicon. Consequently, integration usually requires sub optimal processing conditions for CMOS and for micromachines in order to achieve functional parts. However, with the recent maturing of CMP techniques new approaches to this integration are available.

In the Sandia technology [5], micromachines are constructed within a deep (>5 vm) trench during the initial part of the processing sequence. The machines are defined and all heat treatments completed, but they are not released from the layered oxides used to separate the poly structures. Instead the entire wafer is polished, leaving a planar starting material for CMOS processing. After completing the CMOS sequence, including metalization, the CMOS circuits are protected and the layered oxides in the micromechanics trenches are dissolved.

There are major advantages to integration of logic and micromechanical technologies. These include cost

reduction due to batch processing and to simpler packages, reduction of space, and enormous increases in sensitivity for sensors.

Miscellaneous Technologies: In addition to full flow CMOS, there are many different types of process development activities in the MDL, often not directly related to the current IC baselines. These include integrated hydrogen sensors [6], volatile organic gas detectors, assembly test chips for IC package evaluation, multichip module fabrication, and a variety of hybrid devices for specific applications. All of this work totals about 10-15% of the process steps of the MDL.

Equipment Evaluation: The main link between work in the MDL and the commercial world is through our partnerships with equipment vendors. Sandia provides engineering data and evaluations of specific pieces of equipment in exchange for equity in the equipment itself VI. The data include performance in a manufacturing-like environment, detailed computer simulations of the processes (plasma physics, chemistry, kinetics, etc.) and extensive in-situ monitoring during operation. Generally, the reactors are heavily outfitted with sensors as part of the overall evaluation project. Sensor placement and installation and careful analysis of data represent key benefits of this work to the vendor partners.

These studies do not require full flow CMOS, but do employ 8 inch diameter wafers, in contrast to our 6 inch diameter baseline work. Our partnerships often include SEMATECH, with which Sandia has a large cooperative agreement to support semiconductor R&D. Other partnerships are unilateral. Since the modem pieces of equipment end up belonging to Sandia we use the partnerships to help recapitalize the lab.

IV. Summary

Sandia develops and fabricates custom, rad hard IC in its Microeletronics Development Lab. Although the majority of IC used in Sandia systems is purchased from commercial sources, the MDL provides new technologies and represents a contigency supply of needed circuits for national security needs.

Acknowledaements

This work was supported by the United States Department of Energy under Contract DE-ACO4- 94AL85000. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy.

References

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