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Jan M. Rabaey
Low Power Design Essentials ©2008 Chapter 2
Nanometer Transistors and Their Models
Low Power Design Essentials ©2008 2.2
Chapter Outline
Nanometer transistor behavior and models Sub-threshold currents and leakage Variability Device and technology innovations
Low Power Design Essentials ©2008 2.3
Nanometer Transistors and Their Models
Emerging devices in the sub-100 nm regime post challenges to low-power design– Leakage– Variability– Reliability
Yet also offer some opportunities– Increased mobility– Improved control (?)
State-of-the-art low-power design should build on and exploit these properties– Requires clear understanding and good models
Low Power Design Essentials ©2008 2.4
The Sub-100 nm transistor
Velocity-saturated– Linear dependence between ID and VGS
Threshold voltage VTH strongly impacted by channel length L and VDS– Reduced threshold control through body
biasing Leaky
– Subthreshold leakage– Gate leakage
→ Decreasing Ion over Ioff ratio
Low Power Design Essentials ©2008 2.5
ID versus VDS for 65 nm bulk NMOS transistor
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1x 10
-4
VDS
(V)
I D (
A)
ID linear function of VGS
VGS = 0.8
VGS = 0.6
VGS = 0.4
VGS = 1.0
Early saturationDecreased output resistance
Low Power Design Essentials ©2008 2.6
Drain Current under Velocity Saturation
LEVV
VVWCvI
CTHGS
THGSoxSatDSat
2
Good model, could be used in hand or Matlab analysis
THGSDSatoxeff
DSat VVVC
L
WI
2
LEVV
LEVVV
CTHGS
CTHGSDSat
with
[Ref: Taur-Ning, ’98]
Low Power Design Essentials ©2008 2.7
Models for sub-100 nm CMOS transistors
Further simplification:The unified model – useful for hand analysis
Assumes VDSAT constant
[Ref: Rabaey, DigIC’03]
Low Power Design Essentials ©2008 2.8
Models for sub-100 nm CMOS transistors
0
100
200
300
400
500
600
700
0 0.2 0.4 0.6 0.8 1 1.2
VDS [V]
0.4V
0.6V
0.8V
1.0V
1.2V
simulationunified model
linear
saturation
vel. saturation
VDSAT
I DS[m
A]
Low Power Design Essentials ©2008 2.9
Alpha Power Law Model
Alternate approach, useful for hand analysis of propagation delay
THGSoxDS VVCL
WI
2
Parameter a is between 1 and 2.
In 65nm – 180 nm CMOS technology a ~ 1.2..1.3
[Ref: Sakurai, JSSC’90]
This is not a physical model Simply empirical:
– Can fit (in minimum mean squares sense) to variety of ’s, VTH
– Need to find one with minimum square error – fitted VTH can be different from physical
Low Power Design Essentials ©2008 2.10
Output Resistance
Drain current keeps increasing beyond the saturation point Slope in I-V characteristics caused by:
– Channel length modulation (CLM)
– Drain-induced barrier lowering (DIBL).
[Ref: BSIM 3v3 Manual]
The simulations show approximately linear dependence of IDS on VDS in saturation (modeled by l factor)
Low Power Design Essentials ©2008 2.11
Thresholds and Sub-Threshold Current
Drain current vs. gate-source voltage
0.0E+00
2.0E-04
4.0E-04
6.0E-04
8.0E-04
0 0.2 0.4 0.6 0.8 1 1.2
V GS [V]
I DS
[A
]
VTHZ
VDS = 1.2V
Low Power Design Essentials ©2008 2.12
Forward and Reverse Body Bias
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50.25
0.3
0.35
0.4
0.45
0.5
VBS
(V)
VT (
V)
Threshold value can be adjusted through the 4th terminal,the transistor body.
Forward biasReverse bias
Forward bias restricted by SB and DB junctions
€
VTH = VTH0 +γ ( −2φF +VSB − −2φF
Low Power Design Essentials ©2008 2.13
Evolution of Threshold Control
-0.5 0 0.5-0.1
-0.05
0
0.05
0.1
0.15
VBB (V)
DV
TH (
V)
130 nm
90 nm
65 nm
Body biasing effect diminishes with technology scaling below 100 nm. No designer control at all in FD_SOI technology
210 mV
95 mV
55 mV
Low Power Design Essentials ©2008 2.14
Impact of Channel Length on Threshold Voltages
L
Long-channel threshold
Lmin
With halo implants
(for small values of VDS)
Partial depletion of channel due to source and drain junctions larger in short-channel devices
Simulated VTH of 90 nm technology
Low Power Design Essentials ©2008 2.15
Impact of Channel Length on Threshold Voltages
50% increase in channel lengthdecreases leakage current by almost factor 20 (90 nm)
50 100 150 200 250 300 350 4000
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
length (nm)
No
rma
lize
d L
ea
kag
e C
urr
en
t
Low Power Design Essentials ©2008 2.16
Drain-Induced Barrier Lowering (DIBL)
In a short channel device, source-drain distance is comparable to the depletion region widths, and the drain voltage can modulate the threshold
VTH = VTH0 - ldVDS
Channel
L (D)0 (S)
Long channel
Short channel
Vds = 0.2VVds = 1.2V
Low Power Design Essentials ©2008 2.17
MOS Transistor Leakage Components
G
DS
B(W)
Gate leakage
D-S leakageJunction leakage
Low Power Design Essentials ©2008 2.18
Sub-threshold Leakage
-9
-8
-7
-6
-5
-4
-3
0 0.2 0.4 0.6 0.8 1 1.2
V GS [V]
log
I DS
[lo
g A
]
Subthreshold slope S = kT/q ln10 (1+Cd/Ci)
Drain leakage current is exponential with VGS
Subthreshold swing S is ~70..100mV/dec
VDS = 1.2V
G
S D
Sub
Ci
Cd
The transistor in “weak inversion”
Low Power Design Essentials ©2008 2.19
Impact of Reduced Threshold Voltages on Leakage4
ord
ers
of
ma
gn
itude
300 mV
Leakage: sub-threshold current for VGS = 0
Low Power Design Essentials ©2008 2.20
Subthreshold Current
Subthreshold behavior can be modeled physically
qkT
V
qkTn
VV
SqkT
V
qkTn
VV
oxDS
DSTHGSDSTHGS
eeIeeq
kT
L
WCnI 112
2
with n the slope factor (≥ 1, typically around 1.5), and
2
2
q
kT
L
WCnI oxS
Very often expressed in base 10
S
nV
S
VV
SDS
DSTHGS
II 10110
the subthreshold swing, ranging between 60mV and 100mV)10ln()(q
kTnS with
≈ 1 forVDS > 100 mV
Low Power Design Essentials ©2008 2.21
Subthreshold Current - Revisited
Drain-Induced Barrier Lowering (DIBL)– Threshold reduces approximately linearly with VDS
Body Effect– Threshold reduces approximately linearly with VBS
DSdTHTH VVV l 0
BSdTHTH VVV 0
S
nV
S
VVVV
SDS
DSBSdDSdTHGS
II 101100 l
Leading to:
Leakage exponential function of drain and bulk voltages
Low Power Design Essentials ©2008 2.22
Subthreshold Current as Function of VDS
ID versus VDS for minimum size 65 nm NMOS transistor(VGS = 0)
ld = 0.18S = 100 mV/dec
DIBL
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
0.5
1
1.5
2
2.5
3
3.5
4
4.5x 10
-9
VDS (V)
I D (
A)
Two effects:• diffusion current (like
bipolar transistor)• exponential increase
with VDS (DIBL)
3-10x in currenttechnologies
Low Power Design Essentials ©2008 2.23
Gate-Induced Drain Leakage (GIDL)
Excess drain current is observed, when gate voltage is moved below VTH, and moves to negative values (for NMOS)
More outspoken for larger values of VDS (or GIDL ~ VDG)
High electrical field between G and D causes tunneling and generation of electron-hole pairs
Causes current to flow between drain and bulk
Involves many effects such as band-to-band direct tunneling and trap-assisted tunneling
[Ref: J. Chen, TED’01]
© IEEE 2001
Low Power Design Essentials ©2008 2.24
Combining all Drain Leakage Effects
-0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.210
-12
10-10
10-8
10-6
10-4
VGS (V)
I D (
A)
VDS = 0.1 V
VDS = 1.0 V
VDS = 2.5 V
90 nm NMOS
GIDL
Low Power Design Essentials ©2008 2.25
Gate Leakage
Silicon substrate
1.2 nm SiO2
Gate
Scaling leads to gate-oxide thickness of couple of molecules
MOS digital design has always been based on assumption of infinite input resistance!Hence: Fundamental impact on design strategy!
Causes gates to leak!
[Ref: K. Mistry, IEDM’07]
Introduction of high-k dielectrics
Low Power Design Essentials ©2008 2.26
Gate Leakage Mechanisms
Direct Oxide tunneling dominates for lower Tox
[Ref: Chandrakasan-Bowhill, Ch3, ‘00]
© IEEE 2000
Low Power Design Essentials ©2008 2.27
Direct Oxide Tunneling Currents
VDD
JG (
A/c
m2)
0 0.3 0.6 0.9 1.2 1.5 1.8
10-9
10-6
10-3
100
103
106
109
tox
0.6 nm0.8 nm
1.0 nm1.2 nm
1.5 nm
1.9 nm
VDD trend
[Courtesy: S. Song, 01]
Also: - Gate tunneling strong function of temperature - Larger impact for NMOS than PMOS
JG: exponential function of oxide thickness and applied voltage
oxox
B
ox
TV
V
G eJ
/
)1(1 2/3
Low Power Design Essentials ©2008 2.28
High-k Gate Dielectric
Equivalent Oxide Thickness = EOT = tox = tg * (3.9/eg), where 3.9 is relative permittivity of SiO2 and eg is relative permittivity of high-k material
Currently SiO2/Ni; Candidate materials: HfO2 (eeff~15 - 30); HfSiOx (eeff~12 - 16)– Often combined with metal gate
Electrode
Si substrate
tox SiO2
tg
High-k Material
Electrode
Si substrate
Reduced Gate Leakage for Similar Drive Current
Low Power Design Essentials ©2008 2.29
High-k Dielectrics
Silicon substrate
1.2 nm SiO2
Gate
Silicon substrate
Gate electrode
3.0nm High-k
Buys at a few generations of technology scaling
[Courtesy: Intel]
High-k vs. SiO2 Benefits
Gate capacitance
60% greater Faster transistors
Gate dielectric leakage
> 100% reduction Lower power
Low Power Design Essentials ©2008 2.30
Gate Leakage Current Density Limit versus Simulated Gate Leakage
[Ref: ITRS 2005]
Low Power Design Essentials ©2008 2.31
Temperature Sensitivity
Increasing temperature– Reduces mobility– Reduces VTH
ION decreases with temperature
IOFF increases with temperature
VGS
dsI
increasingtemperature
0 10 20 30 40 50 60 70 80 90 1000
1
2
3
4
5
6
7
8
9
10x 10
4
Temp(°C)
Ion
/Io
ff
90 nm NMOS
Low Power Design Essentials ©2008 2.32
Variability
Scaled device dimensions leading to increased impact of variations– Device physics– Manufacturing– Temporal and environmental
Impacts performance, power (mostly leakage) and manufacturing yield
More outspoken in low-power design due to reduced supply/threshold voltage ratios
Low Power Design Essentials ©2008 2.33
Variability Impacts Leakage
130nm
30%
5X
0.9
1.0
1.1
1.2
1.3
1.4
1 2 3 4 5Normalized Leakage (Isb)
No
rmal
ized
Fre
qu
en
cy
Threshold variations have exponential impact on leakage
[Ref: P. Gelsinger, DAC’04]
Low Power Design Essentials ©2008 2.34
Variability Sources
Physical– Changes in characteristics of devices and wires.– Caused by IC manufacturing process, device
physics & wear-out (electro-migration).– Time scale: 109sec (years).
Environmental– Changes in operational conditions (modes), VDD,
temperature, local coupling.– Caused by the specifics of the design
implementation.– Time scale: 10−6 to 10−9 sec (clock tick).
Low Power Design Essentials ©2008 2.35
Variability Sources and their Time Scales
Signal CouplingSupply/
PackageNoiseTemperature ─
Modal OperationManufacturing ─
Wear-out
10-10-10-8 10-7-10-5 10-4-10-2 105-107
Low Power Design Essentials ©2008 2.36
Process Variations
Percentage of total variation accounted for by within-die variation(device and interconnect)
[Courtesy: S. Nassif, IBM]Technology Node (nm)
0%
10%
20%
30%
40%
250 180 130 90 65
Leff
w, h,
Tox, Vth
3/m
ean
Low Power Design Essentials ©2008 2.37
Threshold Variations Most Important for Power
10
100
1000
10000
1000 500 250 130 65 32
Technology Node (nm)
Me
an
Nu
mb
er
of
Do
pa
nt
Ato
ms
[Courtesy: S. Borkar, Intel]
Decrease of random dopants in channel increases impact of variation on threshold voltage
Low Power Design Essentials ©2008 2.38
Device and Technology Innovations
Power challenges introduced by nanometer MOS transistors can be partially addressed by new device structures and better materials– Higher mobility– Reduced leakage– Better control
However …– Most of these techniques provide only a one (two)
technology generation boost– Need to accompanied by circuit and system level
methodologies
Low Power Design Essentials ©2008 2.39
Device and Technology Innovations
Strained silicon Silicon-on-insulator Dual-gated devices Very high mobility devices MEMS - transistors
DG-SOI
FinFETGP-SOI
Low Power Design Essentials ©2008 2.40
Strained Silicon
Improved ON-Current (10-25%) translates into:• 84-97% leakage current reduction• or 15% active power reduction
[Ref: P. Gelsinger, DAC’04]
Low Power Design Essentials ©2008 2.41
Strained Silicon
Transistor Drive Current (mA/mm)
Tran
sist
or
Lea
kag
e C
urr
ent
(nA
/mm
)
[Ref: S. Chou, ISSCC’05]
Improves Transistor Performance and/or Reduces Leakage
1000
100
10
10.2 0.4 0.80.6 1.0 1.2 1.4 1.6
Std Strain Std Strain
PMOS NMOS
+25% ION +10% ION
0.04 × IOFF
0.20 × IOFF
Low Power Design Essentials ©2008 2.42
Beyond Straining
Hetero-junction devices allow for even larger carrier mobility
100
1000
10000
100000
5.2 5.4 5.6 5.8 6 6.2 6.4 6.6
Mob
ilit
y (c
m2 /
sec)
Lattice Constant (Å)
e Si
Ge, GaAs
InAs
InSbElectrons (intrinsic)Si + strain
[Courtesy: G. Fitzgerald (MIT), K. Saraswat (Stanford)]
Example: Si-Ge-Si hetero-structure channel
Low Power Design Essentials ©2008 2.43
Silicon-on-Insulator (SOI)
Reduced capacitance (source and drain to bulk) results in lower dynamic power
Faster sub-threshold roll-off (close to 60 mV/decade) Random threshold fluctuations eliminated in fully
depleted SOI Reduced impact of soft-errors But
– More expensive– Secondary effects
Thin Oxide
Substrate
FD
S D
G
Thinsiliconlayer
[Courtesy: IBM]
Low Power Design Essentials ©2008 2.44
Example: Double-Gated Fully-Depleted SOI
wellcontact
well
G (Ni silicide)
thin BOX(< 10nm)
thin SOI (< 20 nm)
wellSTI
sub
STI STI
sub
D S
VT control dopant (1018/cm3)
[Ref: M.Yamaoka, VLSI’04, R. Tsuchiya, IEDM’04]
90 nm bulk
65 nm bulk
45 nm bulk
32 nm bulk
65 nm FD-SOI
45 nm FD-SOI
32 nm FD-SOI
Standard deviation (a.u.)210
(VT)intext
intext(VT)
0.5
0.4
0.3
0.5
High dose
Low dose
VDD = 1.0 V
w/o
tSOI = 20 nmtBOX = 10 nm
0.2
0.1
0.0
-0.11.00.0-0.5-1.0
0.6
Well-bias voltage Vwell (V)
Th
resh
old
volt
ag
e V
T (
V)
Buried gate provides accurate threshold control over wide range
© IEEE 2004
Low Power Design Essentials ©2008 2.45
FinFETs – An Entirely New Device Architecture
UC Berkeley, 1999
• Suppressed short-channel effects• Higher on-current for reduced leakage• Undoped channel – No random dopant fluctuations
S = 69 mV/dec
[Ref: X. Huang, IEDM’99]
© IEEE 1999
Low Power Design Essentials ©2008 2.46
BackGated FinFET
Dra
in
Sour
ce
Gate
Fin Height HFIN = W/2
Gate length = Lg
Fin Width = TSi
Dra
in
Gate1
Sour
ce
SwitchingGate
Gate2Vth Control
Fin Height HFIN = W
Gate length = Lg
Back-gated (BG) MOSFETDouble-gated (DG) MOSFET
Independent front and back gatesOne switching gate and Vth control gate Increased threshold control
Low Power Design Essentials ©2008 2.47
New Transistors: FINFETs
Intel tri-gate
Berkeley PMOS FINFET
Manufacturability still an issue – may even cause more variations
GateDrain
Source
[Courtesy: T.J. King, UCB; Intel]
Low Power Design Essentials ©2008 2.48
Some Futuristic Devices
FETs with subthreshold swing < kT/q (I-MOS)
1.0E-11
1.0E-09
1.0E-07
1.0E-05
1.0E-03
0 0.2 0.4 0.6
VS = -1VVD = 0V
5 mV/dec.LI = 25 nmLGATE = 25nmtox = 1 nmtsi = 25 nm
ON
OFF
I-MOS
MOS
N+P+ I-MOS
Buried-Oxide
Poly
Impact Ionization Region
[Courtesy: J. Plummer, Stanford]
Zero OFF-current transistorUses MEMS technology to physically change gate control.Allows for zero-leakage sleeptransistors and advanced memories[Ref: Abele05, Kam05]
© IEEE 2005
Low Power Design Essentials ©2008 2.49
Summary
Plenty of opportunity for scaling in the nanometer age
Deep-submicron behavior of MOS transistors has substantial impact on design
Power dissipation mostly impacted by increased leakage (SD and gate) and increasing impact of process variations
Novel devices and materials will ensure scaling to a few nanometers
Low Power Design Essentials ©2008 2.50
ReferencesBooks and Book Chapters A. Chandrakasan, W. Bowhill, F. Fox (eds.), “Design of High-Performance Microprocessor Circuits”, IEEE Press 2001. J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective,” 2nd ed, Prentice Hall 2003. Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices,Cambridge University Press, 1998.
Articles Abele, N.; Fritschi, R.; Boucart, K.; Casset, F.; Ancey, P.; Ionescu, A.M., “Suspended-gate MOSFET: bringing new MEMS
functionality into solid-state MOS transistor,” Proc. Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp 479-481, Dec. 2005
BSIM3V3 User Manual, http://www.eecs.berkeley.edu/Pubs/TechRpts/1998/3486.html J.H. Chen et al, “An Analytic Three-Terminal Band-to-Band Tunneling Model on GIDL in MOSFET,” IEEE Trans. On Electron
Devices, Vol. 48 No 7, pp. 1400-1405, July 2001. S. Chou, “Innovation and Integration in the Nanoelectronics Era,” Digest ISSCC 2005, pp. 36-38, February 2005. P. Gelsinger, “Giga-scale Integration for Tera-Ops Performance,” 41st DAC Keynote, DAC, 2004, (www.dac.com) X. Huang et al (1999) "Sub 50-nm FinFET: PMOS“, International Electron Devices Meeting Technical Digest, p. 67. December 5-8,
1999. International Technology Roadmap for Semiconductors, http://www.itrs.net/ H. Kam et al., “A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics, “ IEDM Tech.
Digest, pp. 463- 466, Dec. 2005. K. Mistry et al, “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm
Dry Patterning, and 100% Pb-free PackagingProceedings,” IEDM, pp. 247, Washington, Dec. 2007. Predictive Technology Model (PTM), http://www.eas.asu.edu/~ptm/ T. Sakurai and R. Newton. “Alpha-power law mosfet model and its applications to cmos inverter delay and other formulas.,” IEEE
Journal of Solid-State Circuits, 25(2), 1990. R. Tsuchiya et al, “Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high- performance application featuring
wide-range back-bias control,” Proceedings IEDM 2004, pp. 631-634, Dec. 2004. M. Yamaoka et al, “Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology,” Digest of
Technical Papers VLSI Symposium, pp. 288-291, June 2004. W. Zhao, Y. Cao, “New generation of predictive technology model for sub-45nm early design exploration,” IEEE Transactions on
Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006