Scaling theory for information networks

Melanie E. Moses1,*, Stephanie Forrest1,4, Alan L. Davis2, Mike A. Lodder2

and James H. Brown3,4

1Department of Computer Science, and 3Department of Biology, University of New Mexico,Albuquerque, NM 87131, USA

2School of Computing, University of Utah, Salt Lake City, UT 84112, USA4Santa Fe Institute, Santa Fe, NM 87501, USA

Networks distribute energy, materials and information to the components of a variety ofnatural and human-engineered systems, including organisms, brains, the Internet andmicroprocessors. Distribution networks enable the integrated and coordinated functioning ofthese systems, and they also constrain their design. The similar hierarchical branchingnetworks observed in organisms and microprocessors are striking, given that the structure oforganisms has evolved via natural selection, while microprocessors are designed by engineers.Metabolic scaling theory (MST) shows that the rate at which networks deliver energy to anorganism is proportional to its mass raised to the 3/4 power. We show that computationalsystems are also characterized by nonlinear network scaling and use MST principles tocharacterize how information networks scale, focusing on how MST predicts properties ofclock distribution networks in microprocessors. The MST equations are modified to accountfor variation in the size and density of transistors and terminal wires in microprocessors.Based on the scaling of the clock distribution network, we predict a set of trade-offs andperformance properties that scale with chip size and the number of transistors. However,there are systematic deviations between power requirements on microprocessors andpredictions derived directly from MST. These deviations are addressed by augmenting themodel to account for decentralized flow in some microprocessor networks (e.g. in logicnetworks). More generally, we hypothesize a set of constraints between the size, power andperformance of networked information systems including transistors on chips, hosts on theInternet and neurons in the brain.

Keywords: metabolic scaling; networks; microprocessors

1. INTRODUCTION

Computer networks span a vast range of physical sizesand can have billions of components. For example,modern microprocessors contain billions of transistorsnetworked in a few square centimetres of surface area(C. Ludloff 2007, http://sandpile.org/). The Internetconnects half a billion hosts (Internet Systems Con-sortium 2008, http://www.isc.org/index.pl?/ops/ds/

host-count-history.php) and spans the 5!107 km2

surface of the Earth. The size of a network can bemeasured in terms of the number of nodes, in which casethe Internet is about the same size as a computer chip,or as the physical distance spanned by the links, inwhich case the Internet is 10 orders of magnitude larger.

Although computational complexity theory describesthe scaling properties of algorithms, and very-large-scaleintegration (VLSI) scalingdescribeshow somepropertiesof computer chips vary with process and transistorsize (Mead & Conway 1979), computer science lacks a

general predictive theory of network scaling. Forexample, how does wire length or power consumptionscale with the number of transistors on a chip? How willbandwidth demand and latency change as more hosts areadded to the Internet? Minimizing power consumptionand predicting bandwidth demand are important ques-tions in the design of these systems. Answers to suchquestions require a theory of network scaling: one thatdescribes how power consumption, latency and thephysical footprint of a network scale as functions ofsystem size, the number of components and the degreeof centralization.

Organisms also use networks to distribute energy,materials and information to individual components.We adapt the principles of metabolic scaling theory(MST; West et al. 1997; Brown et al. 2004) in order todescribe the scaling of engineered information net-works. The term ‘MST’ is used throughout the paper torefer to the original West, Brown and Enquist model(West et al. 1997). MST is extended to accommodatevariation in the size and density of network com-ponents. We also discuss how decentralized networkdesigns deviate from MST predictions that assume asingle central source of flow in the network. ‘The last

J. R. Soc. Interfacedoi:10.1098/rsif.2008.0091

Published online

Electronic supplementary material is available at http://dx.doi.org/10.1098/rsif.2008.0091 or via http://journals.royalsociety.org.

*Author for correspondence (melaniem@cs.unm.edu).

Received 2 March 2008Accepted 18 April 2008 1 This journal is q 2008 The Royal Society

mile’ (the interface between the network and thecomponents) and the degree of centralization in net-works emerge as important topics for future research inboth biological and information systems.

The paper is organized as follows. We review MSTand explain its implications for information networks,using the particular example of networks known asH-trees that are often used to distribute clock signals onmicroprocessors. We then show how certain engineeringtrade-offs cause systematic differences between networkscaling in microprocessors and organisms. We concludewith a discussion of how the MST approach offers avaluable theoretical perspective to guide and assess thedesign of many networked information systems.

1.1. Network scaling in organisms

Scaling describes how some property of a system, thedimension of a structure or the rate of a process, variessystematically with some other property. Many scalingrelations are described by power functions of the formYZY0X

b, where Y is a dependent variable, Y0 is anormalization constant, X is the independent variableand b is the scaling exponent. Our notation is sum-marized in table 1. We often ignore the normalizationconstant and write YfXb. The scaling exponentquantifies how one component of a system changeswith respect to another, e.g. how the volume of thecirculatory systemgrows to service an increasing numberof cells, or how the footprint of wire in a computerchip must grow to service an increasing number oftransistors. In biology, b is often a simplemultiple of 1/4;for example, metabolic rate (B) scales with body mass(M) as BfM3/4; blood circulation times, gestationperiod and lifespan (t) scale as tfM1/4 (Kleiber 1932;Peters 1983; Schmidt-Nielsen 1984; West et al. 1997).

MST posits that quarter-power exponents arise fromoptimized hierarchical branching resource distributionnetworks, such as mammal and plant vascular systems.These designs evolved under natural selection becausethey minimize the energetic cost of transportingresources while balancing the competing concerns ofperformance, speed and efficiency. According to MST,the delivery capacity of vascular networks scaleswith the 3/4 power of the volume of the network.Thus, larger networks in larger organisms deliver moretotal energy, but with diminishing returns. Becauselarger networks deliver less energy proportional to theirsize, rates of cellular metabolism are forced to decreasewith increasing body size. An alternative design inwhich the cellular metabolic rate remained invariantand the whole organism’s metabolic rate increasedlinearly with body size would require the volume ofthe network to increase nonlinearly as the 4/3 powerof body mass. It is easy to see why natural selectionhas not adopted this strategy. If a 2 g shrew has areasonable volume of blood to support its metabolism,say 0.1 g, a 2 ton elephant will require 100 tons of blood,an obvious impossibility.

The quarter-power scaling relation is derived math-ematically from the laws of physics (e.g. conservation ofmatter and energy and the laws of hydrodynamics) andfour fundamental constraints on the centralized,hierarchical networks that supply raw materials(oxygen and energy) for metabolism (West et al.1997), restated as follows:

—A. Cross-sectional area preserving. The summedcross-sectional area (Anet) at each hierarchical levelis constant throughout the network, so that flow rateis constant and impedance is minimized. Thus,AnetZAkNk for all k where Ak is the cross-sectional

Table 1. Glossary of notation.

symbol meaning

A cross-sectional areavol volumeM massP power (active power)V voltageB metabolic rateD dimensiont timeb scaling exponentNx number of components of type xL length of an edge in a networkK depth of a treek subscript denoting a level in a hierarchical branching network (kZ0 refers to the root)b branching ratio NkC1=Nk in a network (also called fanout)g length ratio Lk=LkC1

wk width of an edge at level k in the network (e.g. wire width)u width ratio wk=wkC1

r density (per unit area or volume)l process widthnet subscript denoting an entire networkorg subscript denoting an entire organismchip subscript denoting an entire computer chipc subscript denoting the lowest level component in a branching structure (e.g. capillary)tr subscript denoting transistors

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area of each branch at level k, and Nk is the numberof branches at level k. This implies that for the finalbranch of the network (the capillaries) AnetZAcNc.We note, however, that area preservation is violatedin the lowest levels of the hierarchy of thecardiovascular system to slow blood velocitythrough the capillaries and allow for diffusion ofoxygen (West et al. 1997).

— B. Space-filling. A hierarchical, self-similar andspace-filling network supplies resources to the entirethree-dimensional volume of the body. One way toachieve this is with a self-similar (or fractal) rule inwhich the lengths of branches decrease systematicallylower in the hierarchy. MST defines a length ratio as

gZLk

LkC1Z b1=3; ð1:1Þ

where Lk is the length of an edge at level k in thehierarchy, and b is the number of daughter branchesper parent branch. According to MST the 1/3exponent arises from self-similarity in three dimen-sions, which requires each branch to be proportionalto the radius of the volume of tissue to which itdelivers energy (West et al. 1997). In the electronicsupplementary material, we derive the MST predic-tion (for the two-dimensional case) for the length,Lnet, from the centre of the network to any leaf (i.e.the sum of all edge lengths from the aorta to anycapillary, assuming a balanced tree). In three dimen-sions the prediction is

LnetfN 1=3c Lc; ð1:2Þ

where Lc is the length of a capillary and Nc is thenumber of capillaries. SinceNc is the number of leavesin the tree, then NcZbK, where K is the depth of thetree.

—C. Terminal units are invariant. The lengths (Lc),cross-sectional areas (Ac) and delivery capacity ofcapillaries do not vary systematically withM. Assuming both the length ratio of equation (1.1)and invariant terminal units is a controversial aspectof MST (Makarieva et al. 2005a; Etienne et al. 2006),and we modify it in our analysis of microprocessorsin §3.1.

—D. Network volume (volnet) is proportional to M.Optimization principles (West et al. 1997) andempirical evidence (Peters 1983) show that, forexample, blood volume is approximately 7%of organism volume in mammals of all sizes. Becauseorganismvolume isproportional toM, thenvolnetfM.This constraint is also modified to cover the case ofmicroprocessors.

From the four constraints above, MST predicts howvolnet scales with Nc, the number of leaves of the tree.Given a balanced tree with cross-sectional area preser-ving, volnetZLnetAnet. From constraints (i) and (iii),and equation (1.2), volnetfAcLcN

4=3c . More generally,

in dimension D,

volnetfAcLcNðDC1Þ=Dc : ð1:3Þ

Because the constraints require volnetfM, and Ac andLc to be constant, N ðDC1Þ=D

c fM , allowing us to predictthe number (Nc) and density (rc) of capillaries in an

organism as follows: NcfMD=ðDC1Þ and rcfMK1=ðDC1Þ.Since each capillary delivers energy at the same rate,this gives the canonical 3/4 power scaling equation formetabolic rate, BfNcfMD=ðDC1Þ where DZ3.

Through these four constraints, MST provides amathematical explanation for D/(DC1) scaling inbiology. However, there are several controversiessurrounding MST. These fall into two general cate-gories. First, several authors suggest that the 3/4 powerscaling of metabolism is not universal, citing examplesfrom particular taxonomic groups, frequently mammals(White & Seymour 2003), and also across animals moregenerally (Glazier 2005; Makarieva et al. 2005b; butsee Savage et al. (2004) andMoses et al. (2008)). Similarcontroversy surrounds the assertion of a universalrelationship between temperature and metabolic rate.Regardless of whether there is universal networkscaling in biology or whether MST is accepted as thebest explanation for it, the scaling approach may still beappropriate in the domain of microprocessors and otherinformation networks.

More relevant to this work is a second set ofcriticisms that the model assumptions are eitherviolated, internally inconsistent or unnecessary togenerate D/(DC1) scaling. In particular, severalauthors have questioned the assumption of invariantterminal units, suggesting that capillaries may varyin size or, more importantly, may vary systemati-cally with body size (Dawson 2003; Kozlowski &Konarzewski 2004; Makarieva et al. 2005a). Thatcriticism is addressed in §3.1.1, where we modify thetheory to incorporate the widely varying sizes oftransistors into our model. We further relax theassumption that the length of the terminal wire in anetwork is constant. In our model, we estimate thedistance between transistors directly from theirdensity. Some have questioned whether self-similarspace filling (constraint B) is theoretically justified(Etienne et al. 2006) andwhether it is consistentwith theassumption of invariant terminal units (Kozlowski &Konarzewski 2004), but see Brown et al. (2005). In §3.1we show that the hierarchical H-tree that distributesclock signal on a chip follows the self-similar space-fillingpredictions when we allow terminal units to vary inlength. Finally, alternative models suggest that 1/4powers can be generated for any resource distributionnetwork without requiring fractal branching (Banavaret al. 1999). We adopt the fractal branching model inthis paper because it describes the H-tree so well.However, more general models that do not requirefractal branching may be appropriate to describe otherinformation networks. Despite these controversies,we believe that the MST formalism is relevant tocomputing and provides a starting framework forarticulating and testing hypotheses about how suchengineered systems scale.

1.2. Wire scaling on computer chips

Since microprocessors were first built in the early 1970s,the number of transistors on an integrated circuithas increased by five orders of magnitude (Mezhiba &Friedman 2002; Moore 2003). The increase is due

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J. R. Soc. Interface

largely to shrinking the size of transistors (measured inprocess width, l) by over 100-fold and increasing chiparea (Achip) by approximately 30-fold (see electronicsupplementary material). The increase in transistordensity (rtr), and commensurate increase in infor-mation processing power (measured in millions ofinstructions per second, MIPS), has required a 500-fold increase in the power to operate each chip, fromapproximately 0.2 W in 1978 to over 100 W today inIntel microprocessors (Moore 2003). Consequently,power and heat dissipation are now dominant con-straints on chip design. The total area consumed bywires (Anet) has increased superlinearly as a fraction ofAchip, and this is a significant component of the growthin power requirements. We examine how well MSTprinciples characterize the relationship between Achip,l, transistor density (rtr) and power (P).

Equations (1.1)–(1.3) can be used to derive thescaling behaviour of networks that distribute clocksignals on computer chips. We treat wires that delivercharge to transistors analogously to the arteries thatdeliver oxygen to cells. The wire network is subject tophysical laws (e.g. conservation of current as describedby Kirchoff’s Laws). Important properties of the chip,such as delay, heat generation and power consumption,are influenced by the physical lengths and cross-sectional areas of the wires. The flow of current throughthe network of wires and transistors is analogous to theflow of blood through the circulatory system.

Despite these similarities, there are importantdifferences between circulatory networks and wires onchips. First, organisms are three dimensional, but chipsare often referred to as 2.5 dimensional (Deng & Maly2004) because the area covered by transistors is twodimensional, but metal layers of wires extend into arelatively thin third dimension. Second, the circulatorysystem is fully centralized, with all blood originatingfrom and returning to the heart, but the logic networkson microprocessors are somewhat decentralized in thatnot all signals pass through any one part of the network.

To simplify the translation of MST to chips, we focuson the H-tree (shown in figure 1), which is a fullycentralized two-dimensional clock distribution net-work. The mapping between the vertebrate circulatorysystem and H-trees is straightforward. The simplestH-tree design has long, wide wires that branch intosuccessively shorter and narrower wires in quantitativeagreement with MST predictions for a two-dimensionalnetwork. Both are hierarchical, fractal-like, branchingtrees that deliver resource (clock signal or blood) from acentral source (clock or heart) to the leaves of the tree(terminal clock buffers or capillaries) that are distrib-uted throughout the area (or volume) of the system.The terminal clock buffers (or capillaries) deliver signal(or oxygen) to an area of chip or volume of tissue. Thearea to which a single clock buffer delivers signal iscalled the isochronic region and is important in ourtheory. Finally, we refer to the region where theterminal units deliver signals or energy to the com-ponents of the system (transistors or mitochondria) asthe last mile by analogy with telecommunicationsnetworks. Both networks enable the system to functionas an integrated whole by ensuring that resources aredistributed to all regions of the system.

The clock distribution system ideally presents aclock signal to all points of the chip simultaneously. Inpractice, simultaneity is impossible due to smallvariations in process, voltage and temperature (PVT)at different locations on the chip. The maximumdifference in clock arrival times under worst caseconditions is called skew, and H-trees illustrate atrade-off between minimizing skew and minimizingpower (Friedman 2001). Although other clock designsrequire less power, the H-tree provides identical pathlengths from the clock source to the leaves of the tree,reducing skew. Small differences in path lengths occur,primarily due to slight geometric irregularities inducedby cell set variations and automated design toolalgorithms. This is important for high-frequencyoperation, because skew is combined with the effective

number of terminal wires (Nc) = 64area of the isochronic region is 4squares

length of a terminal wire(Lc = 1/2 c

–1/2 = 1)isochronicregion

L0

Lc

L1

L2

wire widths decrease by half ateach branching ( = 1/2)wire lengths decrease by half ateach vertical step and at eachhorizontal step, so 2 = 1/2(e.g. L2/L0 = 1/2)

density of terminal wires is theinverse of the isochronic area( c = 1/4)

Figure 1. The H-tree, a two-dimensional hierarchical self-similar branching network that distributes clock signals on anintegrated circuit.

4 Scaling theory for information networks M. E. Moses et al.

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delay due to PVT variations and to worst case logic andwire propagation delays to determine the shortest clockperiod (or the highest frequency) at which the chip willoperate correctly. The fractal branching networkdescribed by MST actually describes idealized H-treesbetter than evolved biological networks because thebalanced tree design eliminates the possibility ofasymmetric side branches in the network.

2. METHODS

We obtained measurements of active power (P), clockfrequency ( f ), process size (l), chip area (Achip) andnumber of transistors (Ntr) for 516 microprocessorsmanufactured by Intel, AMD, Via and Cyrix from 1991to 2006 (see electronic supplementary material). Weincluded only those chips for which a single value ofevery variable was given, and we excluded multi-corechips. Most chips have several releases with differentspecifications, and each of these appears separately inour dataset. We also included data for each of sevenchips manufactured by Intel in the 1970s and 1980s (the4004 through the 486; Moore 2003; electronic supple-mentary material). In the case of the H-tree, we do nothave direct measurements of the total wire area(Anet) or density of the terminal units. Thus, the datareported in figure 2 were generated by simulationsdescribed below.

We follow standard methods to determine the scalingexponents from data by taking the log (base 10) of bothvariables and calculating a linear regression through thelog-transformed data. Different regression techniquescan lead to different scaling exponents (Warton et al.2006; O’Connor et al. 2007). Although ordinary least-squares (OLS) has been traditionally used, it assumesthat all errors occur in the dependent variable.

Reduced major axis (RMA) regression assumes thaterror is equally distributed between the dependentand independent variables. Since we do not know howerror is distributed in these data, we report exponentsobtained from both RMA and OLS regression with95% CIs for each. We suggest that these estimatesprovide reasonable upper and lower bounds for the truescaling exponent.

3. RESULTS

3.1. Scaling of the H-tree

In this section we translate constraints A (areapreserving) and B (space filling) to two dimensions topredict scaling of a simple two-dimensional H-tree.Then we show that clock trees violate constraints C andD and how that alters scaling properties.

—A. Wire width. Cross-sectional area preservingConstraint A becomes wire width preserving forthe two-dimensional clock tree when wires are kepton two metal layers that have constant wirethickness. The summed width of wires at eachhierarchical level allows impedance matching (mini-mizing signal reflections) and maintains constantcurrent density with minimal resistance throughoutthe network.Prediction. We define the wire width ratio, uZwk/wkC1, and note that uZb owing to the area pre-serving constraint, where wk is the width of eachwire at level k and b equals fanout. For an H-tree, uand fanout are equal to 2 at all nodes. Thus, themodel predicts that the wire width at each levelwill be 1/2 the wire width at the level above.Observation. Designs for efficient H-trees (Friedman2001) specify uZ2 (figure 1). These specificationsrequire that the sum of wire widths (wnet) at eachhierarchical level be constant, and wnetZwcNc. As anexample in figure 1, wcZ1 andNcZ64, so that wnetZ64. The same value of wnet is obtained for kZ0 sincew0Z32 and N0Z2.

—B. Wire length. The biological constraint B (net-works are space filling) translates to area filling fortwo-dimensional chips. Each parent H branchestwice to create a new child H, so we consider thescaling of parallel branches of the H, each of which istwo branching generations from its parent (forexample, L2 and L0 in figure 1).Prediction. In two dimensions, accounting for thetwo branchings to generate each H, we rewriteequation (1.1) as

g2 ZLk=LkC2 Z ð2bÞ1=2: ð3:1ÞGiven bZ2, then g2Z2; the length of the four wiresin a child H will be half the length of wires in theparent H.Observations. The length of wires in each daughter His 1/2 that of the parent H (figure 1), following MSTlength scaling predictions.

—C. Network area. For a perfectly balanced treewith area-preserving branching, AnetZwnetLnet.Using the length ratio in equation (3.1) and the

–4 –3 –2 –1 0 1 2 3 4 5 6–6

–4

–2

0

2

4

6

8

log (Anet) in mm2 from simulations

pred

icte

d lo

g (A

net)

in m

m2

Figure 2. Predicted versus simulated Anet. The open circlesshow the predictions of equation (3.2), which assumesinvariant terminal units. The filled circles show the predic-tions of equation (3.3), which sets the lengths of terminal wiressuch that they reach the centre of the isochronic region. Theslope close to 1 and high r2 indicate that equation (3.3) isa more accurate scaling prediction. Dashed line, RMAslopeZ1.25, r 2Z0.88; solid line, RMA slopeZ0.99, r 2Z0.999.

Scaling theory for information networks M. E. Moses et al. 5

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electronic supplementary material, we obtain a two-dimensional version of equation (1.2) for networklength (distance from the clock to any one leaf ):

LnetfN 1=2c Lc.Thus, the two-dimensional version of

equation (1.2) is

AnetfwcLcN3=2c : ð3:2Þ

Equation (3.2) shows that if the lengths (Lc) andwidths (wc) of terminal wires are constant, the areaof chip allocated to wire grows faster than the areaallocated to components.Accounting for variation in the size of terminal units.In MST Ac and Lc are invariant across body sizes,but in chips wc and Lc may vary substantially. Theminimum wc is determined by process size (l). Weassume wczl, although in some cases wc is slightlygreater than l due to artefacts of the design processand slightly irregular geometries created by vari-ations in logic complexity; this has negligible effecton the predictions. The lengths of the terminalH-tree wires (Lc) also vary. When the density ofterminal wires (rc) of the H-tree is lower, theterminal nodes are further apart, so the wires mustbe correspondingly longer in order to create a singleconnected H-tree. Dimensional analysis givesLcZ1=2rK1=2

c , where, by definition, rcZNc=Achip.This simply means that the terminal clock wire ishalf the length of the isochronic region, and thereforereaches the centre of the isochronic region as shownin figure 1. Additionally, the wire at the nexthierarchical level is twice as long and is thereforeable to connect terminal wires in adjacent isochronicregions.Prediction. Substituting in the variables wc and Lc,the network area equation becomes

AnetflNcA1=2chip: ð3:3Þ

If component density (rc) is held constant, thenequations (3.2) and (3.3) are equivalent. However, ifrc varies across chips, then equation (3.3) moreaccurately describes the scaling of H-trees.Observations. We do not have access to directmeasurements of Anet for clock trees on commercialchips. However we can simulate clock trees basedon the design shown in figure 1. We simulated64 H-trees by varying lZ ½10; 100; 1000; 10 000$ mm,NcZ ½16; 16; 256; 4096; 65536$ isochronic regions andAchipZ ½10; 100; 1000; 10 000$ mm2. We measuredAnet by summing the area of all wires in thesimulation for all combinations of these variables.We compared the measurements of Anet with thepredictions of equations (3.2) and (3.3). Figure 2shows that equation (3.3) is linearly related to thesimulations with a very high r 2, while equation (3.2)(which assumes invariant terminal units) has lowerr 2 and a slope greater than 1, indicating systematicdeviations from the data.

It would be beneficial to obtain these measure-ments for H-trees on manufactured microprocessors,particularly since the use of repeaters and restrictionson wire widths in different metal layers may alterthe dimensions of real H-trees from the idealizeddesign. We are pursuing such measurements for

future analyses.—D. Component density. In MST constraint D specifies

volnetfvolorg, which requires that the number of

capillaries (Nc) scales as MD=ðDC1Þ, and the densityof capillaries (rc) scales asM

K1=ðDC1Þ. Constraint D islikely to be violated in microprocessors becauseadditional metal layers are available to hold wirearea that scales superlinearly with the area of the chip.Predictions. A direct translation of Constraint D to atwo-dimensional network predicts AnetfAchip, and

rcfAK1=2chip . However, if constraint D is violated, then

there should be no systematic relationship between rcand Achip. We do not have direct measures of rc ondifferentmicroprocessors. However, rc is the inverse ofthe area of the isochronic region, so that frequency ( f )should be proportional to the radius of the isochronicregion. Thus, if we assume rcf f 2, then we expect norelationship between f and Achip, whereas MST would

predict ffAK1=4chip .

Observation. To test these predictions, we regressedf against Achip on our dataset of 523 micro-processors. The regression is only marginallysignificant (pZ0.013) and explains only 1% of thevariation in the data (r 2Z0.01). Thus, as we expectedthere is no meaningful scaling relationship betweenf and Achip.

3.2. Scaling on microprocessors

In order to test the predictions of MST on real data, weextrapolate the H-tree predictions to account for moregeneral properties of microprocessors for which dataare available.

3.2.1. Scaling of transistor density. The analysis in theprevious section suggests that there is little relationshipbetween the density of clock registers and Achip. Wegeneralize this analysis by treating all transistors asthe terminal units of the logic network on a micro-processor. Then, we can test whether there is arelationship between the density of transistors (rtr)and Achip by regressing the log of rtr against the logof Achip. As expected, the regression is not significant(pZ0.9). However, rtr is correlated with the processsize l: rtrflK2:2. Using OLS regression r 2Z0.92 andthe 95% CI is K2.2 to K2.3 (the RMA exponent isK2.3). This empirical scaling relationship is close towhat would be expected if the footprint of transistorswere a constant fraction of chip area. This is because alower bound on total transistor footprint can beestimated by assuming that the area of each transistoris the square of the minimum feature size (when in factsome transistors may be larger); then the summed areaof all transistors (Atr) isAtrfNtrl

2. To test whetherAtr

(using this estimate) is a constant fraction of chip area,we regress the log of Atr/Achip against the log of Achip.The regression is marginally significant ( pZ0.03 andr 2!0.01), which means that there is almost nocorrelation between the proportion of chip areaoccupied by transistors and Achip, and the proportionof chip area occupied by transistors is constant with

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respect to Achip. To recap, MST posits that componentdensity decreases as the mass of the organism increases,but the data suggest that in microprocessors thedensity is unchanged as the chip area increases.

The 2.5-dimensional geometry of microprocessorsmay explain how transistor density is held constant asAchip increases. Equation (3.3) can be used to predicthow Anet increases with Achip and therefore, how thenumber of metal layers increases with Achip. Substitut-ing rtrf1=l2 into equation (3.3) gives AnetfA3=2

chip=l.Since the network of wires is contained on metal layersand on the silicon layer that holds transistors, weestimate Anet as Anetf ðNmetalC1ÞAchip, where Nmetal isthe number of metal layers. Thus, we predict

lðNmetalC1ÞfA1=2chip. Figure 3 shows this relationship

empirically. The OLS estimate of the scaling exponentis 0.53 (which is indistinguishable from the prediction of1/2), and the RMA exponent is slightly higher (0.7).The data on metal layers (C. Ludloff 2007, http://sandpile.org/) include 32 microprocessors from thedataset described previously. These results show that,once l is accounted for, the number of metal layersincreases predictably with chip area. This correlationhelps explain the reason for transistor density being notdirectly constrained by chip area: as area increases, thenumber of metal layers increases to accommodateexcess wire area, reducing interference between routingwires and placing transistors.

3.2.2. Power scaling prediction. It is important tounderstand wire scaling because the footprint of thewire influences the amount of power required to operatea chip. Wire length is often estimated using Rents Rule(Stroobandt 2001), but we use scaling theory andestimate Anet from equation (3.3). We use this estimateofAnet to predict active microprocessor power, and thenwe test those predictions against empirical data. To dothis, we assume that the other on-chip networks, suchas logic, power and memory, have similar scaling

characteristics as H-trees. This and the other assump-tions given below are almost certainly overly simplistic,but they serve as a starting point. Even this preliminarytheory reveals interesting features of power scaling inmicroprocessors.

The equation for active power is PZaCV 2f(Mezhiba & Friedman 2002), where P is active power,C is capacitance, a is an activity factor that representsthe average percentage of C that is exercised, V isvoltage and f is frequency. We use equation (3.3) totransform the power equation into a form that relatespower to available data on die area, number oftransistors, process size, voltage and clock frequency.

Capacitance is a complicated variable, but it can beestimated as CZQAnet (Ho 2003) where wire complex-ities (such as the m-factor, wire pitch and wire aspectratio) are subsumed in Q. As an initial estimate, weassume thatQ and a are constant factors, so that we canapproximate PfAnetV

2f . Because this equationmeasures the active power of all wires on the chip, theformula forAnetmust account for the footprint of all wirenetworks. By replacing the terminal units of the clocktree (Nc) with the terminal units of all wires (the numberof transistors, Ntr), we assume that other on-chipnetworks scale similarly to the clock tree.

With these assumptions, we can estimate P usingequation (3.3),

PflV 2NtrA1=2chipf : ð3:4Þ

3.2.3. Observations. Figure 4 shows a strong correlationbetween the prediction (equation (3.4)) and observedpower across the 523 microprocessors. The r 2 is 0.79.A scaling exponent equal to 1 would indicate a closecorrespondence between theory and data. However,the scaling estimates are significantly lower than 1 (theOLS estimate is 0.47 and RMA is 0.53), indicatingsystematic deviations between the theoretical predic-tions and the data.

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Figure 3. The number of metal layers increases with chip areaas predicted by equation (3.3). The y-axis represents thenumber of layers containing wire (the number of metal layersplus the silicon layer) multiplied by the process size, and thex-axis represents chip area. The scaling exponent is 0.53(OLS) and r 2 is 0.57. Data are from (C. Ludloff 2007, http://sandpile.org/).

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Figure 4. Power measured on microprocessors versus powerpredicted by equation (3.4) (PflV 2NtrA

1=2c f ). The scaling

exponent is approximately 1/2. The exponent is significantlyless than 1, indicating systematic differences between thescaling prediction and observations. The seven Intel chipsfrom the 1970s and 1980s do not significantly affect thescaling exponent.

Scaling theory for information networks M. E. Moses et al. 7

J. R. Soc. Interface

Thus, equation (3.4) does not provide an adequateexplanation for power scaling. However, a regressionanalysis showed that active power is strongly correlatedindividually with each of l;Ntr andAchip across a varietyof microprocessors (data not shown). The strongcorrelation suggests that these variables are relevantto predicting power, but the form of the equation is notcorrect. As a first step towards improving the theory, weperformed a multiple regression to understandinteractions among the variables. Notably, Achip wasan insignificant term in the multiple regression wheninteraction terms were included.

3.2.4. An alternative scaling prediction for power.Finally, we test whether an alternative equation forAnet gives predictions for power that are moreconsistent with the data. In the electronic supple-mentary material, we derive a prediction for the lengthof the H-tree from the central clock to any leaf of thenetwork, andAnet is derived from that length. However,some networks may not be centralized like the H-tree.For example, in the logic network, wires are not routedfrom each transistor to a centralized control point.Instead, many wires connect transistors or cells that arelocated nearby. Intelligent place and route algorithmsare used to minimize wire length by placing connectedcells in close proximity.

Alternatively if we assume that the length of eachwire scales as the distance between nearest components,then we can estimate the length of each wire from the

density of components, lfrK1=2c . Then we estimate Anet

fNll and given PfAnetV2f predict

PflV 2N 1=2tr A1=2

chipf : ð3:5Þ

The only difference between equations (3.4) and (3.5) isthat the exponent on Ntr changes from 1 to 1/2.

Observations. Figure 5 shows a close correspondencebetween the data and the alternative prediction(equation (3.5)). The slope is only slightly less than 1,(OLS estimated slope is 0.82, RMA is 0.95 with 95% CIbetween 0.76 and 0.99, r 2 is 0.75). The figure excludes

the seven Intel chips from the 1970s and 1980s becausethey appear to be systematically different. Includingthem, the 95% CI is 0.74–0.93. The extreme outliers inthe lower right corner are Intel Xeon Cascade chips thathave unusually large L2 caches. Because our predictiondepends on area and the L2 caches are less active thanother regions of the chip, these chips dissipate less powerthan we predict. If those points are excluded from theregression, the r 2 increases and the scaling exponentincreases so that it is indistinguishable from 1. Weconclude that this decentralized model is more consist-ent with observed power than the centralized model.

3.3. Scaling in other information networks

MST suggests that delivering resources from a centralsource to all parts of an organism is a dominant designconstraint and that efficient solutions to this problemhave evolved via natural selection. We used a similarapproach to characterize constraints in the design ofH-trees and found that the footprint of the H-tree scalesconsistently with MST. However, power requirementsappear to scale differently, consistent with a decen-tralized scaling model. The framework can be extendedto other information networks.

Table 2 highlights seven network properties thathave analogous function in biological networks(illustrated by the circulatory system) and threeinformation networks: the brain, microprocessors andthe Internet. In each system there is a network thatdelivers matter, energy or information to componentsdistributed in physical space. All of these systems aredesigned to maximize some aspect of performanceunder time or power constraints. The optimizingprocess in biology is natural selection; in human builtsystems, it is engineering principles and economics, andin the case of the Internet, self-organization may alsoplay a role. Our results suggest that engineered andnatural systems have developed networks to achievesimilar design goals under similar constraints.

We expect all of these systems to be subject to thefundamental constraint in equation 1.3 so that the sizeof the network increases faster than the number ofcomponents. Thus we expect ðDC1Þ=D scaling ofnetwork size with system size; when network size isconstrained to be linear with system size, we also expect1/D scaling of density and D=ðDC1Þ scaling ofperformance.

The mapping between physical network links andthe material that flows through them is straightfor-ward. All of these networks are built from componentsthat obey the laws of physics, such as conservation ofcurrent or fluid flow through the network. Theseconstraints can be accommodated in different ways,as illustrated by differences between the H-tree and thecirculatory network. Other network properties, such asdecentralization and connectivity patterns, mayfurther alter the scaling constraints.

Additionally, each system has an interface betweenthe network and the components it services. This lastmile determines, for example, how oxygen travels froma capillary to a mitochondrion or how a clock signalmoves from a clock buffer to a flip flop or latch in the

0.5 1.0 1.5 2.0 2.50.5

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1.5

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2.5

log predicted power from decentralized model

log

obse

rved

pow

er

Figure 5. Power measured on microprocessors versus powerpredicted by equation (3.5) (PflV 2N 1=2

tr A1=2chip f ). The scaling

exponent is close to 1 (OLSexponent is 0.82, theRMAexponentis 0.95, 95% CI is 0.76–0.99). Excluding the outliers in thelower right, the scaling exponent is indistinguishable from 1.

8 Scaling theory for information networks M. E. Moses et al.

J. R. Soc. Interface

isochronic region serviced by that clock buffer. MSTdoes not yet address the role of the last mile, but it playsan important role in all of these systems and is an areawhere MST might be fruitfully extended.

Figure 6 shows scaling relationships for threesystems from table 2 (scaling relationships for chipsare shown in figures 2–5). As a preliminary test of theMST-inspired hypothesis, we can compare empiricaldata with the D=ðDC1Þ predictions of MST. The dataillustrate different ways to incorporate network scalinginto the system design. Three-dimensional organismsare subject to constraint D (volnetfvolorg), so that thescaling of metabolism and the products of metabolism(such as biomass production) follow BfM 3=4. In three-dimensional brains, the data show volnetfN 4=3

c

(following equation 1.3) where volnet is approximatedby the volume of white matter (axons), and Nc isrepresented by the volume of grey matter (neuron cellbodies). The Internet covers the two-dimensionalsurface of the Earth and shows 2/3 power scaling ofbandwidth, suggesting that the rate of communicationper host slows by 1/(DC1) scaling as the number ofhosts increases. In this case, the density of hosts is notreduced, but the proportion of processing that usesthe network is reduced. Figure 3 shows that the areaof the network scales faster than the area of the chip,necessitating additional metal layers. These are verydifferent networks, but they face a common constraint:resources are distributed through a network that scalessuperlinearly with the number of components to whichit delivers energy or information.

4. DISCUSSION

We extended the MST framework to characterize thescaling behaviour of microprocessors, particularlyfocusing on the clock trees. The two most importantextensions were relaxing the assumption of invariantterminal units (allowing lengths of terminal units to

vary with their density) and accounting for decentra-lized networks. The H-tree is an example of aninformation network that is geometrically and func-tionally similar to vascular networks. It is a centralized,hierarchical distribution network designed to optimizepower and performance within a constrained physicalspace. In the H-tree, as in vascular networks, the size ofthe network grows faster than the number of com-ponents it connects.

While a common scaling framework describes H-treesand cardiovascular systems, there are importantdifferences in how networks scale in the two systems.The widths of terminal wires in H-trees are determinedby process size (l) and lengths of terminal wires changewith their density (and therefore with the area ofisochronic regions and frequency of the clock), but theyare hypothesized to be approximately invariant inorganisms. When terminal wires are allowed to vary,the predicted clock tree footprint (Anet) changes fromequation (3.2) to (3.3). However, these equations do notaccount for an important innovation in clock trees, whichallows wire width and power to be reduced, violating theassumption of width-preserving branching. This inno-vation, the use of repeaters to amplify the clock signal,produces more efficient clock tree designs. Accountingfor repeaters in the model is left for future work.

The systems also accommodate super-linear networkscaling differently. Organisms decrease componentdensity in order to keep network volume linear withorganism volume, while integrated circuits keep com-ponent density constant but use the third dimension tohold excess wire area. Our predictions for H-tree scalingare consistent with both the simulations and empiricalmeasurements of metal layers (figures 2 and 3).

We hypothesized that the excess wire associatedwith larger chips would result in a predictable increaseof active power with Achip. Although there is a positivecorrelation between our predictions and the obser-vations, there are systematic deviations, and Achip is

Table 2. Mapping between biological and information networks.

circulatory system brain chips Internet

components capillaries/mitochondria

neurons transistors hosts

links blood vessels dendrites, axons wires fibrewhat flows blood (oxygen, glucose) action potentials charge carriers

(electrons)packets (information)

the last mile capillary tomitochondria

synapse isochronic region (forclock trees)

local area network

network properties hierarchical, fractalbranching, space-filling, threedimensions

neural connectivity,space-filling, threedimensions

hierarchical,space-filling,2.5 dimensions

hierarchical,space-filling,two dimensions

what is optimized maximize metabolicrate, minimize trans-port costs and times

maximize informationprocessing, minimizemetabolic demand

maximize processingminimize power

maximize throughputminimize latency

fundamental principles conservation of energyand matter

conservation of energyand matter

Kirchhoff’s laws (con-servation of currentand voltage)

telegrapher’s equation

driving process natural selection natural selection engineering economics engineering economicsself-organization

Scaling theory for information networks M. E. Moses et al. 9

J. R. Soc. Interface

not an important determinant of power consumptionwhen other variables are taken into account. Thedeviations may occur because we subsumedmuch of thecomplexity of power analysis into scaling constants.Alternatively, the assumption that other on-chip net-works such as logic, power and memory have scalingproperties similar to those of H-trees may be incorrect.These networks have different functions and perhaps

topologies that scale differently. Finally, we note thatarea and density are each related, but in differentways, to aspects of the fabrication process that are notincorporated directly into the model. Area directlyaffects yield, which is the expected fraction offabricated chips that are operational. Hence area isdependent upon material and fabrication quality.Density is influenced by l and the number of availablemetal layers associated with the fabrication process.

Given the strong correlation between power and thevariables in equation (3.4), we tested an alternativemodelof network scaling. We found that a model that assumeda completely decentralized network in which eachcomponent was connected only to its nearest neighbourwas a better predictor of power than the centralizedmodel. In this alternative model, the footprint of thenetwork depends on the density of components ratherthan the size of the system. Thus, active power scalesas though the relevant networks (perhaps primarily thelogic network) are decentralized, but the metal layersscale like the network footprint (perhaps dominated byglobal networks such as the H-tree) scales consistentlywith MST predictions for centralized networks. Therelationships between power, wire scaling and componentdensity are of practical significance because all threeproperties are key to chip performance (Mezhiba &Friedman 2002). More research is needed to understandthese scaling relationships.

Equations (3.1)–(3.5) are first steps towards ascaling theory for information networks. Our goal isto develop a predictive theory for microprocessors thatis derived from first principles. Such a theory would bean important contribution for several reasons. First, itwould provide engineers a quantitative metric for theirdesigns in terms of a theoretical ideal. This wouldinform decisions about when to continue optimizing acurrent design strategy versus looking for radicalinnovations. Because the predictions of the MST-inspired scaling theory arise from structural ratherthan behavioural properties, this approach couldpotentially provide a new tool for predicting per-formance. Currently, new designs are evaluated usingexpensive simulations. Because the simulations are sotime-consuming, it is not feasible to test multitudes ofdesigns in detail, nor is it feasible to obtain preciseresults. A theory that can predict hard-to-measureproperties, such as power, from easy-to-measureproperties, such as process width and transistorcount, would be a welcome contribution, even if thepredictions are initially somewhat crude. However, it isimportant to respect the limits of precision that areinherent in an order-of-magnitude scaling theory. Thecurrent formulation is not detailed enough to predictthe exact power requirements of any specific design.

The scaling approach could be useful for character-izing other on-chip networks. For example, H-trees areused in dynamic random access memory (Jouppi2006), asynchronous chips (Takamura & Fukasaku1997) and field programmable gate arrays (Zhu &Wong 1997). Hierarchical designs that attempt tomitigate geometric scaling are evident in cachehierarchy and power networks. Multi-core chipsaddress the clock tree scaling problem by reducing

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Figure 6. Scaling relationships in biological and compu-tational systems. The slope of the fitted regression line on log-transformed axes gives the scaling exponent, b, for (a); therate of biomass production due to growth and reproduction asa function of body mass in different groups of organisms(observed bZ0:76, predicted bZ3=4, figure from Ernest et al.2003); (b) volume of grey matter (neurons) as a function ofwhite matter (axons) in mammalian brains (observedbZ1:23, predicted bZ4=3, figure from Harrison et al. 2002);(c) Internet backbone bandwidth as a function of theprocessing power of the Internet hosts (observed bZ0:66,predicted bZ2=3, data from Moore (2003), Internet SystemsConsortium (2008, http://www.isc.org/index.pl?/ops/ds/host-count-history.php) and Zakon (2006)).

10 Scaling theory for information networks M. E. Moses et al.

J. R. Soc. Interface

the distance that any signal has to travel to withina given core. However, multi-core architectures intro-duce new networking problems, arising from the needto coordinate activities among the different cores.‘Networks on chip’ have been proposed for distributingcontrol and data messages among cores and othercomponents. Further extensions of MST could helppredict the limits of this design strategy.

Extending scaling analysis to other networks revealsadditional commonalities among disparate systems.For example, brains and microprocessors allow wiresto scale in a different dimension than the components toaccommodate super-linearwire scaling. Inbrains, neuroncell bodies (grey matter) cover the two-dimensionalsurface of the brain, while axons and dendrites (whitematter) fill the interior three-dimensional volume,similar to the engineering solution of using a two-dimensional surface to hold transistors and metal layersthat extend into the third dimension to hold wires.Another common feature across these networks is theinterface between the network and the components (thelast mile). In many cases, resource flow through the lastmile is considerably slower than flow through thenetwork. For example, blood is pumped quickly throughlarge arteries, but oxygen slows to diffusive speeds to exitcapillaries and enter cells; wire speeds on the silicon layerare slower than that onmetal layers;wireless connectionsto the Internet are slower than backbone connections.The difference between speed through the network andthat through the last mile probably has significantimpact on system performance and could perhaps bedescribed by extending MST.

An important issue for further investigation is howthe degree of centralization affects network scaling.Some networks are highly centralized (e.g. the cardio-vascular system and the H-tree), while others (e.g.brains and the Internet) have no central controller orrepository of information. Multi-core architectures arenow the focus of the microprocessor industry; in thesedevices there is centralization within each core but eachcore functions autonomously. These decentralizedsystems may exhibit different scaling exponents. Evenin the case of H-trees, there has been a trend towardsdecentralization by inserting repeaters at branchpoints. Repeaters allow a signal to be sent from thecentral clock and amplified as needed to reachcomponents. This innovation is primarily motivatedby signal integrity issues that becomemore problematicat smaller process geometries and may reduce powerrequirements and alter the prediction shown inequation (3.3). Our initial predictions for power scalingon microprocessors assumed that the wire networksthat consume most of the power are centralized likethe H-tree; that assumption is untested and mayexplain why equation (3.4) does not match obser-vations. We tested an alternative scaling model inwhich wires connect only local components, and thatmodel was more consistent with empirical data. Thus,it appears that network scaling on microprocessorsdepends on both the density of components andthe area of the chip. This is similar to observations inurban road networks: the area or ‘lane-miles’ occupiedby these road networks depends on both the density of

the population and the physical area of the city(Samaniego & Moses in press). Accounting for partialdecentralization in networks is a fruitful area forfuture research.

Natural selection and engineering have indepen-dently converged on similar network designs. Eventhough these processes are distinct, they rely oncompetition and optimization within some constraintspace. We have shown one case of how evolution andengineering have discovered similar network designprinciples; we think there are others. In comparingorganisms with engineered systems, it is importantto note that organisms are the result of billions ofyears of evolution, while chip designs have beenoptimized by engineers for only a few decades. Inthese engineered systems, some aspects are locked into ensure backward compatibility (e.g. the applicationprogrammer interface), but other components arecontinually modified (e.g. materials and process tech-nology). This contrasts with biological systems inwhich evolution locked into certain design elementslong ago. Eventually, as component features such asprocess size reach their physical limits, and as the limitsof this architectural regime are approached, we expecteither radical innovations or engineering solutions thatlook more biological.

The authors thank anonymous reviewers for constructivecomments on earlier versions of this manuscript and GeorgeBezerra who contributed valuable insights and made sugges-tions. We also gratefully acknowledge the support of NSFgrant CCF 0621900 and the Santa Fe Institute. M.E.M. andJ.H.B. acknowledge partial support from NSF DEB-0083422and Los Alamos grant W-7405-EN6-36; M.E.M. acknowl-edges partial support from NIH P20 RR-018754; S.F.acknowledges partial support from NSF CCR-0331580 andCCR-0311686 and AFOSR FA9550-07-1-0532; and A.L.D.and M.A.L. acknowledge funding from NSF 162 941 and NSF0430063 and thank HP Laboratories for its support.

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