iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor

• Video analysis technology– Healthcare, HMI,

surveillance, intelligent vehicle…

• Challenges– Privacy:

• Video data revealed from inter-chip traffic

– Throughput: • Traffic mismatch slows down

processors

– Power: • parallel access of data memory

1

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XETAL-II (ISSCC’07)

Data Production: 430Gb/s

Data Consumption: 2.7Gb/s

Parallel Memory Access (2R1W/cycle)

iVisual Architecture

2

AHB Interface (2 Masters)

Global Processor

(GP)

Bitplane Memory

CMOS Image Sensor (CIS)

External Bus (AHB 2.0)

iVisual ChipDecision Feedback

Feature Processor

(FP)

Decision Processor

(DP)

Parallel-to-scalar processor36% throughput increase

Bitplane-based storage, reduced data portReduce 43% process area

Light-in, answer-out SoC architecture, no video data revealed to externalAvoid possible privacy problems

Additional memory hierarchy between SIMD array and memory62% power reduction

Results

3

Connected Component Extraction

131K

55K

Elliptical Matching

18K

12K

16-bin Histogram

8K

2K

Image Sub-Sample

6K

0.3K

Cycle/Frame : XETAL-II Architecture Model

: iVisual

Peak Power Efficiency (GOPS/W)

w/o PE cachew/o FP

39

103

205

iVisual

62%

50%

iVisualIMAP-CE [3] Xetal-II [2]

76.8

0.37

51.23.25

1070.6 x 4.5

205

4016

Peak Power Efficiency (GOPS/W)

Throughput increase

Power efficiency