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ISSCC 2008 Student Forum An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder • Tinoosh Mohsenin • Electrical & Computer Engineering, UC Davis [email protected] • PhD, graduation date: 2008 • Adviser: Professor Bevan Baas • Research areas • Energy efficient and high performance signal processing and error correction architectures • Multi-gigabit full-parallel LDPC decoders • UC Davis • BS from Sharif University • MS from Rice University

ISSCC 2008 Student Forum An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder Tinoosh Mohsenin Electrical & Computer Engineering, UC Davis [email protected]

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Page 1: ISSCC 2008 Student Forum An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder Tinoosh Mohsenin Electrical & Computer Engineering, UC Davis tmohsenin@ucdavis.edu

ISSCC 2008 Student Forum

An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder

• Tinoosh Mohsenin• Electrical & Computer Engineering, UC Davis• [email protected]• PhD, graduation date: 2008• Adviser: Professor Bevan Baas• Research areas

• Energy efficient and high performance signal processing and error correction architectures• Multi-gigabit full-parallel LDPC decoders• Many-core processor architecture design

• UC Davis• BS from Sharif University • MS from Rice University

Page 2: ISSCC 2008 Student Forum An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder Tinoosh Mohsenin Electrical & Computer Engineering, UC Davis tmohsenin@ucdavis.edu

ISSCC 2008 Student Forum

Research Overview

Row processing

Column processing

100001010

010100001

001010100

001100010

100010001

010001100

HH=

• Low Density Parity Check (LDPC) decoders

• Algorithms• Architecture• High energy efficiency• High throughput

• LDPC codes applications• 10 Gigabit Ethernet (10GBASE-T)• WiMAX• Digital Video Broadcasting (DVB-S2)

• T. Mohsenin et al., ICCD, Oct 2006• T. Mohsenin et al., ICASSP, Apr 2007• A. Blanksby et al., JSSC, Mar 2002

Encoder Decoder

Noise

Channel

ethernet cablewirelesshard disk

Page 3: ISSCC 2008 Student Forum An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder Tinoosh Mohsenin Electrical & Computer Engineering, UC Davis tmohsenin@ucdavis.edu

ISSCC 2008 Student Forum

Multi-Split-Row vs. Standard Decoder

Mem

ColRow

Standard decoder

Multi-Split-Row decoderSp1Sp0 Spn-1

MemMem

Col Col

Mem

ColRowRowRow

SignSp0_1

SignSp1_0

SignSp1_2

SignSp2_1SignSpn-2_n-1SignSpn-1_n-2

H =

11

11

11

11

11

1

1

1

1

11

11

11

11

1

1

11

1 1

1

1

1

1

1

1

11

1

1

1

11 1

1

1

11

1

11

1

1

HSplit-Sp0 HSplit-Sp1 HSplit-Spn-1

H =

11

11

11

11

11

1

1

1

1

11

11

11

11

1

1

11

1 1

1

1

1

1

1

1

11

1

1

1

11 1

1

1

11

1

11

1

1

N columnsrow weight=Wr

N/Spn columnsrow weight=Wr/Spn

N/Spn columnsrow weight=Wr/Spn

N/Spn columnsrow weight=Wr/Spn

Page 4: ISSCC 2008 Student Forum An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder Tinoosh Mohsenin Electrical & Computer Engineering, UC Davis tmohsenin@ucdavis.edu

ISSCC 2008 Student Forum

0 2 4 6 8 100

0.5

1

1.5

2

2.5

18.2 mm2 8.8 mm2 5.0 mm2

Split-4 decoder

Split-2 decoder

standard decoder

Decoder Implementation Results

10GBASE-T Code

65 nm, 1.3 V

Standard Split-2 Split-4

Split-4 Improve.

Area Utilization 25% 50% 90% 3.6x

Avg. Wire length (μm) 175.2 115.5 73.8 2.4x

Speed (MHz) 12.5 45 133 10.6x

Throughput (Gbps) 1.7 6.1 18.2 10.6x

Energy per bit (pJ/bit) 141 79 46 3.1x

• (2048,1723) LDPC code adopted by 10GBASE-T

This work

Energy per Decoded bit per Iter (pJ/bit/iter)

Nor

mal

ized

Thr

ough

put

per

Are

a (G

bps/

mm

2 )

In the plot:• 65 nm, 0.85 V• Throughput normalized to 15 iterations• Area: quadratically scaled with feature size, adjusted with row and column weights• Speed: linearly scaled with feature size• Energy: linearly scaled with feature size, quadratically scaled with voltage

[1] A. Blanksby et al., JSSC, Mar 2002[2] M. Mansour et al., JSSC, Mar 2006[3] A. Darabiha et al., CICC, Sep 2007

Darabiha

Mansour

Blanksby

Higher performance per

area, and lower energy