Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter

Inverter PWM signals

SMPS PWMs

+16 V

-8 V

DC bus sensing

NTC output

+24-V DC

VDC_PLUS

C20

00 L

aun

chP

AD

inte

rfac

e

Gate drive

signals

Reinforced isolated

IGBT gate driver ±

ISO5852S

IGBT power module

HALF BRIDGESMPS

+16 V

-8 V

IGBT brake

VDC_MINUS

Inverter output

TI DesignsIsolated IGBT Gate Driver Evaluation Platform for 3-PhaseInverter System

TI Designs Design FeaturesThis reference design consists of a 22-kW power • 3-Phase Inverter System Withstage with TI’s new reinforced isolated IGBT gate – 1200-V Rated IGBT Module of Current Ratingsdriver ISO5852S intended for 3-phase inverters in From 50 to 200 A (Supporting Multiple Vendors)various applications like AC drives. This design allows

– Seven Reinforced Isolated IGBT Gate Drivers:performance evaluation of the ISO5852S in a 3-phaseISO5852S With Working Voltage Isolation ofinverter incorporating 1200-V rated IGBT modules of1.5 kVRMS With Minimum CMTI of 50 kV/μscurrent ratings ranging from 50 to 200 A.

• Incorporates Protection Against Overcurrent andaFalse Turn ON UsingSome of the important functionality and performance

evaluated are short circuit protection using DESAT – DESAT Detectiondetection, soft-shutdown, effectiveness of the Active

– Soft ShutdownMiller Clamp at different inverter dv/dt, ESD, and EFT– Active Miller Clampperformance of the IGBT gate driver at system level

derived from adjustable speed electrical power drive • Meets IEC61800-3 EMC Immunity Requirements:systems (IEC61800-3). Piccolo LaunchPad

– ±8-kV ESD CD per IEC 61000-4-2LAUNCHXL-F28027 generates the PWM signals– ±4-kV EFT per IEC 61000-4-4required for controlling the inverter.

• Onboard Half-bridge Isolated Power SupplyDesign Resources Generating 16 V/–8 Vfor Gate Drivers WithProvision to Operate Gate Drivers With Unipolar or

Design FolderTIDA-00195 Bipolar Supply With External BJT/MOSFET BuffersISO5852S Product Folder • Can Configure Gate Driver Input for Inverting orAMC1200 Product Folder Non-Inverting OperationSN6501 Product Folder

• Option to Evaluate the System WithUCC27211 Product Folder– Twisted Pair Cable Between the Gate DriverCSD88537ND Product Folder

and IGBTTPS54286 Product Folder– External Capacitance Between Gate andLP38691 Product Folder

EmitterSN74ALVC125 Product Folder

Featured ApplicationsASK Our E2E Experts • Industrial Variable Speed DrivesWEBENCH® Calculator Tools • Servo Drives

• Solar Inverters• UPS

1TIDUA15A–June 2015–Revised August 2015 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter SystemSubmit Documentation Feedback

Copyright © 2015, Texas Instruments Incorporated

http://www.ti.com/tool/TIDA-00195

http://www.ti.com/product/ISO5852S

http://www.ti.com/product/AMC1200

http://www.ti.com/product/SN6501

http://www.ti.com/product/UCC27211

http://www.ti.com/product/CSD88537ND

http://www.ti.com/product/TPS54286

http://www.ti.com/product/LP38691

http://www.ti.com/product/SN74ALVC125

http://e2e.ti.com/

http://e2e.ti.com/support/development_tools/webench_design_center/default.aspx

http://e2e.ti.com

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=TIDUA15A

FromController

FromController

FromController

FromController

FromController

FromController

ISO

LAT

ION

ISO

LAT

ION

ISO

LAT

ION

ISO

LAT

ION

ISO

LAT

ION

ISO

LAT

ION

VBUS VBUS VBUS

VGND VGND VGND

+16 V +16 V +16 V

+16 V+16 V +16 V

+5 V

+5 V

± 8 V ± 8 V ± 8 V

To ADC or Controller

± 8 V ± 8 V ± 8 V

+

+

TI'DYH¶V

ControlCenter

Introduction to IGBT Gate Drivers www.ti.com

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and otherimportant disclaimers and information.

1 Introduction to IGBT Gate DriversInsulated gate bipolar transistors (IGBTs) are considerably used in 3-phase inverters that have numerousapplications like variable-frequency drives that control the speed of AC motors, uninterruptible powersupply, solar inverters, and other similar inverter applications.

IGBTs have the advantages of high input impedance as the gate is insulated, has a rapid response ability,good thermal stability, simple driving circuit, good ability to withstand high voltage, snubber-less operation,and controllability of switching behavior providing reliable short-circuit protection. The IGBT is a voltage-controlled device, which gives it the ability to turn ON/OFF very quickly.

A typical application of a three-phase inverter using six isolated gate drivers is shown in Figure 1. Notethat each phase uses a high-side and a low-side IGBT switch to apply positive and negative high-voltageDC pulses to the motor coils in an alternating mode.

The output voltage to the motor is controlled by pulse-width modulation (PWM). PWM is accomplished byturning the transistor on and off several times. The output voltage is an average of the peak or maximumvoltage and the amount of time the transistor is turned on or off.

Figure 1. 3-Phase Inverter With Isolated Gate Drive

The ISO5852S is a reinforced isolated IGBT gate driver from TI intended for use in applications such asmotor control, industrial inverters, switched-mode power supplies, and so on. In these applications,sophisticated PWM control signals are required to turn the power-devices on and off, which at the systemlevel eventually may determine, for example, the speed, position, and torque of the motor or the outputvoltage, frequency, and phase of the inverter. These control signals are usually the outputs of amicrocontroller (MCU), and are at low-voltage levels such as 3.3 or 5.0 V. The gate controls required bythe IGBTs, on the other hand, are in the range of 15 to 20 V, and need high current capability to be ableto drive the large capacitive loads offered by those power transistors. Also, the gate drive needs to beapplied with reference to the emitter of the IGBT and by inverter construction, the emitter node of topIGBT swings between 0 to the DC bus voltage, which is several hundreds of volts in magnitude. As theIGBT can float with respect to ground at the power stage, both the power supply and the gate circuitryshould be isolated from the inverter ground. This gives room to a limited number of gate-driverconfigurations:• Gate drivers with potential separation• Gate drivers without potential separation

2 Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System TIDUA15A–June 2015–Revised August 2015Submit Documentation Feedback


http://www.ti.com


www.ti.com Introduction to IGBT Gate Drivers

The ISO5852S belongs to a family of gate drivers with potential separation and can level shift theincoming 3.3-V and 5.0-V control signals from the microcontroller to the 15-V to 20-V drive required byIGBT while ensuring high-voltage isolation between the driver side and the MCU side.

This reference design consists of a 22-kW power stage with TI’s reinforced isolated gate driversISO5852S intended to drive AC induction motor used in various industrial applications. This referencedesign demonstrates the following functionality and performance of ISO5852S IGBT gate driver in the realsystem:• Unipolar and bipolar IGBT gate driver supply operation• Undervoltage shutdown• Interface with external BJT based current buffers• DESAT detection• Miller clamp• Soft turn OFF• Propagation delay• ESD and EFT immunity performance of IGBT gate driver at system level

IGBT power module has been chosen such that its footprint fits multiple devices so as to perform gatedriver validation on IGBTs from different manufacturers. The footprint supports:• Fuji Electric: 6MBL150VX-120-50, 6MBL100VX-120-50• Mitsubishi: CM150TX-24S1• Infineon: FS50R12KT4, FS200R12KT4R, FS100R17N3E4

The C2000 Piccolo LaunchPad evaluation kit, based on the F28027 MCU is been used to control theinverter.

The power stage includes protection against IGBT overcurrent, over temperature of power module, andDC bus sensing for protection against overvoltage.



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Key System Specifications www.ti.com

2 Key System Specifications

Table 1. Key System Specifications of Power Stage

PARAMETER SPECIFICATIONDC link input voltage 400 to 1100 V

Control voltage 24-V DCIGBT power module 1200 V/50 to 150 A

Maximum input DC current 50 A with 200 CFM AirflowRated power capacity 22 kW

Inverter switching frequency 16 kHz (Default); adjustable through softwareIsolation Reinforced (IEC61800-5)

Operating ambient temperature –25°C to 65°CInverter efficiency ≥ 97% (Theoretical) at rated load

Controller TMS320F28027Motor 3-phase 400-V Induction motor

Provision for resistive braking YesPower supply specification for MCU 3.3 V ±5%

Feedbacks DC bus voltage, IGBT temperatureProtections Short circuit, over temperature, DC bus under- or overvoltage

ESD (IEC61000-4-2) ±8-kV Contact dischargeEFT (IEC61000-4-4) ±4-kV on motor cables (shielded and unshielded)

PCB 370 × 240 mm / 4 Layer, 2Oz copper



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SMPS PWMs

+16 V

-8 V

DC bus sensing

NTC output

+24-V DC

+800-V DC

C20

00 L

aun

chP

AD

inte

rfac

e

Gate drive

signals

Reinforced isolated

IGBT gate driver ±

ISO5852S

IGBT power module

HALF BRIDGESMPS

+16 V

-8 V 3N�ACIM

www.ti.com System Description

3 System DescriptionThe system consists of• IGBT power module: hex bridge IGBTs to provide three phases output for variable-frequency drives to

control the speed of AC motors (up to 22 kW). The PCB footprint supports mounting of different currentrated modules from different manufactures

• ISO5852S reinforced isolated gate driver capable of sourcing a 2.5-A and 5-A sink current is used todrive the IGBTs. Half-bridge converter powered from 24-V with isolated 16-V/-8-V rails are used topower gate drivers. The half-bridge transformer has been designed to meet safety requirements asdescribed in IEC61800-5

• Isolated amplifiers for measuring DC link voltage• C2000 LaunchPad for controlling the inverter. This design uses F28027 InstaSPIN™ FOC-enabled

MCU. The sinusoidal voltage waveform applied to the motor is created by using the Space Vectormodulation technique implemented in the F28027 MCU

• Buck converters for powering control electronics, operated from a 24-V supply and generates multiplevoltage rails like 15 V and 5 V. An LDO is used to generate 3.3 V from a 5-V supply for powering theC2000 LaunchPad

• Local DC link capacitor of ~220 μF. Relay is used to bypass NTC after power up• Discrete brake IGBT for braking during regeneration• Provision to measure the power module temperature using NTC• Provision for operating the FAN

PCB is designed to fulfill the requirements of IEC61800-5. Figure 2 depicts the block diagram of thepower stage.

4 Block Diagram

Figure 2. Power Stage Block Diagram



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Highlighted Products www.ti.com

5 Highlighted ProductsKey features of the highlighted devices can be taken from product datasheets. The following are thehighlighted products used in the reference design.

5.1 ISO5852SThe ISO5852S is a 5.7 kVRMS, reinforced isolated, IGBT gate driver with split outputs, OUTH and OUTL,providing 2.5-A source and 5-A sink currents. The primary side operates from a single 3-V or 5-V supply.The output side allows for a supply range from minimum 15 V to maximum 30 V. An internal DESATdetection recognizes when the IGBT is in an overload condition. Upon a DESAT detect, a Mute logicimmediately blocks the output of the isolator and initiates a soft-turn-off procedure, which disables OUTHand reduces the voltage at OUTL over a minimum time span of 2 μs. When OUTL reaches 2 V withrespect to the most negative supply potential, VEE2, the output is hard-clamped to VEE2.

During normal operation with bipolar output supply the output is hard clamp to VEE2 when the IGBT isturned OFF. If the output supply is unipolar, an active miller clamp connects the output to VEE2.

5.2 CSD88537The CSD88537 is a 60-V, dual N Channel, SO-8 NexFET™ power MOSFET with very low Drain-to-Source ON resistance of 12.5 mΩ. FET is capable of handling continuous current of 8 A. CSD88537 isdesigned to serve in half-bridge power supplies and motor control applications to generate gate driversupplies.

5.3 UCC27211The UCC27211 is a MOSFET driver delivering peak source and sink current of up to 4 A. The inputs areindependent of the supply voltage and have a maximum rating of 20 V. The floating high-side driver canoperate with supply voltages of up to 120 V. The high-side driver is referred to the switch node (HS),which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. Thelow-side driver is referenced to VSS, which is typically ground. Features of the UCC27211 include inputstages UVLO protection, level shift, and built-in boot diode.

5.4 Piccolo LaunchPadThe C2000 LaunchPad is based around the C2000 Piccolo TMS320F28027 MCU, which features a 60-MIPS processing core, 64-KB integrated flash, 8 PWM channels with high resolution capability, 12-bit 4.6-MSPS ADC, capture interface, serial connectivity, and more. It is used to generate the PWM signals forthe 3-phase inverter.

5.5 TPS54286The TPS54286 is a dual output non-synchronous buck converter capable of supporting 2-A outputapplications that operate from a 4.5-V to 28-V input supply voltage, and provides output voltages between0.8 V and 90% of the input voltage. The outputs can be enabled independently, or it can be configured toallow either ratio metric or sequential startup.

With an internally-determined operating frequency, soft start time, and control loop compensation, thisconverter provides many features with a minimum of external components. Other features include pulse-by-pulse overcurrent protection and thermal shutdown protection at 148ºC.



http://www.ti.com

http://www.ti.com/product/tms320f28027


www.ti.com Highlighted Products

5.6 AMC1200The AMC1200 is a precision isolation amplifier with an output separated from the input circuitry by asilicon dioxide (SiO2) barrier that is highly resistant to magnetic interference. This barrier has been certifiedto provide galvanic isolation of up to 4000 VPEAK according to UL1577 and IEC60747-5-2. The input of theAMC1200 is optimized for direct connection to shunt resistors with a voltage range of ±250 mV. Thedevice has low offset error of 1.5 mV max, BW of 60 KHz and CMMR of 108 dB. The AMC1200 has aworking voltage rating of 1200 VPEAK.

The MC1200 is fully specified over the extended industrial temperature range of –40°C to 105°C and areavailable in a wide-body SOIC-8 package (DWV) and a gullwing 8 package (DUB).

5.7 SN6501The SN6501 is a monolithic oscillator/power-driver, specifically designed for small form factor, isolatedpower supplies in isolated interface applications. The device drives a low-profile, center-tappedtransformer primary from a 3.3-V or 5-V DC power supply. The secondary can be wound to provide anyisolated voltage based on transformer turns ratio. The SN6501 consists of an oscillator followed by a gatedrive circuit that provides the complementary output signals to drive the ground referenced N channelpower switches. The internal logic ensures break-before-make action between the two switches. TheSN6501 is available in a small SOT-23 (5) package, and is specified for operation at temperatures from–40°C to 125°C.



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HE1aN-P-DC24V-Y5

5 6

1 4

RL1

470R

R104

10R

R103+24V

BYPASS_RELAY

DGND

DNP

C

B

E

Q5PZT2222A

SK310A-LTP

AC

D22

INRUSH_BYPASSPGND

10µFC131

PGND

1

CN1

Terminal bush

1

CN2

RHRG75120

A C

D1

B59109J0130A020t°

RT1

100R_PTC

680µF

C3

680µFC6

680µFC7

200KR208

200KR209

200KR210

200KR211

200KR212

200KR213 0.22µF

C154FILM CAP

System Design Theory www.ti.com

6 System Design Theory

6.1 Main Power InputThe main power input section is shown in Figure 3. D1 is the reverse polarity protection diode and hasreverse breakdown voltage of 1600 V. The input bulk aluminum electrolytic capacitors C3, C6, and C7serve as local reservoirs for the IGBT module. These capacitors are rated to carry ripple current of 7.7 A.The rest of ripple current is expected to be sourced from external capacitors. In addition to the bulkaluminum capacitor, a polyester capacitor is used across the DC bus to suppress high frequency noises.

The startup current through the bulk capacitor is limited using thermistor, and the thermistor is bypassedafter one second using a relay.

Figure 3. Main Power Input



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GATE_R_TOP

GATE_R_BOTTOM

GATE_Y_TOP

GATE_Y_BOTTOM

GATE_R_TOP_RTN

GATE_R_BOT_RTN

GATE_Y_BOT_RTN

GATE_Y_TOP_RTN

NTC_1

GATE_B_TOP

GATE_B_BOTTOM

GATE_B_TOP_RTN

GATE_B_BOT_RTN

IGBT Module

DC_VOLT_POS130

DC_VOLT_POS231

DC_VOLT_POS332

DC_VOLT_NEG133

DC_VOLT_NEG234

DC_VOLT_NEG335

GATE_R_TOP1

GATE_R_BOTTOM3

GATE_Y_TOP5

GATE_Y_BOTTOM7

GATE_R_TOP_RTN2

GATE_R_BOT_RTN4

GATE_Y_BOT_RTN8

GATE_Y_TOP_RTN6

MOT_Y_PHASE124

MOT_Y_PHASE225

MOT_Y_PHASE326

NTC_220

NTC_119

MOT_B_PHASE323

MOT_B_PHASE222

MOT_B_PHASE121

GATE_B_BOT_RTN12

GATE_B_TOP_RTN10

GATE_B_BOTTOM11

GATE_B_TOP9

DC_VOLT_NEG615

DC_VOLT_NEG514

DC_VOLT_NEG413

DC_VOLT_POS618

DC_VOLT_POS517

DC_VOLT_POS416

MOT_R_PHASE329

MOT_R_PHASE228

MOT_R_PHASE127

FS200R12KT4R

U1

IC_FS200R12KT4R

DGND

NTC_2

APT70GR120L

C

G

E

Q1GATE_BRAKE

DC_POS

BRAKE

1

CN11

Terminal bush

1

CN12

RHRG75120

AC

D2

MOTOR_B_PHASE

MOTOR_R_PHASE

MOTOR_Y_PHASE

0.22 µF

C154FILM CAP

www.ti.com System Design Theory

6.2 Inverter StageThe IGBT-based 3-phase hex bridge inverter is shown in Figure 4. The decoupling capacitor (C154)should be placed near to DC bus entry of inverter for better filtering. An improper layout or position of thedecoupling capacitors can cause undesired switching voltage spikes. IGBT (Q1) and free-wheeling diode(D2) is added externally to the hex bridge IGBT module for braking.

The brake IGBT (APT70GR120L) is rated for 70 A (at TC = 110°C) current rating and 1200 V.

When DC bus voltage increases above the pre-defined value (this reference design uses a 1-kVthreshold) brake operation is enabled through controller and the excessive energy will be dissipatedthrough the resistive bank. The resistor bank is connected across the terminal blocks CN11 and CN12.The rating of external brake resistor is selected on the basis of the VFD rating, braking duty cycle, andmagnitude of the energy to be dissipated.

Figure 4. 3-Phase Inverter of Power Stage



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out

LL

motor LL

PI

V 3 cos=

h ´ ´ ´ Æ


6.2.1 IGBT moduleThis reference design is intended to support various makes of IGBT modules like Infineon, Fuji &Mitsubishi, and so on. The power stage is designed to deliver up to 22-kW power. The power stage wassupplied with 800-V DC replicating high DC bus voltage during regeneration. Considering the safety factorand switching spikes, IGBTs were selected with the voltage rating greater than or equal to 1200 V. Thecurrent rating of the IGBT depends on the peak winding current.

The 3-phase inverter bridge is switched such that the sinusoidal current is injected into the motorwindings.• Motor rating = 22 kW• Line-to-line voltage = 415-V AC• Power factor considered = 0.8• Motor efficiency = 85%

(1)

Current through the winding = 47 ATherefore, the peak value of the winding current = √2 × IRMS = 66 A. (2)

Considering an overloading of 200%, the peak winding current would be 132 A.

The IGBT module used in this reference design (CM150TX-24S1) has continuous collector currentcarrying capacity of 150 A at TC = 100°C and peak current capacity of 300 A.

The selection of IGBT module with inbuilt NTC Thermistor is preferred to avoid thermal breakdown of theIGBT. This IGBT temperature rise information is routed to the MCU to take necessary action.

IGBTs can be driven into saturation to provide a very low voltage drop between the emitter and collector.



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AMC1200SDUBR

VOUTP7

VDD28

VOUTN6

VINN3

GND14

VDD11

GND25

VINP2

U14

10pFC87

10pFC86

0.1µF C84

+5V_ISO

GND_ISO

0.1µF

C83

0RR84

0RR86

DC_BUS_SENSE_POS

DC_BUS_SENSE_NEG0.01µF

C85

10KR88

1KR85

1M

R76

1M

R77

1M

R78

1M

R79

1MR80

1MR81

DGND

DGND

GND_ISOGND_ISO

10 Ohm

R83

10 Ohm

R87

3V34.7µFC166

DC_POS

DC

D

IN

CIN

1KV V

6 M 11K

V 0.00017 V

æ ö= ´ç ÷

+è ø

= ´

85

IN DC

IN

RV V

R

æ ö= ´ç ÷

ç ÷è ø


6.3 DC Link Voltage Sense CircuitThe DC bus input voltage to the inverter module is scaled down and fed to the MCU using the AMC1200isolation amplifier, which has a gain of 8. The differential output of the AMC1200 can directly drive ananalog-to-digital converter (ADC) input or can be further filtered before being processed by the ADC.

The resistor divider network is chosen considering the maximum voltage for the MCU ADC input as 3.3 Vand the maximum DC link voltage to be measured as 1200 V.

To achieve better linearity and the noise performance of the device, the allowable input voltage betweenthe amplifier pin VINP and VINN is ±250 mV. The voltage divider resistor is selected such that input voltageto the amplifier is less than ±250 mV at maximum DC bus condition.

Resistors R76 to R81 (see Figure 5) are selected as 1-M high-voltage resistors and R85 = 1K and R88 =10K. The differential output of the AMC1200 is directly routed to ADC of MCU.

AMC Output = AMC Gain × VIN

(3)

For 400-V DC inputVIN = 0.00017 × 400 ≈ 0.0665 V and VOUT = 8 × 0.0665 V ≈ 0.532 V.

For 1200-V DCVIN = 0.00017 × 1200 ≈ 0.2 VVOUT = 8 × 0.2 V ≈ 1.6 V

A decoupling capacitor of 4.7 μF and 0.1 μF is used for filtering the power-supply path of the AMC1200. Acapacitor (C166 and C84 in Figure 5) should be placed as close as possible to the VDD1 pin for bestperformance.

Figure 5. DC Voltage Sensing Module



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0.1µFC31

0.1µFC28

0RR34

ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U7

0.1µF

C33

1 2

QPC02SXGN-RCJ3

12

QPC02SXGN-RCJ1

10nFC38

RST1

RDY1

FLT1

12QPC02SXGN-RC

J2

3V3

DGND

200pFC40

100pFC39

12

QPC02SXGN-RCJ4

1

TP1

PWM_DRV_R_TOP

VEE_R

+15V R

-8V R

GATE_R_TOP

DC_POS

GATE_R_TOP_GND

GATE_R_TOP_RTN

1k

R39

GATE_R_TOP_GND

12QPC02SXGN-RC

J16

MM

3Z

12

VB

AC

D24

IN+_R_TOP

IN-_R_TOP

IN+_R_TOP

IN-_R_TOP

DGND

3V3

1

1

2

2

NOTE :1. Non-inverting Configuration2. Inverting Configuration

DNP

NOTE:To disable DESATDNP DESAT CapcitorPopulate Jumper

NOTE:Unipolar supply- Populate J1 onlyBipolar supply- Populate J2 only

GL41Y-E3/96

A C

D4

GL41Y-E3/96

A C

D23

1

TP44

1

TP17

4.7µF

C29

220RR35

220RR38

10uF

C25

10uF

C35

DNP

10R R219

1µF

C173

1µF

C174

0RR48

0RR49

0R

R233

DNP

DNP3

0RR60

0R

R61

0R

R62

0RR63

0RR37

RB

16

0M

-60

TR

AC

D69

GATE_R_TOP_GND

1µFC172


6.4 ISO5852S: Isolated IGBT Gate DriverThe ISO5852S is a 5.7-kVRMS, reinforced, isolated IGBT gate driver with split outputs OUTH and OUTLcapable of providing a 2.5-A source and 5-A sink currents. The primary side operates from a single 3.3-Vor 5-V supply. The output side allows for a supply range from minimum of 15 V to maximum 35 V. TheISO5852S has both inverting and non-inverting gate control inputs, an active low reset input, and an opendrain fault output suitable for wired-OR applications.

Figure 6 shows the one section of the gate driver schematic. This IC can be powered with either aunipolar or bipolar supply. If the IC is powered by unipolar supply, the VEE2 PIN should be connected toGND2. The supply bypass capacitors provide the large transient currents necessary during a switchingtransition.

The ISO5852S has the following features:• 5.7-kVRMS reinforced isolation voltage• 1.5-kVRMS working voltage• 12-kV surge rating• Split outputs providing 2.5-A peak source and 5-A peak sink currents• Short propagation delay: 76 ns typical• Active miller and short-circuit clamp• Soft turn-off during short circuit• FAULT alarm and RESET• Input and output supply UVLO with ready (RDY) output• CMOS compatible inputs

Figure 6. ISO5852S Application Schematic



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ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U26

PWM_DRV_B_BOT

DGND

3V3

IN+_B_BOT

IN-_B_BOT

1

1

2

2DNP

DNP

0RR167

0R

R168

0R

R169

0RR170

0.1µFC157

0.1µFC155

ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U26

0.1µFC159

12

QPC02SXGN-RCJ37

12

QPC02SXGN-RCJ38

3V3

DGNDVEE_B_BOT

RDY6

FLT6

RST6

IN+_B_BOT

IN-_B_BOT

4.7µFC156

10uFC98

10uFC101

DNP

10R R217

1µFC188

1µFC189

GATE_B_BOT_GND

+15V B_BOT

-8V B_BOT

1µFC187


6.4.1 Power SupplyVCC1 and GND1 are the supply pins for the input side of the ISO5852S. The supply voltage at VCC1 canrange from 3 to 5.5 V with respect to GND1, thus supporting the direct interface to 3.3 V low-powercontrollers as well as legacy 5 V controllers.

VCC2 and GND2 are the supply pins for the output side of the ISO5852S. VEE2 is the supply return forthe output driver and GND2 is the reference for the logic circuitry. The supply voltage at VCC2 can rangefrom 15 V up to 30 V with respect to VEE2.

A positive VGE of typically 15 V is required to switch the IGBT well into saturation. In this design, VCC2 isfed with 16 V to ensure that IGBT is in full saturation.

For low power IGBTs, miller clamp functionality of the gate driver enables it to be operated with unipolarvoltage (VEE2 connected to GND2). For larger IGBTs, negative values of VGE, ranging from a requiredminimum of –5 V up to the recommended –15 V, are necessary to keep the IGBT turned off and toprevent it from unintentional conducting due to noise transients, particularly during short circuit faults. Theboard has provision for connecting VEE2 to either 0 V or –8 V through jumpers.

Figure 7. ISO5852S Supply Voltages

6.4.2 Control Signal InputsThe two digital control inputs, IN+ and IN–, allow for inverting and non-inverting control of the gate driveroutput. In the non-inverting configuration, IN+ receives the control input signal and VIN– is connected toGND1. In the inverting configuration, VIN– is the control input while VIN+ is connected to VCC1.

Figure 8. ISO5852 Non-Inverting and Inverting Input Configurations



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ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U7

220R

220R

GATE

RG(ON)

RG(OFF)


6.4.3 Gate ResistanceThe gate current and the appropriate power of the voltage supply depend on the operating frequency, biascontrol voltages, and total gate charge. The total gate charge is published in IGBT datasheets, dependingon gate-control voltage. The gate charge necessary for switching is very important to establish theswitching performance of a MOSFET or IGBT. The lower the charge, the lower is the gate-drive currentneeded for a given switching time. The gate current can be controlled using external gate resistor betweendriver output and gate of IGBT. The value of the gate resistor determines the peak charge and dischargecurrents.

The ISO5852S device features a split-output configuration where the gate drive current is sourced throughthe OUTH pin and sunk through the OUTL pin. This pin arrangement provides flexibility to applyindependent turn-on and turn-off resistors to the OUTH and OUTL pins respectively and easily control theswitching slew rates. The value of the gate resistor influences different aspects of the switching processlike:• IGBT switching losses• Control di/dt• Cross conduction• Reverse recovery losses of the diode

The value of gate resistor is system dependent and usually chosen a value to provide optimumperformance. Strong sink capability (5 A) in an asymmetrical drive also boosts immunity against parasiticMiller turn-on effect.

Figure 9. Gate Drive Split Outputs



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MJD3055T4

3

1

2

MJD2955T4

2

1

3

VEE_R_BOT

+15V R_BOT

GATE

OUTH

OUTL

220R

220R

10RSK310A-LTP

AC

0R

MJD3055T4

3

1

2MJD2955T4

2

1

3

VEE_R_BOT

+15V R_BOT

GATE

OUTH

OUTL

220R

220R

2.2R

2.2R

10R

SK310A-LTP

AC

MJD3055T4

3

1

2

MJD2955T4

2

1

3

2.2R

2.2R

VEE_R_BOT

+15V R_BOT

0R

GATE

OUTH

OUTL

220R

220R


6.4.4 Optional External Current BufferWhen driving larger IGBTs requiring gate currents more than 5 A, an external current boost circuit can bebuilt with discrete NPN/PNP complimentary pair. One possible implementation is shown in Figure 10. Theselected BJT should be of fast switching and to have sufficient current gain to deliver the desired peakoutput current. The circuit, in Figure 10, with a MJD3055T4/MJD2955 pair can drive gate currents up to 10A.

Figure 10. Options in Using External Current Buffer

6.4.5 Undervoltage LockoutThe undervoltage lockout feature prevents the application of insufficient gate voltage (VGE-ON) to the powerdevice by forcing OUTH/OTL low during power-up and whenever supply voltage drops below 11 V. IGBTstypically require gate voltages of VGE = 15 V to achieve their rated, low saturation voltage, VCES. At gatevoltages below 13 V typically, their VCE-ON increases drastically, especially at higher collector currents. Ateven lower voltages, that is VGE < 10 V, an IGBT starts operating in the linear region and quicklyoverheats. The UVLO feature of ISO5852S avoids operating the IGBT in linear region by shutting it offduring insufficient gate supply voltage.

The UVLO feature has a hysteresis of 1 V typical and the typical values for the positive and negativegoing input threshold voltages are VTH+ = 12 V and VTH– = 11 V.

6.4.6 Desaturation Protection (DESAT)The DESAT fault detection prevents IGBT destruction due to excessive collector currents during a shortcircuit fault. Short circuits caused by bad wiring, or overload conditions induced by the load can cause arapid increase in IGBT current, leading to excessive power dissipation and heating. IGBTs becomedamaged when the current approaches the saturation current of the device and the collector-emittervoltage, VCE, rises above the saturation voltage level, VCE-sat. The drastically increased power dissipationoverheats and destroys the IGBT.

To prevent damage to IGBT, ISO5852S slowly turns OFF the IGBT in the event of fault detection. Slowturn OFF ensures the overcurrent is reduced in a controlled manner during the fault condition. The DESATfault detection involves a comparator that monitors the IGBT’s VCE and compares it to an internal 9-Vreference. If voltage across the IGBT reaches the threshold, DESAT detects immediately and blocks thegate driver output and initiates a soft-turn-off procedure that disables the OUTH, and reduces the voltageat OUTL over a minimum time span of 2 μs. The output is hard clamped to VEE2 when OUTL reaches 2 Vwith respect to VEE2.



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( )

b

b

9 V 100 pF t

500 A

t s 1.8

´=

m

m =

DESAT

b

9 V Ct

500 A

´=

m

ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U24

200pFC149

100pFC150

12

QPC02SXGN-RCJ33

1

TP6

DC_POS

GATE_B_TOP_GND

1k

R159

MM

3Z

12

VB

AC

D55

DNP

GL41Y-E3/96

A C

D53

GL41Y-E3/96

A C

D54

TP41

RB

16

0M

-60T

R

AC

D73


6.4.6.1 DESAT Pin ProtectionThe diodes (GL41Y in Figure 11) at the DESAT signal block the high voltage during the IGBT OFF stateand conduct forward current, which allows the sensing of the IGBT’s saturated collector-to-emitter voltage(VCESAT) when the IGBT is "ON". To avoid false DESAT triggering, fast switching diodes with lowcapacitance are recommended. Because the sum of the DESAT diode forward-voltage and the IGBTcollector-emitter voltage make up the voltage at the DESAT-pin, VF + VCE = VDESAT, the VCE level, whichtriggers a fault condition, can be modified by adding multiple DESAT diodes in series: VCE-FAULT (TH) = 9 V –n × VF (where n is the number of DESAT diodes). When using two diodes instead of one, diodes with halfthe required maximum reverse-voltage rating may be chosen. See Figure 11 where provision is providedto mount two DESAT diodes.

Switching inductive loads causes large instantaneous forward voltage transients across the freewheelingdiodes of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which drawsubstantial current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistorcan be connected in series with the DESAT diode. Further protection is possible through an optionalSchottky diode (MM3Z12VB), whose low forward voltage assures clamping of the DESAT input to GNDpotential at low voltage levels.

Figure 11. DESAT Detection

DESAT Blanking TimeThe DESAT fault detection must remain disabled for a short time period following the turn-on of the IGBTto allow its collector voltage to drop below the 9-V DESAT threshold. This time period, called the DESATblanking time, tBLK, is controlled by an internal charge current of ICHG = 500 μA, the 9-V DESAT threshold,VDSTH, and an external blanking capacitor, CBLK.

CDESAT = 100 pF (refer to C150 in Figure 11).

(4)

The capacitor value can be scaled slightly to adjust the blanking time. However, because the blankingcapacitor and the DESAT diode capacitance build a voltage divider that attenuates large voltage transientsat DESAT, CBLK values smaller than 100 pF are not recommended.

If VCE exceeds this reference voltage (9 V) after the blanking time, the comparator inside ISO5852Scauses the gate drive and fault logic to initiate a fault shutdown sequence. This sequence starts with theimmediate generation of a fault signal, which is transmitted across the isolation barrier towards the faultindicator circuit at the input side of the ISO5852S.

This board also provides feature of disabling the DESAT during testing by connecting the jumper at theDESAT pin.



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6.4.7 Active Miller ClampDuring turn-on or turn-off of IGBTs, displacement current flows through the miller capacitor (gate tocollector capacitor) of the IGBT, raising its gate voltage. It could lead to unintentional turn-on of the IGBT.When the high-side IGBT turns on within an inverter leg, the voltage across the low-side IGBT increaseswith a high dv/dt. The ratio of reverse transfer capacitance to the input capacitance is larger for IGBTs(CRES/CIES). This produces an increased Miller effect and a larger noise is coupled from the collector to thegate.

This induces a current in the gate of the lower IGBT that may produce turn-on of the low-side deviceshorting the DC bus.

However, certain low-power IGBTs have a lesser CRES (reverse transfer capacitance) and do not neednegative gate voltage for turn-off. Instead, the clamp functionality of the ISO5852S can be used to ensurethat gate is pulled to emitter thorough a low-impedance path, preventing a false turn-on.

The CLAMP transistor is turned on when OUTL reaches 2 V with regard to VEE2 during turn-off of theIGBT. The CLAMP transistor hard clamps the OUTL pin to VEE2. The clamp transistor remains on once itis ON even if OUTL goes above 2 V. The CLAMP transistor is again turned off during IGBT turn-onprocess.

If the supply is unipolar, an active Miller clamp connects the output to VEE2 (Ground), and this condition islatched. During a bipolar supply operation, the output is hard clamped to VEE2 (-8 V) when the IGBT isturned off.

For larger IGBTs, a still negative gate voltage is required. Another reason for the negative gate voltage atIGBTs is of the operation at higher voltages with increased (dv/dt) coupling of noise.

6.4.8 Fault and Protection HandlingThe FAULT pin indicates an error event (with soft shutdown) has occurred such as IGBT short circuit.Fault will be latched until the reset is applied. FAULT will go high, when the logic low pulse is applied toRESET pin. This can be accomplished with an MCU, or an additional logic gate that synchronizes theRESET signal with the appropriate input signal.

The ready pin is high during the primary and secondary side supplies are good. It is pulled LOW when thesupply voltage is less than the UVLO limits.

6.4.9 External Gate Emitter Capacitor to Shunt Miller CurrentAn option to mount external capacitor between IGBT gate and emitter has been provided to evaluate theeffectiveness of clamp functionality.

This capacitor can sink the additional charge originating from the Miller capacitance during the turn-on oftop IGBT. Due to the additional capacitance, the effective input capacitance of the IGBT is CG||CGE, thegate charge required to reach the threshold voltage will be increased.



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( ) ( )2gate dc gate sw gate ge sw gateP P Q F V C F V= + ´ ´ D + ´ ´ D

Rg

Cge (Ext)-8 V

-16 V

PWM

VDC+

VDC-


6.4.10 Power DissipationIn the process of turning the IGBT ON and OFF, power is dissipated by the driver IC, IGBT gate, and byany RC circuits in the gate drive path.

Figure 12. Driver Power Loss

The total gate power dissipation is calculated with Equation 5:

where• Qgate = total gate charge• Fsw = Switching frequency• ΔVgate = Gate driver output voltage swing (5)

For CM150TX-24S1, Qg is approximated as 450 nC for bipolar switching and 300 nC for unipolarswitching with Vge = 15 V.

• FSW = 16 KHz• ΔVgate = 15 V and 23 V• Cge = 10 nF

The static power dissipation of ISO5852S is PDC = IQ × VDD where IQ is the quiescent current for thedriver. The quiescent current is the current consumed by the device to bias all internal circuits such asinput stage, reference voltage, logic circuits, protections, and so on, and also any current associated withswitching of internal devices when the driver output changes state. The ISO5852S features very lowquiescent currents — 6 mA when supplied with 15 V and –8 V.

Power dissipation for bipolar switching: Pgate = 0.138 + 0.1656 + 0.085 = 0.4 W

Power dissipation for unipolar switching: Pgate = 0.2 W



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HSG

LSG

0RR89

0R

R92

Half Bridge converter : SMPS

+15V

DGND

DGND DGND

LI_PWM

HI_PWM

0RR125

+24V

HS

HS

DGND DGND

SK310A-LTP

AC

D44

SK310A-LTP

AC

D43

SK310A-LTP

A C

D42

CSD88537ND

7

2

1

5

4

3

6

8U15

17.8 ohmR90

17.8 ohmR91

10µFC47

0RR232

UCC27211DPRT

VD

D1

LI8

LO10

VS

S9

HO3

HS4

HB2

NC5

NC6

HI7

U16

0.1µF

C1100RR124

0.33 µFC49

0.1µFC109

0.1µFC113

0.1µFC126

0.1µFC147

+15V R_BOT

-8V R_BOT

GATE_R_BOT_GND

LS1

750313734

3

5

8

913

14

T2

Transformer_SMPS

10µFC10810µFC105

10µFC11610µFC114

10µFC143

10µFC112

47uFC106

47uFC111

47uFC115

47uFC136

+15V R

-8V R

GATE_R_TOP_GND

3.3uFC88

3.3uFC97

RB160M-60TR

AC

D68

RB160M-60TR

AC

D76

RB160M-60TR

AC

D77

RB160M-60TR

AC

D78

RB160M-60TR

AC

D79

RB160M-60TR

AC

D80


6.5 Half-Bridge SMPS for Gate DriverA half-bridge SMPS is used to generate isolated positive (16 V) and negative (–8 V) voltage rails requiredby IGBT gate drivers from a single 24-V DC input supply. The half-bridge driver is operated in open loopmode with 500 kHz / 50% duty cycle generated by the Piccolo controller.

This half-bridge topology allows for more efficient use of the transformer core than the flyback or forwardconverters. The transformer has two secondaries, each generating 8.7 V (required output = 8 V with adiode drop of 0.7 V). A voltage doubler has been used to generate 16 V from the secondary generated 8V. Each transformer is used to power TOP and BOTTOM IGBTs of each phase.

Figure 13. Isolated Power Supply

During the turn-on and turn-off of IGBT, gate driver requires instant peak current from its power supply fora short period of time, so it is important to use proper by-pass capacitors for the power supply. To achievethe minimum output ripple with high-current load transients, a 47-μF capacitor at each of the output on thesecondary side is used.



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6.5.1 Transformer Specification• Two isolated outputs with VOUT1 = 8.7 V at 250 mA and VOUT2 = 8.7 V at 250 mA• Switching frequency = 500 kHz• Primary to secondary isolation = 7.4 kV for 1.2/50-µs impulse voltage• Type test voltage:

– Primary to Secondary = 3.6 kVRMS

– Secondary1 to Secondary2 = 1.8 kVRMS

• Spacing:– Primary to Secondary clearance = 8 mm– Secondary1 to Secondary2 clearance = 5.5 mm– Creepage distance = 9.2 mm

• Functional Isolation Primary and secondary : 1.5-kV DC• DC isolation between secondaries: 1.5-kV DC

Figure 14. Half-Bridge Transformer Symbol



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+24V

GND GND

+24V

GND

3.3R

R93

51.1KR97

+15V

+15V

GND

3.3R

R94

0RR95

0RR99

GND

GND

+5V

20KR100

GND

+5V

1nFC121

1nFC122

100uH 0.5AL1

47uH 1.5AL2

GND

2.87KR101

TPS54286PWP

PVDD11

BOOT12

SW13

FB28

EN15

GND4

BP11

BOOT213

EN26

FB17

SEQ10

ILIM29

SW212

PVDD214

PW

PD

15

U17

DNP

DNP

10RR98

10RR96

3.83KR102

10µF

C117

10µF

C118

0.033µF

C119

0.033µF

C120

4.7µFC123

4.7µF

C127

4.7µFC125

4.7µF

C128

10µFC124

SK310A-LTP

AC

D20

SK

310

A-L

TP

AC

D21

GND

0.01µFC30

0.01µFC32

DNP

DNP


6.6 Design of 24-V to 15-V and 5-V Step-Down DC-DC ConverterThe 15-V regulated power supply for the half-bridge driver and 5 V are derived using the TPS54286switching converter. The TPS54286 device is a dual step-down (buck) regulator with an integrated high-side and low-side n-channel MOSFET. This operates in constant switching frequency, current modecontrol which reduces output capacitance, and also reduces the complexity of compensation design. Thedesign specifications of the step-down converter are given Table 2. The schematic of the step-downconverter is shown in Figure 15.

Table 2. Design Specifications of Step-Down Converter

PARAMETER SPECIFICATIONOutput voltage 15 V and 5 V

Maximum output current 150 mA and 500 mAInput voltage 24 V pre-regulated

Output voltage ripple 0.5% of VOUT

Figure 15. 24-V to 15-V and 5-V Step-Down Converter



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( ) ( ) ( )

RIPPLE 3

2 2

L rms

24 V 5 V 1I 0.230 0.154 A 0.15 A

47 H 600 10

1I 0.5 0.15 0.501 A

12

-» ´ ´ = »

m ´

= + =

( ) ( ) ( )2 2

L rms

1I 0.2 0.1 0.202 A

12= + =

( ) ( )( ) ( )2 2

RIPPLEL rms L avg

1I I I

12= +

RIPPLE 3

24 V 15 V 1I 0.635 0.095 A 0.1 A

100 H 600 1 0

-» ´ ´ = »

m ´

( ) OUTIN max

RIPPLE min

SW

V V 1I D

L f

-» ´ ´

min

min 3

15 V 0.7 VD 0.635

24 V 0.7 V

24 V 15 V 1L 0.635 95.25 H 100 H

0.1 600 10

+» »

+

-» ´ ´ = m » m

´

min 3

24 5 1L 0.23 48.71 H 47 H

0.15 600 10

-» ´ ´ = m » m

´

( )

( )

OUTIN max

min min

SWLRIP max

V V 1L D

I f

-» ´ ´

min

15 V 0.7 VD 0.23

24 V 0.7 V

+» »

+

( )

OUT FD

min

FDIN max

V VD

V V

+»

+


6.6.1 Circuit Design

6.6.1.1 Output Inductor Selection (LO)To calculate the minimum value of the output inductor,

For 5-V output

(6)

(7)

For 15-V output

Ripple current for 15 V

(8)

(9)

Ripple current for 5 V



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30.8 20 10

R103 3.809 k5 0.8

´ ´= = W

-

FB

OUT1 FB

V R97R103

V V

´

=

-

30.8 51.1 10

R102 2.873 k15 V 0.8

´ ´= = W

-

FB

OUT1 FB

V R97R102

V V

´

=

-

( )OUT 2

2 3

1C 14.97 F

4 6 10 47 H

= = m

´ p ´ ´ ´ m

( )OUT 2

2 3

1C 7.04 F

4 6 10 1 00 H

= = m

´ p ´ ´ ´ m

( )OUT 2

2

RES

1C

4 f L

=

´ p ´ ´


6.6.1.2 Output CapacitorThe internal compensation of the TPS54286 limits the selection of the output capacitors. Internalcompensation has a double zero resonance at about 6 kHz, so the output capacitor is selected byEquation 10.

For 15 V

(10)

For 5 V

6.6.1.3 Output Voltage RegulationFor this design feedback divider resistors (R97, R100) are 20K and 51.1K. The lower resistor R102 andR103 are found using the following equations.

(11)

(12)

6.6.1.4 Bootstrap circuitA 3.3-nF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. Usea ceramic capacitor with X5R or better grade dielectric. The capacitor should be rated 50 V or higher.

A small resistor with value between 1 and 3 Ω to be placed in series with the bootstrap capacitor; thisreduces the rising edge ringing at the SW node.

6.6.1.5 SnubberFast switching and parasitic inductance and capacitance results in a voltage ringing at the SW node. If theringing results in excessive voltage on the SW node or erratic operation of the converter, an R-C snubber(C = between 330 pF and 1 nF, R = 10 Ω) may be used to dampen the ringing at the SW node to ensureproper operation over the full load range.



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F max DO max O max

min

IN min DS max D max

V V Vn 1.031

V R I

- - -

- - -

+

= ´

- ´

+

min

5.5 VVt 9.1 V s

2 300 kHz³ = m

´

IN maxmaxmin IN max

min

VTVt V

2 2 f

-

-³ ´ =

´

SN6501DBVR

D11

VCC2

D23

GND4

GND5

U19

DGND

MBR0520LT3G

A C

D40

MBR0520LT3G

A C

D410.1µFC43

+5V_ISO

+5V

GND_ISO

0.1µF

C37

+5V

DGND

MM3Z5V1BAC

D63

47 OhmR200

Wurth Elektronik750313734

1

2

34

5

6T1

10uFC36

10µFC41

10µFC44

DNP


6.7 Design of 5-V isolated DC-DC ConverterThe AMC1200 requires isolated power supply for powering its input section. The SN6501 is used as aswitching device to generate a 5-V isolated output.

Table 3. Specifications for Selection of 5-V DC-DC Converter

PARAMETER SPECIFICATIONOutput voltage 5 V

Output current required 10 mAInput voltage 5 V

Output voltage ripple 0.5% of VOUT

The SN6501 is a monolithic oscillator and power-driver, specifically designed for isolated power suppliesin isolated interface applications with small form factor. It drives a low-profile, center-tapped transformerprimary from a 3.3-V or 5-V DC power supply. The SN6501 consists of an oscillator followed by a gatedrive circuit that provides the complementary output signals to drive the ground referenced N-channelpower switches. The internal logic ensures break-before-make action between the two switches.

Features:• Push-pull driver for small transformers• Single 3.3-V or 5-V supply

Figure 16. Isolated 5-V Converter

Transformer SelectionTo prevent a transformer from saturation its V-t product must be greater than the maximum V-t productapplied by the SN6501. The maximum voltage delivered by the SN6501 is the nominal converter inputplus 10%. The maximum time voltage is applied to the primary is half the period of the lowest frequency atthe specified input voltage. Therefore, the transformer’s minimum V-t product is determined usingEquation 13.

(13)

Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typicalfootprints of 10 × 12 mm. Other important factors to be considered in transformer selection are isolationvoltage, transformer wattage, and turns ratio.

Transformer Turns Ratio Estimation

(14)



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Table 4. Transformer Specifications

PARAMETERS TEST CONDITIONS VALUEDC resistance 1-3 @ 20°C 0.419 Ω maxDC resistance 6-4 @ 20°C 0.335 Ω max

Inductance 1-3 100 kHz,10-mV AC, LS 340 µH min.Dielectric 1-6 6250 VRMS, 1 second 5000 VRMS, 1 minuteTurns ratio (6-4): (1-3) 1.1:1, +-2%

Figure 17. Isolated Transformer Construction

6.8 5-V To 3.3-V Regulator

Table 5. Specification of 3.3-V Output LDO

PARAMETER SPECIFICATIONSInput voltage 5 V

Output 3.3 mAOutput current 350 mA

The LP38691 is selected is based on specifications outlined in Table 5. The LP3869x is a low-dropoutCMOS linear regulator providing tight output tolerance (2% typical), extremely low-dropout voltage (250mV at 500-mA load current VOUT = 5 V), and excellent AC performance using ultra-low equivalent seriesresistance (ESR) ceramic output capacitors.

Figure 18. 3.3-V Circuit



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6.9 Status IndicationsThe ISO5852S fault and ready indications are shorted and connected to two LED indications as shown inFigure 19.

Figure 19. Status Indication Through LED



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6.10 LaunchPad ConnectionsThe C2000 InstaSPIN™ Piccolo LaunchPad is used for controlling the inverter.

The LaunchPad has following connections to the power stage:• Thermistor feedback from the IGBT module• DC bus voltage feedback• FAULT ready• PWM enable and RESET signals from the ISO5852S• Relay_Enable signal• Fan drive signals• PWM signals for half-bridge SMPS• PWM signals for gate driver

PWM_EN is used to control the buffer providing PWM signals to ISO5852S.

Figure 20. LaunchPad Connections for C2000 Piccolo LaunchPad



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System Test Results www.ti.com

7 System Test Results

7.1 Power Supply

7.1.1 3.3-V LDO Output (U18)

Figure 21. Output Voltage of 3.3-V LDO With Load of 100 Figure 22. Ripples in 3.3-V LDO Output With Load of 100mA mA

7.1.2 Buck Converter Outputs TPS54286PWP (U17)

7.1.2.1 15-V Output

Figure 23. 15-V Supply With Load of 15 mA Figure 24. Ripples in 15-V Supply With Load of 15 mA



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www.ti.com System Test Results

7.1.2.2 5-V Output

Figure 25. 5-V Supply With Load of 150 mA Figure 26. Ripples on 5 V With Load of 150 mA

7.1.3 Isolated 5-V Output SN6501DBVR (U19)

Figure 27. 5-V Isolated Supply Output With Load of 7 mA Figure 28. Ripple on 5-V Isolated Supply Output WithLoad of 7 mA



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7.1.4 Half-Bridge Gate Driver supply

7.1.4.1 16-V Output From Half-Bridge SMPS

Figure 29. 16 V during power ON Figure 30. Ripples on 16 V at 2.5-A Source Current and4.5-A Sink current

Figure 31. Ripples on 16 V at 2.5-A Source Current Figure 32. Ripples on 16 V at 4.5-A Sink Current



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7.1.4.2 –8-V Output From Half-Bridge SMPS

Figure 33. –8 V During Power ON Figure 34. Ripple on –8 V

Figure 35. Ripple on –8 V at 2.5-A Source Current Figure 36. Ripple on –8 V at 4.5-A Sink Current



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7.2 Power ON Test Without External BJT/MOSFET BufferThe undervoltage lockout feature monitors the secondary voltage rail and prevents the IGBT operatingwith insufficient gate voltage (VGE-ON) by forcing OUTH/OUTL to low (during power-up else VCC2 dropsbelow 12 V). In Figure 37 and Figure 38, the gate driver output is held low (CH2) until VCC (CH3)exceeds 12 V. CH1 represents the PWM input of ISO5852S.

Figure 37. Gate Driver Output During Power ON With Figure 38. Gate Driver Output (Zoomed)Unipolar Supply

NOTE: CH1: PWM from controller, CH2: Gate driver output, CH3: 16-V supply

Figure 39. Gate Driver Output During Power ON With Figure 40. Gate Driver Output (Zoomed)Bipolar Supply

NOTE: CH1: –8-V supply, CH2: Gate driver output, CH3: 16-V supply



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7.3 Power ON Test With External BJT Buffer

Figure 41. External BJT Buffer Output During Power ON Figure 42. Gate Driver Output (Zoomed)With Unipolar Supply

NOTE: CH1: PWM from controller, CH2: Gate driver output, CH3: 16-V supply

Figure 43. Gate Driver Output During Power ON With Figure 44. Gate Driver Output (Zoomed)Bipolar Supply

NOTE: CH1: –8-V supply, CH2: Gate driver output, CH3: 16-V supply



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7.4 2.5-A/5-A Sink and Source Current With Bipolar Supply Without BJT Buffer (InfineonModule)Figure 45 through Figure 47 show the sink and source currents delivered directly by ISO5852S.

Test conditions:• RG (ON): 7.5 Ω• RG (OFF): 0.0 Ω• IGBT module: Infineon FS200R12KT4R_B11• Gate charge (QG): 1.65 μC• Internal resistance: 3.5 Ω• Input capacitance Cies: 14 nF

Figure 45. Gate Driver Output — 2.5-A Source Current Figure 46. Gate Driver Output — 4.5-A Sink Current

Figure 47. Source and Sink Current

NOTE: CH2: Gate current, CH3: Gate driver output



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Controller PWM bufferISO5852S

IGBT gate driverPWM


7.5 PWM Signal DelaySection 7.5.1 and Section 7.5.2 show the propagation delay between the Piccolo controller and the gatedriver.

Figure 48. Piccolo Controller and Gate Driver Diagram

7.5.1 Delay Between PWM Buffer Input and PWM Buffer Output

Figure 49. Propagation Delay of PWM Buffer (R-Top) Figure 50. Propagation Delay of PWM Buffer (R-Top)(Rising Edge) (Falling Edge)

Figure 51. Propagation Delay of PWM Buffer (R-Bot) Figure 52. Propagation Delay of PWM Buffer (R-Bot)(Rising Edge) (Falling Edge)

NOTE: CH1: PWM from controller, CH2: PWM buffer output, CH3: Current buffer output



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Table 6. Delay Between PWM Signals

PWM BUFFER INPUT AND PWM BUFFER OUTPUT TIME (ns)R_Top (Rising) 5.0R_Top (Falling) 5.0

R_Bottom (Rising) 3.0R_Bottom (Falling) 4.0

7.5.2 Delay Between PWM Buffer Input and Gate Driver Output

Figure 53. Gate Driver Propagation Delay R_Top (Rising) Figure 54. Gate Driver Propagation Delay R_Top(Falling)

Figure 55. Gate Driver Propagation Delay R_Bottom Figure 56. Gate Driver Propagation Delay R_Bottom(Rising) (Falling)

NOTE: CH1: PWM from controller, CH2: PWM buffer output, CH3: Current buffer output

Table 7. Delay Between PWM Signals

PWM BUFFER INPUT AND GATE DRIVER OUTPUT TIME (ns)R_Top (Rising) 84.0R_Top (Falling) 80.0

R_Bottom (Rising) 82.0R_Bottom (Falling) 81.0



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7.6 Induced Voltage at Gate for dV/dt of 2.5 kV/μs With 10-m Motor Cable

7.6.1 Active Miller Clamp Disabled

Figure 57. 2.5-kV/μs Inverter dV/dt Figure 58. Induced Voltage at 2.5-kV/μs dV/dt

NOTE: 2.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active millerclamp disabled and Cge(Ext) = 0 nF

CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT


NOTE: 2.5-kV/μs inverter output and induced voltage at gate of bottom IGBT with active miller clampdisabled and Cge(Ext) = 10 nF


Table 8. Summary of Induced Voltage for 2.5-kV/μS dV/dt (Active Miller Clamp Disabled)

INDUCED VOLTAGE AT THE BOTTOM IGBTTEST CONDITIONS (POSITIVE PEAK IN VOLTS)Active Miller clamp disabled 3.4Cge(Ext)=0nFActive Miller clamp disabled 2Cge(Ext)=10nF



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7.6.2 Active Miller Clamp Enabled


NOTE: 2.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active millerclamp enabled and Cge(Ext) = 0 nF



NOTE: 2.5-kV/μs inverter output and induced voltage at gate of bottom IGBT with active miller clampenabled and Cge(Ext) = 10 nF


Table 9. Summary of Induced Voltage for 2.5-kV/µs dV/dt (Active Miller Clamp Enabled)

INDUCED VOLTAGE AT THE BOTTOM IGBTTEST CONDITIONS (POSITIVE PEAK IN VOLTS)Active Miller clamp enabled. 0.4Cge(Ext) = 0 nFActive Miller clamp enabled 0.4Cge(Ext) = 10 nF



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7.7 Induced Voltage at Gate for dV/dt of 5 kV/μs With 10-m Motor Cable


Figure 65. 5-kV/μs Inverter dV/dt Figure 66. Induced Voltage at 5-kV/μs dV/dt

NOTE: 5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active millerclamp disabled and Cge(Ext) = 0 nF



NOTE: 5-kv/µs inverter output and induced voltage at the gate of bottom IGBT with active millerclamp disabled and Cge(Ext) = 10 nF


Table 10. Summary of Induced Voltage for 5-kV/µs dV/dT (Active Miller Clamp Disabled)

INDUCED VOLTAGE AT THE BOTTOM IGBTTEST CONDITIONS (POSITIVE PEAK IN VOLTS)Active Miller clamp disabled 4Cge(Ext)=0nFActive Miller clamp disabled 2.8Cge(Ext)=10nF



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NOTE: 5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active millerclamp enabled and Cge(Ext) = 0 nF



NOTE: 5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active millerclamp enabled and Cge(Ext) = 10 nF


Table 11. Summary of Induced Voltage for 5-kV/μs dV/dt (Active Miller Clamp Enabled)

INDUCED VOLTAGE AT THE BOTTOM IGBTTEST CONDITIONS (POSITIVE PEAK IN VOLTS)Active Miller clamp enabled 0.44Cge(Ext) = 0 nFActive Miller clamp enabled 0.44Cge(Ext) = 10 nF



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7.8 Induced Voltage at Gate for dV/dt of 7.5 kV/μs With 10-m Motor Cable



NOTE: 7.5-kV/μs inverter output and induced voltage at the bottom IGBT - active miller clampdisabled and Cge(Ext) = 0 nF



NOTE: 7.5-kV/μs inverter output and induced voltage at the bottom IGBT with active miller clampdisabled and Cge(Ext) = 10 nF


Table 12. Summary of Induced Voltage for 7.5-kV/μs dV/dt (Active Miller Clamp Disabled)

INDUCED VOLTAGE AT THE BOTTOM IGBTTEST CONDITIONS (POSITIVE PEAK IN VOLTS)Active Miller clamp disabled 4Cge(Ext) = 0 nFActive Miller clamp disabled 3.2Cge(Ext) = 10 nF



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NOTE: 7.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active millerclamp enabled and Cge(Ext) = 0 nF



NOTE: 7.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT - active millerclamp enabled and Cge(Ext) = 10 nF


Table 13. Summary of Induced Voltage for 7.5-kV/μs dV/dt (Active Miller Clamp Enabled)

INDUCED VOLTAGE AT THE BOTTOM IGBTTEST CONDITIONS (POSITIVE PEAK IN VOLTS)Active Miller clamp enabled 0.72Cge(Ext) = 0 nFActive Miller clamp enabled 0.56Cge(Ext) = 10 nF



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7.9 Maximum Achievable dV/dt Without External BJT Buffer

Figure 81. Max dV/dt and Induced Voltage Without External Buffer With 10-m Motor Cable (Bipolar)

NOTE: CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT

Maximum dV/dt achieved without external BJT buffer: 8.47 kV/μs

Test conditions:• RG (ON): 2.2 Ω• RG (OFF): 2.2 Ω• IGBT module: CM150TX-24S1_MITSUBISHI• Gate charge (QG): 315 nC• Internal resistance: 13 Ω• Input capacitance CIES: 15 nF



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7.10 Current Through Clamp Pin

Figure 82. Current Through Clamp Pin

Test conditions:• External buffer: without BJT• Supply: Unipolar• RG (ON): 2.2 Ω• RG (OFF): 2.2 Ω• IGBT module: CM150TX-24S1_MITSUBISHI• Gate charge (QG): 315 nC• Internal resistance: 13 Ω• Input capacitance CIES: 15 nF



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Inverter module

Gate driver ISO58252

R1

R2

R3

R4

Out H

Out L

D1

IGBT gate

100 cm

cable

Probe point

I1

Discharge

Charge


7.11 Validation of Gate Signals With External Cable (Without BJT Buffer)

Figure 83. Gate signal at Gate of IGBT With 100-cm External Cable

NOTE: CH1: Gate driver output, CH3: Vce of bottom IGBT

Figure 84. Block Diagram for Measurement of Gate Signal With External Cable

7.12 DESAT Signal During Normal Operation

Figure 85. DESAT During Normal Operation (Zoomed) Figure 86. DESAT During Normal Operation

NOTE: CH1: Bottom gate driver output, CH2: DESAT signal, CH3: Vce of bottom IGBT



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SMPS PWMs

+16 V

-8 V

DC bus sensing

NTC output

+24-V DC

+800-V DC

C20

00 L

aun

chP

AD

inte

rfac

e

Gate drive

signals

Reinforced isolated

IGBT gate driver ±

ISO5852S

IGBT power module

HALF BRIDGESMPS

+16 V

-8 V

Short between inverter output

to DC (-ve)


7.13 Short Circuit Test — Hard Switched

NOTE: All the tests in Section 7.13 and Section 7.14 were performed using engineering samples ofISO5852S. The final silicon has a higher pulldown drive during soft shutdown whencompared to the engineering samples, resulting in lower soft shutdown time for given Qg ofthe IGBT die. Refer to the latest datasheet of ISO5852S on TI Website athttp://www.ti.com/product/ISO5852S

Figure 87 shows the block diagram of hard-switched fault setup.

Figure 87. Block Diagram of Short Circuit Setup (Hard Fault Switch)

A hard fault switch short circuit test was performed using the power module CM150TX-24S1_MITSUBISHI. This test is performed such that one arm of the inverter bottom IGBT already has ashort (from Figure 87, Y phase output is connected to DC negative), during the same turning ON the topIGBT (Y_Top) to know the performance of DESAT detection.

Test conditions:• Short circuit connection: Y-phase inverter output to DC negative• Motor connected: NO• Inverter dV/dT: 2.5 kV/μs, 5 kV/μs, 7.5 kV/μs• IGBT module: CM150TX-24S1_MITSUBISHI• Gate charge (QG): 315 nC• Internal resistance: 13 Ω• Input capacitance CIES: 15 nF



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7.13.1 Hard Switched Fault With Inverter dV/dt of 2.5kV/μs

Figure 88. DESAT Activation to Gate Driver Turn OFF Figure 89. DESAT Activation to Fault Indication

Figure 90. Gate Driver Output During Soft Shutdown

NOTE: CH1: Fault signal, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driver output

Figure 91. Voltage Across (Vce) Top IGBT Figure 92. IC — During Short circuit



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NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Vce of topIGBT

Table 14. Summary of Short Circuit Test of Hard Switched Fault with 2.5 kV/µs

PARAMETER VALUEDESAT activation to gate driver turn OFF 360.0 nsDESAT activation to Fault indication 1.16 µsSoft shutdown time 10.2 µsShort circuit current 1.04 kADip in Vce 220 V

7.13.2 Hard Switched Fault With Inverter dV/dt of 5 kV/μs


Figure 95. Gate Driver Output During Soft Shutdown




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Figure 96. Voltage Across (Vce) Top IGBT and IC– During Short Circuit


Table 15. Summary of Short Circuit Test of Hard Switched Fault with 5 kV/µs

PARAMETER VALUEDESAT activation time to gate driver turn OFF 360 nsDESAT activation to fault output 800 nsSoft shutdown time 10.5 µsShort circuit current 1.05 kADip in Vce 240 V



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7.13.3 Hard Switched Fault With Inverter dV/dt of 7.5 kV/μs



Figure 99. Voltage Across (Vce) Top IGBT Figure 100. IC– During Short Circuit


Table 16. Summary of Short Circuit Test of Hard Switched Fault with 7.5 kV/µs

PARAMETER VALUEDESAT activation to gate driver turn OFF 760 nsDESAT activation to fault 1.12 µsSoft shutdown time 10 µsShort circuit current 1.08 kADip in Vce 270 V



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7.14 Short Circuit Test — Fault Under LoadA fault under load short circuit test was performed using the power module CM150TX-4S1_MITSUBISHI.This test is conducted using a add on module for the short circuit consisting of high power IGBTconnected between one of the phase output to DC negative. Refer Figure 101 for the test setup.

Figure 101. Setup for Short Circuit Test — Fault Under Load

7.14.1 Fault Under Load Short Between Phase to DC –ve for 2.5-kV/µs Inverter OutputTest conditions:• Short circuit connection: R phase inverter output to DC negative• Motor connected: Yes• Inverter dV/dT: 2.5 kV/µs• IGBT module: CM150TX-24S1_MITSUBISHI• Gate charge (QG): 315 nC• Internal resistance: 13 Ω• Input capacitance CIES: 15 nF



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SMPS PWMs

+16 V

-8 V

DC bus sensing

NTC output

+24-V DC

+800-V DC

C20

00 L

aun

chP

AD

inte

rfac

e

Gate drive

signals

Reinforced isolated

IGBT gate driver ±

ISO5852S

IGBT power module

HALF BRIDGESMPS

+16 V

-8 V 3N�ACIM

Isolated gate driver

800 V -ve

Add on module for short circuit test


Figure 102. Block Diagram of Fault Under Load Test Short Between Phase to DC –ve

Figure 103. DESAT Activation to Fault Output Figure 104. Gate Driver Output During Soft Shutdown

Table 17. Summary of Short Circuit Test — Fault Under Load for 2.5 kV/µs(Phase Output to DC Negative)

PARAMETER VALUEDESAT activation to gate driver turn OFF 1.30 µsSoft shutdown 14.80 µs



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SMPS PWMs

+16 V

-8 V

DC bus sensing

NTC output

+24-V DC

+800-V DC

C20

00 L

aun

chP

AD

inte

rfac

e

Gate drive

signals

Reinforced isolated

IGBT gate driver ±

ISO5852S

IGBT power module

HALF BRIDGESMPS

+16 V

-8 V 3N�ACIM

Isolated gate driver

Add on module for short circuit test


7.14.2 Fault Under Load — Short Circuit Between Phase to PhaseA fault under load short circuit test was performed using Mitsubishi power module CM150TX-24S1. Thistest is conducted using a add-on module for the short circuit consisting of high-power IGBT connectedbetween R_phase and Y_phase of inverter output (see Figure 105).

Figure 105. Block Diagram of Fault Under Load Test — Phase-to-Phase Short (dV/dt: 2.5 kV/µs)

Test conditions:• Short circuit connection: Between R_phase and Y_phase• Motor connected: Yes• Inverter dV/dT: 2.5 kV/µs• Cable length: 10 meters• IGBT module: CM150TX-24S1_MITSUBISHI• Gate charge (QG): 315 nC• Internal resistance: 13 Ω• Input capacitance CIES: 15 nF



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Figure 106. Gate Driver Output During Soft Shutdown Figure 107. DESAT Activation to Gate Driver Turn Off

NOTE: CH1: Fault signal, CH2:PWM from Controller, CH3: DESAT signal, CH4: Gate driver output

Figure 108. IC– During Short Circuit Fault Under Load

NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driveroutput

Table 18. Summary of Short Circuit Test for Fault Under Load for 2.5 kV/µs (Phase-to-Phase Short)

PARAMETER VALUEDESAT activation to gate driver turn OFF 420.0 nsSoft shutdown of gate driver output 11.20 µsPeak current 980 A



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7.15 EMC Test

7.15.1 Electrical Fast Transient (EFT) TestEFT pulses were applied to motor cable using capacitive coupling clamp as per IEC 61000-4-4. This testwas conducted for multiple levels of fast transient voltages (±1 kV, ±2 kV, ±3 kV, ±4 kV) at 5 kHz forduration of 60 seconds.

Different configurations used during testing are listed in Table 19:

Table 19. EFT Test Configurations

UUT/AUX EQUIPMENTTEST CONFIGURATION MOTOR CABLE REFERENCELOCATION1 Shielded Ground plane Figure 1092 Shielded 10-cm isolated from plane Figure 1103 Unshielded Ground plane Figure 1114 Unshielded 10-cm isolated from plane Figure 112

Test setup:• DC bus voltage: 400 V• Auxiliary unit power rating: 2.2 kW• Load condition: No load• Motor rpm: 750 rpm• Cable length: 10 meters• EFT test equipment: emtest UCS 500N• Capacitor coupling network



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Figure 109. Test Configuration 1 Figure 110. Test Configuration 2

Figure 111. Test Configuration 3 Figure 112. Test Configuration 4

Table 20. EFT Test Results

TEST RESULTSEFT PULSES DURATION

Config:1 Config:2 Config:3 Config:41 kV 60 seconds PASS PASS PASS PASS

–1 kV 60 seconds PASS PASS PASS PASS2 kV 60 seconds PASS PASS PASS PASS



–4 kV 60 seconds PASS PASS PASS PASS

Test pass refers to motor running continuously (without unusual sound) with no malfunctioning observed inthe power stage (includes IGBT gate drivers), thereby meeting performance class B requirements as perIEC61800-3.



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7.15.2 Electrostatic Discharge (ESD) TestESD pulses were applied (contact discharge) to the heat sink while the power stage was running themotor to check for malfunctions. CD was applied on the heat sink close to the IGBT gate drivers. ESDpulses were applied at multiple levels (±2 kV, ±4 kV, ±6 kV, ±8 kV) with 10 pulses on each polarity andlevel. IEC 61000-4-2 has been used as reference for the test method.

Different configurations used during testing are listed in Table 21:

Table 21. ESD Test Configurations

TEST CONFIGURATION UUT/AUX EQUIPMENT LOCATION REFERENCE1 Insulated sheet Figure 113 and Figure 1142 Ground reference plane Figure 1163 10 cm isolated from reference Figure 115

Test setup:• DC bus voltage: 400 V• Auxiliary unit power rating: 2.2 kW• Load condition: No load• Motor rpm: 750 rpm• Cable length: 10 meters (Unshielded)• ESD test equipment: emtest UCS 500N

Table 22. ESD Test Results

TEST RESULTSESD PULSES DURATION

Config:1 Config:2 Config:32 kV 10 pulses PASS PASS PASS

–2 kV 10 pulses PASS PASS PASS4 kV 10 pulses PASS PASS PASS



–8 kV 10 pulses PASS PASS PASS

A test pass refers to the motor running continuously (without unusual sound) with no malfunctioningobserved in the power stage (includes IGBT gate drivers), thereby meeting performance class Brequirements as per IEC61800-3.



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Figure 113. EUT/AUX Equipment on Insulated Sheet

Figure 114. Test Configuration 1 Figure 115. EUT/AUX Equipment Isolated FromReference Plane by 10 cm

Figure 116. Test Configuration 2: EUT/AUX Equipment on Reference Plane



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1

2

3

1986242-3CN3

MOTOR_R_PHASEMOTOR_Y_PHASEMOTOR_B_PHASE

GATE_R_TOP

GATE_R_BOTTOM

GATE_Y_TOP

GATE_Y_BOTTOM

GATE_R_TOP_RTN

GATE_R_BOT_RTN

GATE_Y_BOT_RTN

GATE_Y_TOP_RTN

NTC_1

GATE_B_TOP

GATE_B_BOTTOM

GATE_B_TOP_RTN

GATE_B_BOT_RTN

IGBT Module

Motor connector

PGND

1

CN1

Terminal bush

1

CN2

RHRG75120

A C

D1

DC_VOLT_POS130

DC_VOLT_POS231

DC_VOLT_POS332

DC_VOLT_NEG133

DC_VOLT_NEG234

DC_VOLT_NEG335

GATE_R_TOP1

GATE_R_BOTTOM3

GATE_Y_TOP5

GATE_Y_BOTTOM7

GATE_R_TOP_RTN2

GATE_R_BOT_RTN4

GATE_Y_BOT_RTN8

GATE_Y_TOP_RTN6

MOT_Y_PHASE124

MOT_Y_PHASE225

MOT_Y_PHASE326

NTC_220

NTC_119

MOT_B_PHASE323

MOT_B_PHASE222

MOT_B_PHASE121

GATE_B_BOT_RTN12

GATE_B_TOP_RTN10

GATE_B_BOTTOM11

GATE_B_TOP9

DC_VOLT_NEG615

DC_VOLT_NEG514

DC_VOLT_NEG413

DC_VOLT_POS618

DC_VOLT_POS517

DC_VOLT_POS416

MOT_R_PHASE329

MOT_R_PHASE228

MOT_R_PHASE127

FS200R12KT4R

U1

IC_FS200R12KT4R

DGND

NTC_2

APT70GR120L

C

G

E

Q1GATE_BRAKE

DC_POS

BRAKE

1

CN11

Terminal bush

1

CN12

RHRG75120

AC

D2

MOTOR_B_PHASE

MOTOR_R_PHASE

MOTOR_Y_PHASE

B59109J0130A020t°

RT1100R_PTC

INRUSH_BYPASS

680µF

C3

680µFC6

680µFC7

200KR208

200KR209

200KR210

200KR211

200KR212

200KR213 0.22µF

C154FILM CAP

www.ti.com Design Files

8 Design Files

8.1 SchematicsTo download the schematics, see the design files at TIDA-00195.

Figure 117. IGBT Module



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0.1µFC48

0R

R40

ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U9

10RR42

1 2

QPC02SXGN-RCJ8

12

QPC02SXGN-RCJ6

10nFC55

RST2

RDY2

FLT2

12

QPC02SXGN-RCJ7

3V3

DGND

200pF

C57

100pFC56

12

QPC02SXGN-RCJ9

1

TP2

PWM_DRV_R_BOT

VEE_R_BOT

0.1µFC31

0.1µFC28

0RR34

ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U7

10RR36

0.1µF

C33

1 2

QPC02SXGN-RCJ3

12

QPC02SXGN-RCJ1

10nFC38

RST1

RDY1

FLT1

12

QPC02SXGN-RCJ2

3V3

DGND

200pFC40

100pFC39

12

QPC02SXGN-RCJ4

1

TP1

PWM_DRV_R_TOP

VEE_R

+15V R

-8V R

Gate Driver Top IGBT R

Gate Driver Bottom IGBT R

GATE_R_TOP

GATE_R_BOTTOM

DC_POS

GATE_R_TOP_GND

GATE_R_BOT_RTN

+15V R

VEE_R GATE_R_TOP_RTN

1k

R39

1k

R45

12QPC02SXGN-RC

J17

GATE_R_TOP_GND

12

QPC02SXGN-RCJ16

MM

3Z

12

VB

AC

D26

MM

3Z

12

VB

AC

D24

SK310A-LTP

AC

D3

SK310A-LTP

AC

D5

IN+_R_TOP

IN-_R_TOP

IN+_R_TOP

IN-_R_TOP

DGND

3V3

IN+_R_BOT

IN-_R_BOT

DGND

3V3

IN+_R_BOT

IN-_R_BOT

GATE_R_BOT_GND

1

1

2

2

1

1

2

2


DNP

DNP

NOTE:To disable DESATDNP DESAT CapcitorPopulate Jumper

NOTE:Unipolar supply- Populate J1 onlyBipolar supply- Populate J2 only

All Notes are applicable for all Gate Driver Sections

GL41Y-E3/96

A C

D4

GL41Y-E3/96

A C

D23

GL41Y-E3/96

A C

D6

GL41Y-E3/96

A C

D25

1

TP44

1

TP17

1

TP18

1

TP19

1

TP20

1

TP21

MJD3055T4

3

1

2

Q6

MJD2955T4

2

1

3

Q8

2.2RR121

2.2RR134

SUD40N08-16-E3Q7

SUD50P08-25L-E3Q9

MJD3055T4

3

1

2

Q10

MJD2955T4

2

1

3 Q12

2.2RR145

2.2RR161

SUD40N08-16-E3Q11

SUD50P08-25L-E3Q13

4.7µF

C29

4.7µFC46

220RR35

220RR38

220RR41

220RR44

10uF

C25

10uF

C35

DNP

DNP

10R R220

10R R219

1µF

C173

1µF

C174

0RR48

0RR49

0R

R233

1µF

C176

0.1µFC45

0.1µFC50

10uFC42

10uFC51

1µF

C177

0R

R234

0R

R236

0RR235

1

TP37

1

TP38

DNP

DNP

DNP

DNP

DNP

DNP

DNP

DNP

3

DNP

3

NOTE :3. DNP While testingwith twistedpair

DNP

3

DNP

3

DNPNOTE :

3. DNP While testingwith twistedpair

0RR60

0R

R61

0R

R62

0RR63

0RR66

0R

R67

0R

R82

0RR105

0RR107

0RR122

0RR135

0RR146

GATE_R_BOT_GND

+15V R_BOT

-8V R_BOT

VEE_R_BOT

+15V R_BOT

DNP

DNP

0RR37

0RR7

DNP

DNP

DNP

DNP

RB

16

0M

-60

TR

AC

D69

RB

16

0M

-60

TR

AC

D70

GATE_R_TOP_GND

GATE_R_BOT_GND

GATE_R_TOP_RTN

1µFC175

1µFC172

Design Files www.ti.com

Figure 118. Gate Driver R



http://www.ti.com


0.1µFC135

0R

R147

ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U22

10RR149

1 2

QPC02SXGN-RCJ28

12

QPC02SXGN-RCJ25

10nFC142

12

QPC02SXGN-RCJ26

3V3

DGND

200pF

C138100pFC139

12

QPC02SXGN-RCJ27

1

TP5

PWM_DRV_Y_BOT

VEE_Y_BOT

0.1µFC58

0R

R133

ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U20

10R

R137

1 2

QPC02SXGN-RCJ22

12

QPC02SXGN-RCJ19

10nFC71

12

QPC02SXGN-RCJ20

3V3

DGND

200pFC64

100pFC66

12

QPC02SXGN-RCJ21

1

TP4

PWM_DRV_Y_TOP

VEE_Y

+15V Y

-8V Y

Gate Driver Top IGBT Y

Gate Driver Bottom IGBT Y

GATE_Y_TOP

GATE_Y_BOTTOM

DC_POS

GATE_Y_TOP_GND

GATE_Y_BOT_RTN

+15V Y

VEE_Y GATE_Y_TOP_RTN

1k

R132

1k

R144

12QPC02SXGN-RC

J30

GATE_Y_TOP_GND

12

QPC02SXGN-RCJ24

GATE_Y_TOP_GND

MM

3Z

12

VBA

C

D51

MM

3Z

12

VBA

C

D47

SK310A-LTP

AC

D48

SK310A-LTP

AC

D52

IN+_Y_TOP

IN-_Y_TOP

DGND

3V3

DGND

3V3

IN+_Y_BOT

IN-_Y_BOT

1

1

2

2

1

1

2

2


IN+_Y_TOP

IN-_Y_TOP

IN+_Y_BOT

IN-_Y_BOT

RDY3

FLT3

RST3

RDY4

FLT4

RST4

DNP

DNP

GL41Y-E3/96

A C

D45

GL41Y-E3/96

A C

D46

GL41Y-E3/96

A C

D49

GL41Y-E3/96

A C

D50

1

TP22

1

TP23

1

TP24

1

TP25

1

TP26

1

TP27

MJD3055T4

3

1

2

Q14

MJD2955T4

2

1

3

Q16

2.2RR172

2.2RR183

SUD40N08-16-E3Q15

SUD50P08-25L-E3Q17

MJD3055T4

3

1

2

Q18

MJD2955T4

2

1

3

Q20

2.2RR185

2.2RR187

SUD40N08-16-E3Q19

SUD50P08-25L-E3Q21

4.7µF

C54

4.7µF

C134

220RR136

220RR139

220RR148

220RR151

DNP

DNP

10R R215

10R R214

1µFC179

1µFC180

0.1µFC53

0.1µFC61

10uFC52

10uFC59

0R

R237

0RR238

0R

R239

1µFC182

1µFC183

0.1µFC133

0.1µFC137

10uFC60

10uFC69

0R

R240

0RR241

0R

R242

1

TP39

1

TP40

DNP

DNP

DNP

DNP

DNP

DNP

DNP

DNP

3

DNP

3


DNP

DNP

3

DNP

3


0RR128

0R

R129

0R

R130

0RR131

0RR140

0R

R141

0R

R142

0RR143

0RR184

0RR186

GATE_Y_BOT_GND

GATE_Y_BOT_GND

GATE_Y_BOT_GND

+15V Y_BOT

-8V Y_BOT

+15V Y_BOT

VEE_Y_BOT

DNP

DNP

0RR138

0R

R150

DNP

DNP

DNP

0RR162

0RR173

DNP

RB

16

0M

-60

TR

AC

D71

RB

16

0M

-60

TR

AC

D72

GATE_Y_TOP_RTN

1µFC181

1µFC178


Figure 119. Gate Driver Y



http://www.ti.com


0.1µFC157

0.1µFC155

0R

R174

ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U26

10R

R176

0.1µFC159

1 2

QPC02SXGN-RCJ40

12

QPC02SXGN-RCJ37

10nFC164

12

QPC02SXGN-RCJ38

3V3

DGND

200pF

C160100pFC161

12

QPC02SXGN-RCJ39

1

TP7

PWM_DRV_B_BOT

VEE_B_BOT

0.1µFC146

0RR160

ISO5852

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN-11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

U24

10R

R164

1 2

QPC02SXGN-RCJ34

12

QPC02SXGN-RCJ31

10nFC153

12

QPC02SXGN-RCJ32

3V3

DGND

200pFC149

100pFC150

12

QPC02SXGN-RCJ33

1

TP6

PWM_DRV_B_TOP

VEE_B

+15V B

-8V B

Gate Driver Top IGBT B

Gate Driver Bottom IGBT B

GATE_B_TOP

GATE_B_BOTTOM

DC_POS

GATE_B_TOP_GND

GATE_B_BOT_RTN

+15V B

VEE_B GATE_B_TOP_RTN

1k

R159

1k

R171

12

QPC02SXGN-RCJ42

GATE_B_TOP_GND

12QPC02SXGN-RC

J36

GATE_B_TOP_GND

MM

3Z

12

VB

AC

D59

MM

3Z

12

VB

AC

D55

SK310A-LTP

AC

D56

SK310A-LTP

AC

D60

DGND

3V3

DGND

3V3

IN+_B_BOT

IN-_B_BOT

1

1

2

2

1

1

2

2


IN+_B_TOP

IN-_B_TOPIN+_B_TOP

IN-_B_TOPRDY5

FLT5

RST5

RDY6

FLT6

RST6

IN+_B_BOT

IN-_B_BOT

DNP

DNP

GL41Y-E3/96

A C

D53

GL41Y-E3/96

A C

D54

GL41Y-E3/96

A C

D57

GL41Y-E3/96

A C

D58

1

TP31

1

TP32

1

TP33

1

TP28

1

TP29

1

TP30

MJD3055T4

3

1

2

Q22

MJD2955T4

2

1

3

Q24

2.2RR189

2.2RR191

SUD40N08-16-E3

D2

G1

S3

Q23

SUD50P08-25L-E3D2

G1 S

3

Q25

MJD3055T4

3

1

2

Q26

MJD2955T4

2

1

3

Q28

2.2RR193

2.2RR195

SUD40N08-16-E3Q27

SUD50P08-25L-E3Q29

4.7µFC145

4.7µFC156

220RR163

220RR166

220RR175

220RR178

10uFC98

10uFC101

DNP

DNP

10R R217

10R R2160.1µFC144

0.1µFC148

10uFC91

10uFC941µF

C185

1µFC186

1

TP41

0R

R243

0RR244

0R

R245

1

TP42

1µFC188

1µFC189

0R

R246

0RR247

0R

R248

DNP

DNP

DNP

DNP

DNP

DNP

DNP

DNP

3

DNP

3


DNP

DNP

3

DNP

3


0RR155

0R

R156

0R

R157

0RR158

0RR167

0R

R168

0R

R169

0RR170

0RR188

0RR190

0RR192

0RR194

GATE_B_BOT_GND

GATE_B_BOT_GND

GATE_B_BOT_GND

+15V B_BOT

-8V B_BOT

+15V B_BOT

VEE_B_BOT

DNP

DNP

0RR165

0RR177

DNP

DNP

DNP

DNP

RB160M-60TR

AC

D73

RB

16

0M

-60

TR

AC

D74

GATE_B_TOP_RTN

1µFC184

1µFC187


Figure 120. Gate Driver B



http://www.ti.com


0.1µFC65

0.1µFC62

0R

R54

VCC115

GND19

GND116

OUTH4

OUTL6

CLAMP7

DESAT2

IN11

IN+10

GND23

VCC25

RDY12

FLT13

RST14

VEE21

VEE28

ISO5852

U11

0.1µF

C67

12

QPC02SXGN-RCJ11

RST7

RDY7

FLT7

12

QPC02SXGN-RC

J12

3V3

DGND

200pFC74

100pFC73

12

QPC02SXGN-RCJ14

1

TP3

VEE_BRAKE

GATE_BRAKE

Gate Driver Brake IGBT

PWM_DRV_BRAKER

BRAKE

1k

R59

12

QPC02SXGN-RCJ18

MM

3Z

12

VB

AC

D39

DGND

3V3

IN+_BRAKE

IN-_BRAKE

IN+_BRAKE

IN-_BRAKE

1

1

2

2

DNP

GL41Y-E3/96

A C

D10

GL41Y-E3/96

A C

D62

1

TP34

1

TP35

4.7µF

C63

47R

R55

47R

R58

10uFC104

10uFC107

10R R218

1µFC191

1µF

C192

1

TP43

0RR251

PGND

DNP

DNP

0RR117

0R

R118

0R

R119

0RR120

GATE_B_BOT_GND

GATE_B_BOT_GND

GATE_B_BOT_GND

+15V B_BOT

-8V B_BOT


DNP3

RB

16

0M

-60

TR

AC

D75

1µFC190


Figure 121. Brake Drive



http://www.ti.com


RDY1

RDY2

RDY3

RDY4

RDY5

RDY6

RDY7

LTST-C170EKTRED

AC

D8

FLT1

FLT2

FLT3

FLT4

FLT5

FLT6

FLT7

DGND

RDY

FLT

3V3

DGND

3V3

0R

R51

RST1

RST2

RST3

RST4

RST5

RST6

RST7

RSTRST

Ready Indication

Fault Indication

Reset Control

LTST-C170GKT

GREEN

AC

D7

+15V R

-8V R

+15V Y

-8V Y

+15V B

-8V B

LTST-C170GKT

GREENA CD27

GREENACD28

GREENA CD29

GREENA CD31

GREENA CD83

620 Ohm R109

1.3K R108

620Ohm R111

1.3K R110

620Ohm R113

1.3K R112

620Ohm R6

1.3K R5

GREENACD30

GREENACD32

GREENACD84

SMPS Power Rails LED indications

120Ohm

R52

120OhmR47

+24VGREEN

A CD35

+5VGREEN

A CD36

3V3GREEN

A CD37

+15V

LTST-C170GKT

GREENA CD381.3K R116

DGND

GND

120Ohm R154

300Ohm R153

2.37K R152

BC847BPN,115Q3B

BC847BPN,115Q3A

3V3

10KR64

10KR65

3V3

GATE_R_TOP_GND

GATE_Y_TOP_GND

GATE_B_TOP_GND

GATE_R_TOP_GND

GATE_Y_TOP_GND

GATE_B_TOP_GND

20K

R50

20K

R53

GREENA CD81

620 Ohm R4

1.3K R3

GREENACD82

GREENA CD33

620 Ohm R2

1.3K R1

GREENACD34

+15V R_BOT

-8V R_BOT

GATE_R_BOT_GND

GATE_R_BOT_GND

GATE_Y_BOT_GND+15V Y_BOT

-8V Y_BOTGATE_Y_BOT_GND

GATE_B_BOT_GND+15V B_BOT

-8V B_BOTGATE_B_BOT_GND


Figure 122. LED Indications



http://www.ti.com


PWM_DRV_R_TOP

PWM_EN

BRAKER_ON

PWM_DRV_BRAKER

GATE_DRIVER_BUFFER

3V3

DGND

10KR12

3V3

0.01µFC68

FAN_DRV

FAN_DRV_BUFFER

10

KR

27

10K

R1

7

1OE1

1A2

1Y3

2OE4

2A5

2Y6

GND7

3Y8

3A9

3OE10

4Y11

4A12

4OE13

VCC14

U3

SN74ALVC125PW

PWM_R_TOP

DGNDDGNDDGND

PWM_EN

PWM_DRV_B_BOT

3V3

DGND

10KR19

3V3

0.01µFC70

10

KR

25

10KR26

1OE1

1A2

1Y3

2OE4

2A5

2Y6

GND7

3Y8

3A9

3OE10

4Y11

4A12

4OE13

VCC14

U5

SN74ALVC125PW

PWM_B_BOT

DGND

DGND

DGND

PWM_DRV_Y_TOP

PWM_EN

PWM_DRV_R_BOT

3V3

DGND

10KR106

3V3

0.01µFC34

10

KR

16

10

KR

20

1OE1

1A2

1Y3

2OE4

2A5

2Y6

GND7

3Y8

3A9

3OE10

4Y11

4A12

4OE13

VCC14

U2

SN74ALVC125PW

PWM_Y_TOP

PWM_R_BOT

DGNDDGNDDGND

PWM_DRV_B_TOP

PWM_EN

PWM_DRV_Y_BOT

3V3

DGND

10KR18

3V3

0.01µFC195

10K

R2

4

10K

R2

3

1OE1

1A2

1Y3

2OE4

2A5

2Y6

GND7

3Y8

3A9

3OE10

4Y11

4A12

4OE13

VCC14

U4

SN74ALVC125PW

PWM_B_TOP

PWM_Y_BOT

DGNDDGNDDGND

DGND

10R

R15 10R

R14

10R

R21

10R

R22

PWM_ENDGND


Figure 123. Gate Driver Buffer



http://www.ti.com


PPPC102LFBN-RC

1

2

3

4

5

6

7

8

9

1011

12

13

14

15

16

17

18

19

20

CN6

PWM_R_TOPPWM_R_TOP

PWM_Y_TOP

PWM_B_TOP

PWM_R_BOT

PWM_Y_BOT

PWM_B_BOT

DGND

DGND

HI_PWM

LI_PWM

BRAKER_ON

BYPASS_RELAY

DGND

DGND

DGND

DGND

DGND

DGND

PWM_Y_TOP

PWM_B_TOP

PWM_R_BOT

PWM_Y_BOT

PWM_B_BOT

PPPC102LFBN-RC

1

2

3

4

5

6

7

8

9

1011

12

13

14

15

16

17

18

19

20

CN9

PWM_EN

FLT

RDY

RST

DGND

+5V

NTC_1

DC_BUS_SENSE_POS

DC_BUS_SENSE_NEG

Fro

m L

aun

ch

Pad

3V3

3V3

FAN_DRV

0.01µFC76

10RR68

0.01µFC81

10RR73

0.01µFC80

10RR72

0.01µFC79

10RR71

0.01µFC78

10RR70

0.01µFC77

10RR69

10R

R74

0.01µFC82

0R

R8

DGND

0RR13

LI_PWM

HI_PWM

Launch Pad Connector J1 & J5

Launch Pad Connector J6 & J2

10KR75

1.5nFC27

10RR9

10RR10

10RR11

1.5nFC26

0.01µFC24

DGND

DGND

DGND

10uFC16810uFC169

0.01µF

C196

DGND


Figure 124. Board-to-Board Connections



http://www.ti.com


AMC1200SDUBR

VOUTP7

VDD28

VOUTN6

VINN3

GND14

VDD11

GND25

VINP2

U14

10pFC87

10pFC86

0.1µF C84

+5V_ISO

GND_ISO

0.1µF

C83

0RR84

0RR86

DC_BUS_SENSE_POS

DC_BUS_SENSE_NEG

DC BUS VOLTAGE SENSING

0.01µFC85

SN6501DBVR

D11

VCC2

D23

GND4

GND5

U19

DGND

MBR0520LT3G

A C

D40

MBR0520LT3G

A C

D410.1µFC43

+5V_ISO

10KR88

1KR85

1M

R76

1M

R77

1M

R78

1M

R79

1M

R80

1M

R81DGND

DGND

+5V

GND_ISOGND_ISO

GND_ISO

PGND GND_ISO

0R

R123

0.1µF

C37

+5V

DGND

10 Ohm

R83

10 Ohm

R87

3V3

4.7µFC166

MM3Z5V1BAC

D63

47 OhmR200

DC_POS

Wurth Elektronik750313734

1

2

34

5

6T1

10uFC36

10µFC41

10µFC44

0.1µFC197

DNP


Figure 125. DC Bus Voltage Sensing



http://www.ti.com


0.1µFC90

68µF

C89

HSG

LSG

0RR89

0R

R92

Half Bridge converter : SMPS

+15V

DGND

DGND DGND

DGND

DGND

LI_PWM

HI_PWM

0RR125

+24V

+24V

HS

HS

DGND DGND

SK310A-LTP

AC

D44

SK310A-LTP

AC

D43

SK310A-LTP

A C

D42

CSD88537ND

7

2

1

5

4

3

6

8

U15

17.8 ohmR90

17.8 ohmR91

10µFC47

0393570002Molex

1

2

P1

0RR232

UCC27211DPRT

VD

D1

LI8

LO10

VS

S9

HO3

HS4

HB2

NC5

NC6

HI7

U16

0.1µF

C1100RR124

0.33 µFC49

0.1µFC109

0.1µFC113

0.1µFC126

0.1µFC147

+15V R_BOT

-8V R_BOT

GATE_R_BOT_GND

LS1

750313734

3

5

8

9

13

14

T2

Transformer_SMPS

10µFC10810µFC105

10µFC11610µFC114

10µFC143

10µFC112

47uFC106

47uFC111

47uFC115

47uFC136

S5B-E3/57T

A C

D11

+15V R

-8V R

GATE_R_TOP_GND

3.3uFC88

3.3uFC97

RB160M-60TR

AC

D68

RB160M-60TR

AC

D76

RB160M-60TR

AC

D77

RB160M-60TR

AC

D78

RB160M-60TR

AC

D79

RB160M-60TR

AC

D80


Figure 126. Gate Driver Power Supply (R Phase)



http://www.ti.com


0.1µFC5

0.1µFC10

0.1µFC14

0.1µFC17

+15V Y_BOT

-8V Y_BOT

GATE_Y_BOT_GND

HS

LS2

0.1µFC21

0.1µFC92

0.1µFC99

0.1µFC103

+15V B_BOT

-8V B_BOT

GATE_B_BOT_GND

HS

3

5

8

9

13

14

750313734

T3

Transformer_SMPS

3

5

8

9

13

14

750313734

T4

Transformer_SMPS

10µFC4

10µFC1

10µFC9

10µFC1310µFC11

10µFC16

10µFC2010µFC18

10µFC23

10µFC9610µFC93

10µFC102

47uFC2

47uFC8

47uFC12

47uFC15

47uFC19

47uFC22

47uFC95

47uFC100

+15V Y

-8V Y

GATE_Y_TOP_GND

+15V B

-8V B

GATE_B_TOP_GND

DGND

+24V

3.3uFC158

3.3uFC165

DGND

+24V

3.3uFC167

3.3uFC170

LS3

RB160M-60TR

AC

D12

RB160M-60TR

AC

D13

RB160M-60TR

AC

D14

RB160M-60TR

AC

D15

RB160M-60TR

AC

D16

RB160M-60TR

AC

D17

RB160M-60TR

AC

D18

RB160M-60TR

AC

D19

RB160M-60TRAC

D64

RB160M-60TR

AC

D65

RB160M-60TR

AC

D66

RB160M-60TR

AC

D67


Figure 127. Gate Driver Power Supply (Y and B Phase)



http://www.ti.com


+24V

GND GND

+24V

GND

3.3R

R93

51.1KR97

+15V

+15V

GND

3.3R

R94

0RR95

0RR99

GND

GND

+5V

20KR100

GND

LP38691DTX

GN

D2

VCC3

VOUT1

U18

GND

+5V 3V3

+5V

Buck Converter 24V to 15V & 5V

3.3V LDO

1nFC121

1nFC122

100uH 0.5AL1

47uH 1.5AL2

GND

2.87KR101

GND DGND

TPS54286PWP

PVDD11

BOOT12

SW13

FB28

EN15

GND4

BP11

BOOT213

EN26

FB17

SEQ10

ILIM29

SW212

PVDD214

PW

PD

15

U17

DNP

DNP

10RR98

10RR96

3.83KR102

10µF

C117

10µF

C118

10µFC129

10µFC130

0.033µF

C119

0.033µF

C120

4.7µFC123

4.7µF

C127

4.7µFC125

4.7µF

C128

10µFC124

SK310A-LTP

AC

D20

SK

310

A-L

TP

AC

D21

GND

0.01µFC30

0.01µFC32

DNP

DNP


Figure 128. Buck Converter 24 V to 15 V and 5 V



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HE1aN-P-DC24V-Y5

5 6

1 4

RL1

470R

R104

10R

R103+24V

BYPASS_RELAY

DGND

Inrush Bypass Relay : Drive Circuit Fan Driver Circuit

DNP

1

2

CN10

Fan

10KR180

+24V

DGND

200Ohm

R179FAN_DRV_BUFFER

C

B

E

Q5PZT2222A

0RR182

CSD18531Q5A

D

G

S

Q4MFG_PN

FAN_DRV_BUFFERSK310A-LTP

AC

D22

SK310A-LTP

AC

D61

INRUSH_BYPASSPGND

10µFC131


Figure 129. Inrush Relay



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8.2 Bill of MaterialsTo download the bill of materials (BOM), see the design files at TIDA-00195.

8.3 Layer PlotsTo download the layer plots, see the design files at TIDA-00195.

8.4 Altium ProjectTo download the Altium project files, see the design files at TIDA-00195.

8.5 Gerber FilesTo download the Gerber files, see the design files at TIDA-00195.

8.6 Assembly DrawingsTo download the assembly drawings, see the design files at TIDA-00195.



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www.ti.com References

9 References

1. IEEE, Analytical calculation of the RMS current stress on the DC-link capacitor of voltage-PWMconverter systems, Kolar, J.W.; ETH Zurich, Power Electron. Syst. Lab., Zurich; Round, S.D., July2006

10 Terminology

PWM— Pulse Width Modulation

LaunchPad— All reference to LaunchPad refers to InstaSPIN-FOC enabled C2000 LaunchPads

CFM— Cubic Feet per Minute

MCU— Microcontroller unit

FETs, MOSFETs—Metal–oxide–semiconductor field-effect transistor

IGBT— Insulated Bipolar Gate Transistor

ESD— Electro Static Discharge

EFT— Electrical Fast Transients

RPM— Rotation per Minute

RMS— Root Mean Square

11 AcknowledgmentsThe authors would like to thank Kamat Anant and Baranwal Shailendra (Industrial Interface Business unitat TI) for their technical contributions to this design.

12 About the AuthorsKRISTEN MOGENSEN is a system engineer in the Industrial Systems–Motor Drive team at TexasInstruments, responsible for developing reference designs for industrial drives.

N. NAVANEETH KUMAR is a systems architect at Texas Instruments, where he is responsible fordeveloping subsystem solutions for motor controls within Industrial Systems. N. Navaneeth brings to thisrole his extensive experience in power electronics, EMC, analog, and mixed signal designs. He hassystem-level product design experience in drives, solar inverters, UPS, and protection relays. N.Navaneeth earned his Bachelor of Electronics and Communication Engineering from BharathiarUniversity, India and his Master of Science in Electronic Product Development from Bolton University, UK.



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Revision History www.ti.com

Revision History

Changes from Original (June 2015) to A Revision ......................................................................................................... Page

• Added Note under Section 7.13 ....................................................................................................... 46

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

74 Revision History TIDUA15A–June 2015–Revised August 2015Submit Documentation Feedback


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