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FN8264Rev.11.00
Jun 11, 2019
ISL70002SEHRadiation Hardened and SEE Hardened 18A Synchronous Buck Regulator with Current Sharing
DATASHEET
The ISL70002SEH is a radiation hardened and SEE hardened high-efficiency monolithic, synchronous buck regulator with integrated MOSFETs. This single chip power solution operates over an input voltage range of 3V to 5.5V and provides a tightly regulated output voltage that is externally adjustable from 0.8V to ~85% of the input voltage. Output load current capability is primarily determined by PVIN voltage with up to 22A for a single IC at PVIN ≤ 5.5V for TJ ≤ +125°C. Two ISL70002SEH devices, configured to current share, can provide up to 38A of total output current at PVIN ≤ 5.5V for TJ ≤ +125°C assuming ±27% worst-case current share accuracy.
The ISL70002SEH uses peak current-mode control with integrated error amp compensation and pin-selectable slope compensation. Switching frequency is also pin selectable to either 1MHz or 500kHz. Two devices can be synchronized 180° out-of-phase to reduce input RMS ripple current.
High integration makes the ISL70002SEH an ideal choice to power small form factor applications. Two devices can be synchronized to provide a complete power solution for large scale digital ICs, like Field Programmable Gate Arrays (FPGAs) that require separate core and I/O voltages.
Applications• FPGA, CPLD, DSP, CPU core, and I/O voltages
• Low-voltage, high-density distributed power systems
Related LiteratureFor a full list of related documents, visit our website:
• ISL70002SEH device page
Features• DLA SMD 5962-12202
• Maximum output current for a single device: Up to 22A (see “Absolute Maximum Ratings in a Heavy Ion Environment” on page 9)
• Maximum output current for two current sharing devices based on 27% worst case current share mismatch: Up to 38A (see “Absolute Maximum Ratings in a Heavy Ion Environment”)
• Available in a thermally enhanced heat spreader package (R64.C)
• 1MHz or 500kHz switching frequency
• 3V to 5.5V supply voltage range
• ±1% reference voltage (line, load, temperature, and rad)
• Redundancy/junction isolation: exceptional SET performance
• Excellent transient response
• High efficiency >90%
• Two ISL70002SEH synchronization, inverted-phase
• Comparator input for enable and power-good
• Input undervoltage, output undervoltage, and adjustable output overcurrent protection
• QML qualified per MIL-PRF-38535
• Full military temperature range operation (-55°C to +125°C)
• Radiation environment
- High dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)
- ELDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)**Level assured by characterization; “EH” version is production tested to 50krad(Si).
• SEE hardness
- SEL and SEB LETTH . . . . . . . . . . . . . . . . 86.4MeV/mg/cm2
- SEFI LETTH. . . . . . . . . . . . . . . . . . . . . . . . . . 43MeV/mg/cm2
- SET LETTH . . . . . . . . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm2
FIGURE 1. EFFICIENCY 5V INPUT, 500kHz, Tcase = +25°C FIGURE 2. 2-PHASE SET PERFORMANCE AT 86.4MeV/mg/cm2
50556065707580859095
100
0 2 4 6 8 10 12 14 16 18 20 22
Effic
ienc
y (%
)
Load Current (A)
0.95VOUT 1.2VOUT1.5VOUT 1.8VOUT2.5VOUT 3.3VOUT CH4 SYNC
CH3 VOUT x 10
CH2 SLAVE LX + 15V
CH1 MASTER LX + 20V
AM
PL
ITU
DE
(V
)
-6 -4 -2 0 2 4 6 8 10 12 14
25
20
15
10
5
0
FN8264 Rev.11.00 Page 1 of 29Jun 11, 2019
ISL70002SEH
Typical Application Schematic
FIGURE 3. SINGLE UNIT OPERATION
FN8264 Rev.11.00 Page 2 of 29Jun 11, 2019
ISL70002SEH
FIGURE 4. TWO-PHASE OPERATION WITH CURRENT SHARING
Typical Application Schematic (Continued)
FN8264 Rev.11.00 Page 3 of 29Jun 11, 2019
ISL70002SEH
Functional Block Diagram
POWER-ONRESET (POR)
PWMREFERENCE
0.6V
SOFT-START
COMPENSATION
EA GM
SLOPECOMPENSATION
GATEDRIVE
CURRENTSENSE
LXx
PVINx
FB
UV
PGOOD POWER-GOOD
PGNDx
AV
DD
SS
M/S
SYNC
PORSEL
REF
TDI
TDOBIT
TPGMTRIM
AGND
DV
DD
DGND
EN
TRIM
SC0
SC1
OVERCURRENTADJUST OCSSA
OCSSB
OCAOCB
FSEL
CURRENTSHARE
PWMCONTROL
LOGIC
ISH
RE
FAIS
HR
EF
B
ISH
RE
FC
ISH
AIS
HB
ISH
C
ISHENISHSL
ISHCOM
GND
PGNDxPGNDx
FIGURE 5. FUNCTIONAL BLOCK DIAGRAM
FN8264 Rev.11.00 Page 4 of 29Jun 11, 2019
ISL70002SEH
Pin Configuration64 LD CQFPTOP VIEW
Ordering InformationORDERING SMD NUMBER
(Note 2) PART NUMBER
(Note 1)TEMP. RANGE
(°C)PACKAGE
(RoHS Compliant)PKG.
DWG. #
5962R1220201VXC ISL70002SEHVF -55 to +125 64 Ld CQFP R64.A
5962R1220201VYC ISL70002SEHVFE -55 to +125 64 Ld CQFP with heat spreader R64.C
5962R1220201V9A ISL70002SEHVX -55 to +125 Die
N/A ISL70002SEHF/PROTO (Notes 3) -55 to +125 64 Ld CQFP R64.A
N/A ISL70002SEHFE/PROTO (Notes 3) -55 to +125 64 Ld CQFP with heat spreader R64.C
N/A ISL70002SEHX/SAMPLE (Notes 3) -55 to +125 Die
N/A ISL70002SEHEVAL1Z (Note 4) Evaluation Board
N/A ISL70002SEHEVAL2Z (Note 4) Current Sharing Evaluation Board
N/A ISL70002SEHDEMO1Z (Note 4) High Current Sharing Demonstration Board
NOTES:
1. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the temperature range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE die is capable of meeting the electrical limits and conditions specified in the DLA SMD at +25°C only. The /SAMPLE is a die and does not receive 100% screening across the temperature range to the DLA SMD electrical limits. These part types do not come with a certificate of conformance because there is no radiation assurance testing and they are not DLA qualified devices.
4. Evaluation board uses the /PROTO parts. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity.
ISHC
ISHREFB
ISHB
ISHREFA
ISHA
FB 1
2
3
4
5
6
7
8
9
10
11
17 18 19 20 21 22
ISHREFC
AVDD
AGND
DGND
DVDD
43
42
41
40
39
38
2726252423
PVIN6
LX6
PGND6
PGND5
LX5
PVIN5
59 58 57 56 55 5448
47
46
45
44
64 63 62 61 60
EN
PV
IN1
LX
1
PG
ND
1
PG
ND
2
LX
2
LX3
PGND3
PGND4
LX4
PVIN4
RE
F
OC
A
OC
SS
A
OC
B
OC
SS
B
28 32313029
53 52 51 50 49
PV
IN2
SC
1
SC
0
NC
/HS
*
PV
IN3
SS 12
13
14
15
16
PGOOD
ISHCOM
ISHSL
ISHEN
37
36
35
34
33 LX8
PGND8
PGND7
LX7
PVIN7
LX
9
PG
ND
9
PG
ND
10
LX
10
PV
IN1
0
SY
NC
PV
IN8
NC
FS
EL
M/S
PV
IN9
GN
D
TP
GM
TD
I
TD
O
PO
RS
EL
*HEAT SPREADER OUTLINE
* Indicates heat spreader package R64.C
PR
OD
UC
T B
RA
ND
NA
ME
AR
EA
1 (FB)
BOTTOM SIDE DETAIL
FOR PIN 1 LOCATION
NOTE:5. The ESD triangular mark is indicative of
Pin #1’s location. It is a part of the device marking and is placed on the lid in the quadrant where Pin #1 is located.
(Note 5)
FN8264 Rev.11.00 Page 5 of 29Jun 11, 2019
ISL70002SEH
Pin DescriptionsR64.A
PIN NUMBERR64.C
PIN NUMBER PIN NAME DESCRIPTION
1 FB Voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and from FB to AGND to adjust the output voltage in accordance with Equation 1:
where: VOUT = output voltageVREF = reference voltage (0.6V typical)RT = top divider resistor (Must be 1kΩRB = bottom divider resistorThe top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate SEE and to improve stability margins.If using current share, tie FB of the master to FB of the slave.
2, 4, 6 ISHA, ISHB, ISHC
If configured as a current share master (ISHSL = DGND, ISHEN = DVDD), these pins are outputs that provide a current equal to 25 times the redundant A/B/C error amp output currents plus ISHREFA/ISHREFB/ISHREFC (nominally 100µA each). If configured as a current share slave (ISHSL = DVDD, ISHEN = DVDD), the ISHA/ISHB/ISHC pins are inputs that become the slave’s redundant A/B/C error amp output current. If using current share, tie ISHA/ISHB/ISHC of the master to ISHA/ISHB/ISHC of the slave. If not using current share, tie ISHA/ISHB/ISHC to DVDD. ISHA/ISHB/ISHC are tri-stated prior to a valid POR and when ISHEN = DGND.
3, 5, 7 ISHREFA, ISHREFB, ISHREFC
If configured as a current share master (ISHSL = DGND, ISHEN = DVDD), these pins provide a reference output current equal to 100µA each. If configured as a current share slave (ISHSL = DVDD, ISHEN = DVDD), the ISHREFA/ISHREFB/ISHREFC pins accept a reference input current. For a current share slave, this input current is used together with the ISHA/ISHB/ISHC current to determine the master’s redundant A/B/C error amp output current. If using current share, tie ISHREFA/ISHREFB/ISHREFC of the MASTER to ISHREFA/ISHREFB/ISHREFC of the slave. If not using current share, tie ISHREFA/ISHREFB/ISHREFC to DVDD. The purpose of the reference current is to reduce the impact of external noise coupling onto ISHA/ISHB/ISHC. ISHREFA/ISHREFB/ISHREFC are tri-stated prior to a valid POR and when ISHEN = DGND.
8 AVDD Bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. AVDD should be the same voltage as DVDD and PVINx (±200mV).
9 AGND Analog ground associated with the internal analog control circuitry. Connect this pin directly to the PCB ground plane.
10 DGND Digital ground associated with the internal digital control circuitry. Connect this pin directly to the PCB ground plane.
11 DVDD Bias supply input to the internal digital control circuitry. Locally filter this pin to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. DVDD should be the same voltage as AVDD and PVINx (±200mV).
12 SS Soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output ramp time in accordance with Equation 2:
where:tSS = soft-start output ramp timeCSS = soft-start capacitorVREF = reference voltage (0.6V typical)ISS = soft-start charging current (23µA typical)Soft-start time is adjustable from approximately 2ms to 200ms.The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.If using current share, CSS of the slave should be at least twice the CSS of the master.
13 PGOOD Power-good output. This pin is an open drain logic output that is pulled to DGND when the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin to DGND with a 10nF ceramic capacitor to mitigate SEE. If using current share, tie PGOOD of the master to PGOOD of the slave.
VOUT VREF 1 RT RB + = (EQ. 1)
tSS CSS VREF ISS= (EQ. 2)
FN8264 Rev.11.00 Page 6 of 29Jun 11, 2019
ISL70002SEH
14 ISHCOM Bidirectional communication line between a current share master and a current share slave. If using current share, tie ISHCOM of the master to ISHCOM of the slave. The master enables the slave by resistively (~ 8.5kΩ) pulling ISHCOM high. The slave indicates an overcurrent fault condition to the master by pulling ISHCOM low. To mitigate SET, connect a 47pF ceramic capacitor from ISHCOM to the PCB ground plane. If not using current share this pin should be floated or connected to the PCB ground plane. ISHCOM is tri-stated if ISHEN is low.
15 ISHSL Logic input that configures the IC as a current share master or slave. Tie this pin to DVDD to configure the IC as a current share slave. Tie this pin to the PCB ground plane to configure the IC as a current share master, or if the current share feature is not being used.
16 ISHEN Input that enables/disables the current share feature. To enable the current share feature, tie this pin to DVDD. To disable the current share feature, tie this pin to the PCB ground plane.
17 PORSEL Input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V supply, connect this pin to DVDD or PVIN. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply voltages between 5V and 3.3V, connect this pin to DGND. See additional considerations for PORSEL when using an external SYNC clock input on page 16.
18 TDO Connect this pin to the PCB ground plane.
19 TDI Connect this pin to the PCB ground plane.
20 TPGM Connect this pin to the PCB ground plane.
21 GND This pin is connected to an internal metal die trace that serves as a sensitive node noise shield. Connect this pin to the PCB ground plane.
22 SYNC When this pin is configured as an output (clock Master Mode, M/S = DVDD), it drives the SYNC input of another ISL70002SEH with a square wave that is inverted (~180° out-of-phase) from the master clock driving the master PWM circuits. When configured as an input (clock Slave Mode, M/S = DGND), this pin uses the SYNC output from another ISL70002SEH or an external clock to drive the clock slave PWM circuitry. If synchronizing to an external clock, the clock must be SEE hardened and the frequency must be within the range of 400kHz to 1.2MHz. The master configured SYNC output is active when biased.
23, 28, 32, 37, 38, 43, 44, 49, 53, 58
PVINx Power supply inputs to the corresponding internal power blocks. These pins must be connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly to PGNDx with ceramic capacitors located as close as possible to the IC. PVINx should be the same voltage as DVDD and AVDD (±200mV).
24, 27, 33, 36, 39, 42, 45, 48, 54, 57
LXx Outputs of the corresponding internal power blocks and should be connected to the output filter inductor. These pins are internally connected to the synchronous MOSFET power switches.
25, 26, 34, 35, 40, 41, 46, 47, 55, 56
PGNDx Power grounds associated with the corresponding internal power blocks. These pins also provide the ground path for the metal package lid. Connect these pins directly to the PCB ground plane. These pins should also connect to the negative terminals of the input and output capacitors. Place the input and output capacitors as close as possible to the IC.
29 M/S Clock master/slave input for selecting the direction of the bidirectional SYNC pin. For SYNC = Output (Master Mode), connect this pin to DVDD or PVIN. For SYNC = Input (Slave Mode), connect this pin to the PCB ground plane.
30 FSEL Oscillator frequency select input. Tie this pin to DVDD or PVIN to select a 1MHz nominal oscillator frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.
31, 50 31 NC, HS No Connect. These pins are not connected to anything internally. They should be connected to the PCB ground plane.
N/A 50 HS For the R64.C package (heat spreader option), this pin is connected to the heat spreader on the underside of the package. Connect this pin and/or the heat spreader to a thermal plane. This is a floating node.
Pin Descriptions (Continued)
R64.A PIN NUMBER
R64.C PIN NUMBER PIN NAME DESCRIPTION
FN8264 Rev.11.00 Page 7 of 29Jun 11, 2019
ISL70002SEH
51, 52 SC0/SC1 Inputs that comprise a 2-bit code to select the slope compensation (SC) current ramp referred to the output as shown below:SC1 = DVDD or PVIN, SC0 = DVDD or PVIN: SC = 6.6A/µs for FSEL = GNDSC1 = DVDD or PVIN, SC0 = GND: SC = 3.3A/µs for FSEL = GNDSC1 = GND, SC0 = DVDD or PVIN: SC = 1.6A/µs for FSEL = GNDSC1 = GND, SC0 = GND: SC = 0.8A/µs for FSEL = GND
SC1 = DVDD or PVIN, SC0 = DVDD or PVIN: SC= 13.4A/µs for FSEL = DVDD or PVINSC1 = DVDD or PVIN, SC0 = GND: SC = 6.7A/µs for FSEL = DVDD or PVINSC1 = GND, SC0 = DVDD or PVIN: SC = 3.4A/µs for FSEL = DVDD or PVINSC1 = GND, SC0 = GND: SC = 1.7A/µs for FSEL = DVDD or PVINIf using current share, SC0 and SC1 of the slave MUST match the master SC0 and SC1.
59 EN Enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to the PCB ground plane with a 10nF ceramic capacitor to mitigate SEE. This pin can be tied to DVDD or PVIN
60, 62 OCSSB/OCSSA
These pins set the redundant A/B peak overcurrent limit threshold during soft-start. Connect a resistor from OCSSx to OCx in accordance with the following equation:ROCSSx (kΩ) = (60 x ROCx)/[(IOCSSx x ROCx) - 60]where ROCx (kΩ) is the resistor value chosen to set the peak overcurrent limit during normal operation and IOCSSx (A) is the desired peak current limit threshold during soft-start.
61, 63 OCB/OCA These pins set the redundant A/B peak overcurrent limit threshold during normal operation. Connect a resistor from this pin to the PCB ground plane in accordance with the following equation: ROCx (kΩ) = 60/IOCwhere IOC (A) is the desired peak current limit threshold during normal operation.
64 REF Internal reference voltage output. Bypass this pin to the PCB ground plane with a 220nF ceramic capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or sinking) is available from this pin. If using current share, tie REF of the master to REF of the slave through a 10Ω resistor.
Pin Descriptions (Continued)
R64.A PIN NUMBER
R64.C PIN NUMBER PIN NAME DESCRIPTION
FN8264 Rev.11.00 Page 8 of 29Jun 11, 2019
ISL70002SEH
Absolute Maximum Ratings in a Heavy Ion Environment (Note 6)
Thermal Information
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AGND + 6.2VDVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND + 6.2VLXx, PVINx (Note 13) . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 6.2V
- up to 14A at TJ = 125°C, 12A at TJ = 150°C without Schottky Clamp Diode
LXx, PVINx (Note 13) . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 5.5V- 18A to 22A at TJ = 125°C with Schottky Clamp Diode LX to GND- 14A to 18A at TJ = 125°C without Schottky Clamp Diode
AVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . PVINx - PGNDx ± 0.3VSignal Pins (Note 11). . . . . . . . . . . . . . . . . . . . .AGND - 0.3V to AVDD + 0.3VDigital Control Pins (Note 12). . . . . . . . . . . . . DGND - 0.3V to DVDD + 0.3VPGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND + 6.2VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND + 2.5VESD Rating
Human Body Model (Tested per MIL-STD-883 TM3015) . . . . . . . . . .2kVMachine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200VCharged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . 750V
Absolute Maximum Ratings without Heavy IonsAVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AGND + 6.5VDVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND + 6.5VLXx, PVINx (Note 13) . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 6.5VAVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . PVINx - PGNDx ± 0.3VSignal Pins (Note 11). . . . . . . . . . . . . . . . . . . . .AGND - 0.3V to AVDD + 0.3VDigital Control Pins (Note 12). . . . . . . . . . . . . DGND - 0.3V to DVDD + 0.3VPGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND + 6.5VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND + 2.5V
Thermal Resistance JA (°C/W) JC (°C/W)CQFP Package R64.A (Notes 7, 9) . . . . . . . 34 1.5CQFP Package R64.C (Notes 8, 10) . . . . . . 17 0.7
Operating Junction Temperature Range . . . . . . . . . . . . . -55°C to +150°CStorage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Recommended Operating ConditionsAVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND + 3V to 5.5VDVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND + 3V to 5.5VPVINx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGNDx + 3V to 5.5VAVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . PVINx - PGNDx ± 0.1VSignal Pins (Note 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AGND to AVDDDigital Control Pins (Note 12) . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVDDREF, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally SetGND, TDI, TDO, TPGM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGNDILXx (TJ ≤ +150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.2AAmbient Temperature Range . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact productreliability and result in failures not covered by warranty.
NOTES:
6. Absolute Maximum Ratings assume operation in a heavy ion environment with LET = 86.4MeV•cm2/mg.
7. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board. See TB379 for details.
8. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
9. For JC, the “case temp” location is the center of the package underside.
10. For JC, the “case temp” location is the center of the exposed metal heat spreader on the package underside.
11. EN, FB, ISHx, ISHREFx, OCx, OCSSx, PORSEL, and REF pins.
12. FSEL, GND, ISHCOM, ISHEN, ISHRSL, M/S, SYNC, SC0, SC1, TDI, TDO, and TPGM pins.
13. The 6.2V absolute maximum rating must be met for a 20MHz bandwidth limited observation at the device pins. In addition, for a 600MHz bandwidth limited observation, the peak transient voltage on PVINx (measured to PGNDx) must be less than 7.1V with a duration above 6.2 V of less than 10ns, and the peak transient voltage on LXx (measured to PGNDx) must be less than 7.9V with a duration above 6.2 V of less than 10ns.
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = FSEL = M/S = SC0 = SC1 = 3V to 5.5V; GND = AGND = DGND = PGNDx = ISHx = ISHCOM = ISHEN = ISHREFx = ISHSL = TDI = TDO = TPGM = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V; LXx = SYNC = Open Circuit; OCx is connected to OCSSx with a 10kΩ resistor; OCx is connected to GND with a 4.99kΩ resistor shunted by a 6.8nF capacitor; PGOOD is pulled up to VIN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; TA = TJ = -55°C to +125°C; Post 100krad(Si) (Note 11)
PARAMETER TEST CONDITIONSMIN
(Note 15)TYP
(Note 14)MAX
(Note 15) UNIT
POWER SUPPLY
Operating Supply Current (Current Share Disabled)
VIN = 5.5V 70 105 mA
VIN = 3.6V 43 65 mA
Standby Supply Current(Current Share Disabled)
VIN = 5.5V, EN = GND, ISHEN = GND 2.5 6 mA
VIN = 3.6V, EN = GND, ISHEN = GND 2 4 mA
FN8264 Rev.11.00 Page 9 of 29Jun 11, 2019
ISL70002SEH
Operating Supply Current(Current Share Enabled, Current Share Master)
VIN = ISHEN = 5.5V, ISHCOM = open circuit 70 120 mA
Operating Supply Current(Current Share Enabled, Current Share Slave)
VIN = ISHEN = ISHSL = 5.5V, ISHCOM pulled to VIN with 1kΩ, M/S = GND, ISHx = ISHREFx = -100µA, SYNC = external 1MHz clock
70 120 mA
Standby Supply Current (Current Share Enabled, Current Share Slave)
VIN = ISHEN = ISHSL = 5.5V, EN = M/S = GND, SYNC = external 1MHz clock
3.0 7 mA
VIN = ISHEN = ISHSL = 5.5V, M/S = GND, SYNC = external 1MHz clock, ISHCOM = GND
7.3 11 mA
OUTPUT VOLTAGE AND CURRENT
Reference Voltage 0.594 0.6 0.606 V
Output Voltage Tolerance VOUT = 0.8V to 2.5V, IOUT = 0A to 12A (Notes 16, 17) -2 2 %
Error Amp Input Offset Voltage VIN = 5.5V, VREF = 600mV, test mode -1 3 mV
Feedback (FB) Input Leakage Current VIN = 5.5V, VFB = 600mV -1.5 1.5 µA
Sustained Output Current VIN = 3V, VOUT = 1.8V, current at which VOUT falls to 98% of set-point with OCA = OCB = PVIN (Note 18)
16 22 A
PWM CONTROL LOGIC
Internal Oscillator Tolerance FSEL = VIN or GND -15 15 %
External Oscillator Range M/S = GND 0.4 1.2 MHz
Minimum LXx On-Time VIN = 5.5V, test mode 200 275 ns
Minimum LXx Off-Time VIN = 5.5V, test mode 0 50 ns
Minimum LXx On-Time VIN = 3V, test mode 225 300 ns
Minimum LXx Off-Time VIN = 3V, test mode 0 50 ns
PORSEL, Master/Slave (M/S), SC1, SC0, ISHSL, ISHEN, FSEL Input Voltage
Input high threshold VIN -0.5 1.3 V
Input low threshold 1.2 0.5 V
PORSEL, Master/Slave (M/S), SC1, SC0, ISHSL, ISHEN, FSEL Input Leakage Current
VIN = 5.5V -1 1 µA
Synchronization (SYNC) Input Voltage Input high threshold, M/S = GND 2.3 1.7 V
Input Low Threshold, M/S = GND 1.5 1 V
Synchronization (SYNC) Input Leakage Current
VIN = 5.5V, M/S = GND, SYNC = VIN or GND -1 1 µA
Synchronization (SYNC) Output Voltage VIN - VOH at IOH = -1mA 0.1 0.4 V
VOL at IOL = 1mA 0.1 0.4 V
POWER BLOCKS
Upper Device rDS(ON) VIN = 3V, 4A load, all power blocks in parallel, test mode (Note 14)
20 40 mΩ
Lower Device rDS(ON) VIN = 3V, 4A load, all power blocks in parallel, test mode (Note 14)
15 30 mΩ
LXx Output Leakage VIN = 5.5V, EN = LXx = GND, single LXx output -1 µA
VIN = LXx = 5.5V, EN = GND, single LXx output 10 µA
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = FSEL = M/S = SC0 = SC1 = 3V to 5.5V; GND = AGND = DGND = PGNDx = ISHx = ISHCOM = ISHEN = ISHREFx = ISHSL = TDI = TDO = TPGM = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V; LXx = SYNC = Open Circuit; OCx is connected to OCSSx with a 10kΩ resistor; OCx is connected to GND with a 4.99kΩ resistor shunted by a 6.8nF capacitor; PGOOD is pulled up to VIN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; TA = TJ = -55°C to +125°C; Post 100krad(Si) (Note 11) (Continued)
PARAMETER TEST CONDITIONSMIN
(Note 15)TYP
(Note 14)MAX
(Note 15) UNIT
FN8264 Rev.11.00 Page 10 of 29Jun 11, 2019
ISL70002SEH
Dead Time (Note 17) Within a single power block or between power blocks 2.2 25 ns
Efficiency (Note 17) VIN = 3.3V, VOUT = 1.8V, IOUT = 6A, FSEL = GND 88 %
VIN = 5V, VOUT = 2.5V, IOUT = 6A 90 %
POWER-ON RESET
VIN POR Rising threshold, PORSEL = VIN 4.1 4.3 4.45 V
Hysteresis, PORSEL = VIN 225 325 425 mV
Rising threshold, PORSEL = GND 2.65 2.8 2.95 V
Hysteresis, PORSEL = GND 70 140 240 mV
Enable (EN) Input Voltage Rising/falling threshold 0.56 0.6 0.64 V
Enable (EN) Input Leakage Current VIN = 5.5V, EN = VIN or GND -3 3 µA
Enable (EN) Sink Current EN = 0.3V 6.4 11 16.6 µA
SOFT-START
Soft-Start Source Current SS = GND 20 23 27 µA
Soft-Start Discharge ON-Resistance 2.2 4.7 Ω
Soft-Start Discharge Time 256 Clock Cycles
POWER-GOOD SIGNAL
Rising Threshold VFB as a percentage of VREF, test mode 107 111 115 %
Rising Hysteresis VFB as a percentage of VREF, test mode 2 3.5 5 %
Falling Threshold VFB as a percentage of VREF, test mode 85 89 93 %
Falling Hysteresis VFB as a percentage of VREF, test mode 2 3.5 5 %
Power-Good Drive VIN = 3V, PGOOD = 0.4V, EN = GND 7.2 mA
Power-Good Leakage VIN = PGOOD = 5.5V 1 µA
PROTECTION FEATURES
Undervoltage Monitor
Undervoltage Trip Threshold VFB as a percentage of VREF, test mode 71 75 79 %
Undervoltage Recovery Threshold VFB as a percentage of VREF, test mode 84 88 92 %
Overcurrent Monitor
Overcurrent Trip Level IOCx = 60µA, test mode (Note 19) 5.35 7.35 A
IOCx = 240µA, test mode (Note 19) 23 26 A
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = FSEL = M/S = SC0 = SC1 = 3V to 5.5V; GND = AGND = DGND = PGNDx = ISHx = ISHCOM = ISHEN = ISHREFx = ISHSL = TDI = TDO = TPGM = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V; LXx = SYNC = Open Circuit; OCx is connected to OCSSx with a 10kΩ resistor; OCx is connected to GND with a 4.99kΩ resistor shunted by a 6.8nF capacitor; PGOOD is pulled up to VIN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; TA = TJ = -55°C to +125°C; Post 100krad(Si) (Note 11) (Continued)
PARAMETER TEST CONDITIONSMIN
(Note 15)TYP
(Note 14)MAX
(Note 15) UNIT
FN8264 Rev.11.00 Page 11 of 29Jun 11, 2019
ISL70002SEH
CURENT SHARE
Slave Load Current Master load current = 12A, VIN = 3.3V, VOUT = 0.8V, SC1 = ISHSL = M/S = 0, SC0 = ISHEN = FSEL = 1, SYNC = 1MHz external, 500nH inductor (Notes 17, 18)
7 12 17 A
Master load current = 12A, VIN = 3.3V, VOUT = 1.8V, SC0 = ISHSL= M/S = 0, SC1 = ISHEN = FSEL = 1, SYNC = 1MHz external, 500nH inductor (Notes 17, 18)
7 12 17 A
Master load current = 12A, VIN = 5.0V, VOUT = 1.8V, SC0 = ISHSL = M/S = 0, SC1 = ISHEN = FSEL = 1, SYNC = 1MHz external, 500nH inductor (Notes 17, 18)
7 12 17 A
Master load current = 12A, VIN = 5.0V, VOUT = 2.5V, ISHSL = M/S = 0, SC0 = SC1 = ISHEN = FSEL = 1, SYNC = 1MHz external, 500nH inductor (Notes 17, 18)
7 12 17 A
ISHx, ISHREFx, Tri-State Leakage Current VIN = 5.5V, EN = GND -1 0 1 µA
Master ISHCOM Pull-Up Resistance ISHCOM = -50µA 6.5 10 13 kΩ
Slave ISHCOM Input Leakage Current VIN = ISHSL = 5.5V -1 1 µA
Slave ISHCOM Pull-Down Resistance ISHSL = VIN, EN = GND, ISHCOM = 7.2mA 35 75 125 Ω
Slave ISHCOM Input High Voltage ISHSL = VIN 42 52 62 % of VIN
Slave ISHCOM Input Low Voltage ISHSL = VIN 26 36 46 % of VIN
Slave ISHCOM Input Voltage Hysteresis ISHSL = VIN 7 16 24 % of VIN
ISHSL Input Leakage Current -1 1 µA
ISHSL Input High Voltage VIN - 0.5 1.3 V
ISHSL Input Low Voltage 1.2 0.5 V
SLOPE COMPENSATION
SC1 = SC0 = VIN 5.9 13.4 17.7 A/µs
SC1 = VIN, SC0 = GND 3.0 6.7 8.8 A/µs
SC1 = GND, SC0 = VIN 1.5 3.4 4.5 A/µs
SC1 = SC0 = GND 0.7 1.7 2.2 A/µs
FSEL = GND, SC1 = SC0 = VIN 2.9 6.6 8.8 A/µs
FSEL = GND, SC1 = VIN, SC0 = GND 1.4 3.3 4.5 A/µs
FSEL = GND, SC1 = GND, SC0 = VIN 0.7 1.6 2.2 A/µs
FSEL = GND, SC1 = SC0 = GND 0.3 0.8 1.2 A/µs
NOTES:
14. Typical values shown reflect TA = TJ = +25°C operation and are not guaranteed.
15. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C, unless otherwise specified.
16. Limits do not include tolerance of external feedback resistors. The 0A to 12A output current range can be reduced by Minimum LXx On-time and Minimum LXx Off-time specifications.
17. Limits established by characterization or analysis and are not production tested.
18. Tested sequentially on LX2, LX6 and LX9.
19. Tested sequentially on LX2 and LX6 at 535mA to 735mA and 2.3A to 2.6A.
20. Tested in accordance with MIL-STD-883, method 1019, condition A.
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = FSEL = M/S = SC0 = SC1 = 3V to 5.5V; GND = AGND = DGND = PGNDx = ISHx = ISHCOM = ISHEN = ISHREFx = ISHSL = TDI = TDO = TPGM = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V; LXx = SYNC = Open Circuit; OCx is connected to OCSSx with a 10kΩ resistor; OCx is connected to GND with a 4.99kΩ resistor shunted by a 6.8nF capacitor; PGOOD is pulled up to VIN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF capacitor; TA = TJ = -55°C to +125°C; Post 100krad(Si) (Note 11) (Continued)
PARAMETER TEST CONDITIONSMIN
(Note 15)TYP
(Note 14)MAX
(Note 15) UNIT
FN8264 Rev.11.00 Page 12 of 29Jun 11, 2019
ISL70002SEH
Typical Performance Curves
FIGURE 6. OVERCURRENT REFERENCE VOLTAGE FIGURE 7. REF VOLTAGE vs VIN
FIGURE 8. OSC FREQUENCY vs VIN FIGURE 9. LXx MINIMUM ON-TIME vs VIN
FIGURE 10. SUSTAINED OUTPUT CURRENT WITH OVERCURRENT DISABLED
FIGURE 11. OPERATING CURRENT vs VIN
596.0
596.5
597.0
597.5
598.0
598.5
599.0
599.5
600.0
-55 -35 -15 5 25 45 65 85 105 125
OCB
OCA
TEMPERATURE (°C)
VO
LT
AG
E (
mV
)
598.0
598.5
599.0
599.5
600.0
600.5
601.0
601.5
602.0
-55 -35 -15 5 25 45 65 85 105 125
VIN = 5.5V
VIN = 3V
TEMPERATURE (°C)
VR
EF (
mV
)
900
925
950
975
1,000
1,025
1,050
-55 -35 -15 5 25 45 65 85 105 125
VIN = 5.5V
VIN = 3V
TEMPERATURE (°C)
OS
C F
RE
QU
EN
CY
(kH
z)
125
150
175
200
225
250
275
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (°C)
VIN = 3V
VIN = 5.5V
MIN
IMU
M O
N-T
IME
(n
s)
0
5
10
15
20
25
30
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (°C)
OCx DISABLED
SU
ST
AIN
ED
OU
TP
UT
CU
RR
EN
T (
A)
10
35
40
45
50
55
60
65
70
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (°C)
VIN = 5.5V
VIN = 3.6V
OP
ER
AT
ING
CU
RR
EN
T (
mA
)
FN8264 Rev.11.00 Page 13 of 29Jun 11, 2019
ISL70002SEH
Functional DescriptionThe ISL70002SEH is a monolithic, fixed frequency, current-mode synchronous buck regulator. Two ISL70002SEH devices can be used to provide a total DC/DC solution for FPGAs, CPLDs, DSPs, and CPUs.
Power BlocksThe power output stage of the regulator consists of ten power blocks that are paralleled to provide up to 18A (22A with an external Schottky diode clamp) output current capability. The block diagram in Figure 13 shows a top level view of the individual power blocks.
Each power block has a power supply input pin (PVINx), a phase output pin (LXx), and a power supply ground pin (PGNDx). All PVINx pins must be connected to a common power supply rail, and all PGNDx pins must be connected to a common ground. LXx pins should be connected to the output inductor based on the required load current, but must include the LX2, LX6, and LX9 pins. Power Blocks 2, 6, and 9 together comprise a triple redundant with majority voter configuration for the PWM control. This is included to prevent PWM control signal upsets for the internal drive circuitry in the event of SEE ion strikes. In particular applications where all LX pins are not used, LX2, LX6, and LX9 pins must be used without exception. The unused LXx pins should be left unconnected. Connecting all ten LXx pins to the output inductor provides a maximum 12A of output current at +150°C die temperature. See the “Typical Application Schematic” on page 2 for pin connection guidance.
Power Blocks 2 and 6 contain the master pilot current sensing devices, which provide current feedback. These power blocks must be connected to the output inductor. The Overcurrent Protection (OCP) is a redundant AND function of both pilot devices. This redundancy is to avoid a false OC upon an ion strike in the OCP circuitry.
Main Control LoopDuring normal operation, the internal top power switch is turned on at the beginning of each clock cycle. Current in the output inductor ramps up until the current comparator trips and turns off the top power MOSFET. Next, the bottom power MOSFET turns on, and the inductor current ramps down for the rest of the cycle.
The current comparator compares the output current at the ripple current peak to the scaled current pilot. The error amplifier monitors VOUT and compares it with an internal reference voltage. The output voltage of the error amplifier creates a proportional current to the pilot. If VOUT is low, both the current level of the pilot is increased and the trip off current level of the output is increased. The increased output current raises VOUT until it is in agreement with the reference voltage.
FIGURE 12. LX ON-RESISTANCE, ALL POWER BLOCKS IN PARALLEL, VIN = 3V
Typical Performance Curves (Continued)
0
5
10
15
20
25
30
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (°C)
NFET
PFET
ON
-RE
SIS
TA
NC
E (
mΩ
)
POWER BLOCK 10PGND10
POWER BLOCK 9
POWER BLOCK 8
POWER BLOCK 1
POWER BLOCK 2
POWER BLOCK 3
PVIN10
PGND9
PVIN9
PGND8
PVIN8
PGND1
PVIN1
PGND2
PVIN2
PGND3
PVIN3
FIGURE 13. POWER BLOCK DIAGRAM
LX2
LX1
LX3
LX10
LX9
LX8
POWER BLOCK 7
POWER BLOCK 6
POWER BLOCK 4
POWER BLOCK 5
PGND4
PVIN4
PGND5
PVIN5
LX4
LX5
PGND7
PVIN7
PGND6
PVIN6
LX7
LX6
Note: Shaded blocks indicate pilot current
PWMA and OCPA
PWMB and OCPB
PWMC
and overcurrent sensors.
FN8264 Rev.11.00 Page 14 of 29Jun 11, 2019
ISL70002SEH
Output Voltage SelectionThe output voltage of the ISL70002SEH can be adjusted using an external resistor divider as shown in Figure 14. RT should be set to 1kΩ to mitigate SEE. RT should be shunted by a 4.7nF ceramic capacitor, CC, to mitigate SEE and to improve loop stability margins. The REF pin should be bypassed to AGND with a 220nF ceramic capacitor to mitigate SEE. Note that no current (sourcing or sinking) is available from the REF pin.
RB can be determined from Equation 3. You can configure the output voltage from 0.8V to 85% of the input voltage.
The minimum on-time determines the lowest output voltage, so when VIN = 5.5V and the switching frequency is 500kHz this parameter limits the regulated output voltage to about 0.8V or greater. It increases at the 1MHz switching frequency to about 1.6V or greater. The minimum on-time increases by about 9% at VIN = 3V, but the 500kHz output voltage is not limited by the minimum on-time and the 1MHz minimum VOUT is approximately 0.9V.
Switching Frequency/SynchronizationThe ISL70002SEH features an internal oscillator running at a fixed frequency of either 500kHz or 1MHz ±15% over recommended operating conditions. When the FSEL pin is grounded, the oscillator operates at 500kHz, and if FSEL is connected to DVDD, it operates at 1MHz.
The regulator can be configured to run from the internal oscillator, can be synchronized to another ISL70002SEH, or can be synchronized to an SEE hardened external clock with a frequency range of 500kHz to 1MHz (±20%).
To run the regulator from the internal oscillator, connect the M/S pin to DVDD. In this case, the output of the internal oscillator appears on the SYNC pin. To synchronize two regulators to the SYNC output of an SEE hardened external clock (or to another ISL70002SEH regulator, see “Synchronized 2-Phase Operation”), connect the M/S pin to DGND. In this case, the SYNC pin is an input that accepts an external synchronizing signal. When M/S is connected to DGND, the ISL70002SEH is synchronized 180° out-of-phase with respect to the SYNC input of the external clock. Ideally, two or more regulators operating with individual SYNC inputs should be
operated out-of-phase and balanced to reduce input current ripple and to increase the effective switching frequency.
When using an ISL70002SEH in Slave mode and applying an external clock to SYNC (whether from a master ISL70002SEH or another external clock), it is imperative that all slave ISL70002SEH's using that external clock signal have their switching disabled through the EN input prior to any stoppage of the clock on the SYNC input. If the external clock signal on the SYNC pin stops or is otherwise removed while the slave ISL70002SEH is enabled, the internal lower FET turns on and remains on as the ISL70002SEH control circuit waits for the next rising edge of the external clock that never arrives, as shown in Figure 15. Current from the load then recirculates through the stuck-on lower FET. Figure 15 shows the SYNC stopping at a low level. If the SYNC stops at a level greater than the SYNC voltage threshold (Vth), and then decreases through the SYNC Vth, there is a solitary LX pulse.
Synchronized 2-Phase OperationThe ISL70002SEH can operate two ICs as a single 2-phase regulator with nearly twice the load current capacity. In 2-phase operation mode, a redundant current sharing bus balances the load current between the two devices and communicates any fault conditions. One ISL70002SEH is designated the master and the other the slave. The master ISHSL pin is connected to DGND and the slave ISHSL pin is connected to DVDD. The ISHEN pins on both master and slave are connected to DVDD. The SYNC, ISHA, ISHB, ISHC, ISHREFA, ISHREFB, ISHREFC, ISHCOM, and FB pins are connected from the master to the slave and the REF pins are tied with a 10Ω resistor. When configured this way, the two-phase regulator nearly doubles the load current capacity, limited only by the current share match tolerance.
In this master/slave configuration, the ISL70002SEH ICs operate 180°out-of-phase to minimize the input ripple current, effectively operating as a single IC at twice the switching frequency. The master phase uses the falling edge of the SYNC clock to initiate the master switching cycle with the nonoverlap period before the rising edge of LX, while the slave phase internally inverts the SYNC input and uses the falling edge of the inverted copy to start its switching cycle. This is independent of whether the master phase is configured for an external clock
FIGURE 14. OUTPUT VOLTAGE SELECTION
FB
COUT
LOUT VOUTLXx
RT
RBVREF
ERRORAMPLIFIER
REF
CREF
-
+
CC
VREF = 0.6VCREF = 220nFRT = 1kCC = 4.7nF
D
RS
CS
RB RT
VREFVOUT VREF–-------------------------------------= (EQ. 3)
FIGURE 15. SYNC LOSS SHOWING LX PULLED LOW
LX
VOUT
SYNC
FN8264 Rev.11.00 Page 15 of 29Jun 11, 2019
ISL70002SEH
(master M/S = DGND) or its internal clock (master M/S = DVDD). The master error amplifier and compensation controls the two-phase regulator while the slave error amplifier is disabled. The schematic in Figure 4 on page 3 shows the complete connections for the master and slave.
Often an enable signal is not provided; instead the PVIN enables the ISL70002SEH function. In a 2-phase configuration with PVIN = 5V, a method to ensure that slave switching is appropriately enabled and disabled relative to the master switching is to set the clock slave ISL70002SEH PORSEL high and clock master ISL70002SEH PORSEL low. As the PVIN voltage is ramped up, the master device is active and producing a clock out to the SYNC input of the slave device before the slave device becomes active. As the PVIN ramps down, the slave device’s switching turns off at the higher PORSEL threshold prior to the master device. This method can also be used in a dual single phase application, where the clock master ISL70002SEH is providing an out-of-phase SYNC signal to the clock slave ISL70002SEH but not current sharing. This method cannot be used in PVIN = 3.3V applications. Figure 16 illustrates the LX activity with a rising and falling PVIN with PORSEL = 1, which shows the initiation of LX switching activity at PVIN ~ 4.3V and stopping within 5µs of falling below the PORSEL falling threshold at ~4.0V. This is the expected behavior for PVIN droop times >1ms.
For PVIN = 3.3V applications, a method must be employed to prevent the lower FET from being left indefinitely in an on state to ensure the slave IC is disabled before the master IC SYNC output is halted by either a falling PVIN or a common disabling signal. In applications where the EN input pin is tied to the PVIN, adding a resistor divider on the slave EN to enable <3V, but greater than the PORSEL maximum of 2.95V is advised. This would ensure that the slave IC is enabled before PVIN = 3V on a rising PVIN and disabled prior to the master entering the POR shutdown on a falling PVIN. As the falling PVIN decreases to the slave enable falling threshold the slave device is disabled prior to the master device being disabled (see Figure 17). Notice the slave LX is tri-stated unlike in Figure 15 on page 15. If a common enable signal is used, the resistor divider on the slave IC ensures a turn-on after and a turn-off before the master IC; thus, preserving the SYNC signal integrity to the slave device and preventing the lower FET stuck in a latched on condition.
Operation InitializationThe ISL70002SEH initializes based on the state of the Power-On Reset (POR) monitor of the PVINx inputs and the state of the EN input. Successful initialization prompts a soft-start interval and the regulator begins slowly ramping the output voltage. When the commanded output voltage is within the proper window of operation, the power-good signal changes state from low-to-high, indicating proper regulator operation.
Power-On ResetThe POR circuitry prevents the controller from attempting to soft-start before sufficient bias is present at the PVINx pins.
The POR threshold of the PVINx pins is controlled by the PORSEL pin. For a nominal 5V supply voltage, PORSEL should be connected to the DVDD. For a nominal 3.3V supply voltage, PORSEL should be connected to DGND. For nominal supply voltages between 5V and 3.3V, PORSEL should be connected to DGND. The POR rising and falling thresholds are shown in the “Electrical Specifications” table on page 11.
Hysteresis between the rising and falling thresholds ensures that small perturbations on PVINx seen during regulator turn-on/turn-off do not cause the regulator to inadvertently turn off or turn on. When the PVINx pins are below the POR rising threshold, the internal synchronous power MOSFET switches are turned off, and the LXx pins are held in a high-impedance state.
Enable and Disable
After the POR input requirement is met, the ISL70002SEH remains in shutdown until the voltage at the enable input rises above the enable threshold. Figure 18 on page 17 shows that the enable circuit features a comparator type input. In addition to simple logic on/off control, the enable circuit allows the level of an external voltage to precisely gate the turn-on/turn-off of the regulator. An internal IEN current sink with a typical value of 11µA is active only when the voltage on the EN pin is below the enable threshold. The current sink pulls the EN pin low. As VCONTROL rises, the enable level is not set exclusively by the resistor divider from VCONTROL. With the current sink active, the enable level is defined by Equation 4. R1 is the resistor from the
FIGURE 16. PORSEL = 1 PVIN RAMPING AND SYNC ACTIVITY
LX
PVIN
FIGURE 17. FALLING PVIN to M/S DISABLE
PVIN
LX_M
LX_S
FN8264 Rev.11.00 Page 16 of 29Jun 11, 2019
ISL70002SEH
EN pin to VCONTROL and R2 is the resistor from the EN pin to the AGND pin.
When the voltage at the EN pin reaches the enable threshold, the IEN current sink turns off.
With the part enabled and the IEN current sink off, the disable level is set by the resistor divider. The disable level is defined by Equation 5.
The difference between the enable and disable levels provides adjustable hysteresis so that noise on VCONTROL does not interfere with the enabling or disabling of the regulator.
Bypass the EN pin to the AGND pin with a 10nF ceramic capacitor to mitigate SEE.
Soft Start
When the POR and enable circuit requirements are met, the regulator initiates a soft-start. Figure 19 shows that the soft-start circuit clamps the error amplifier reference voltage to the voltage on an external soft-start capacitor connected to the SS pin. The soft-start capacitor is charged by an internal ISS current source (23µA typical). As the soft-start capacitor is charged, the output voltage slowly ramps to the set point determined by the reference voltage and the feedback network. When the voltage on the SS pin is equal to the internal reference voltage (600mV), the soft-start interval is complete though the SS pin voltage continues to rise to approximately 1.4V. PGOOD is enabled after SS reaches 1.4V. The controlled ramp of the output voltage reduces the inrush current during start-up. The soft-start output ramp interval is defined in Equation 6 and is adjustable from approximately 2ms to 200ms. The value of the soft-start capacitor (CSS) should range from 82nF to 8.2µF, inclusive. The peak inrush current can be calculated from Equation 7. The
soft-start interval should be selected long enough to ensure that the peak inrush current plus the peak output load current does not exceed the SS overcurrent trip level of the regulator.
The soft-start capacitor is immediately discharged by a 2.2Ωresistor whenever POR conditions are not met or EN is pulled low. The soft-start discharge time is equal to 256 clock cycles.
Power-GoodThe power-good (PGOOD) pin is an open-drain logic output that indicates when the output voltage of the regulator is within regulation limits. The PGOOD pin pulls low during shutdown and remains low when the controller is enabled. After a successful soft-start, the PGOOD pin releases and the voltage rises with an external pull-up resistor. The power-good signal transitions low immediately when the EN pin is pulled low.
The power-good circuitry monitors the FB pin and compares it to the rising and falling thresholds shown in the “Electrical Specifications” table on page 11. If the feedback voltage exceeds the typical rising limit of 111% of the reference voltage, the PGOOD pin pulls low. The PGOOD pin continues to pull low until the feedback voltage falls to a typical of 107.5% of the reference voltage. If the feedback voltage drops below a typical of 89% of the reference voltage, the PGOOD pin pulls low. The PGOOD pin continues to pull low until the feedback voltage rises to a typical 92.5% of the reference voltage. The PGOOD pin then releases and signals the return of the output voltage within the power-good window.
The PGOOD pin can be pulled up to any voltage from 0V to 5.5V, independent of the supply voltage. The pull-up resistor should have
(EQ. 4)VENABLE VREF 1R1R2-------+ IEN R1+=
VDISABLE VREF 1R1R2-------+= (EQ. 5)
FIGURE 18. ENABLE CIRCUIT
-
+
VREF
EN
PVINx
VIN
PORLOGIC
VCONTROL
R1
R2
IEN
ENABLECOMPARATOR
CEN
VREF = 0.6VIEN = 11µACEN = 10nF
(EQ. 6)tSS CSS
VREFISS---------------=
(EQ. 7)IINRUSH COUT
VOUTtSS
----------------=
FIGURE 19. SOFT-START CIRCUIT
-
+VREF
FB
PWMLOGIC
ISS
ERRORAMPLIFIER
REF
CREF
VOUT
RT
RB
+
SS
CSS
VREF = 0.6VISS = 23µA
RD
RD = 2.2Ω
FN8264 Rev.11.00 Page 17 of 29Jun 11, 2019
ISL70002SEH
a nominal value from 1kΩ to 10kΩ. The PGOOD pin is bypassed to DGND with a 10nF ceramic capacitor to mitigate SEE.
Slope CompensationThe SC0 and SC1 pins select four levels of current-mode slope compensation. In current-mode buck regulators, when the duty cycle approaches and exceeds 50%, the regulator operates in sub-harmonic oscillation without slope compensation. Slope compensation is widely considered unnecessary if the duty cycle is held below 40% and provides better phase margin. Transient duty cycles must be taken into consideration when selecting the level of slope compensation. Table 1 describes the amount of effective current that is added the output power stage signal that is used in the PWM modulator.
Fault Monitoring and ProtectionThe ISL70002SEH actively monitors output voltage and current to detect fault conditions. Fault conditions trigger protective measures to prevent damage to the regulator and external load device.
Undervoltage ProtectionA hysteretic comparator monitors the FB pin of the regulator. The feedback voltage is compared to an undervoltage threshold that is a fixed percentage of the reference voltage. When the comparator trips on two consecutive switching cycles, indicating a valid undervoltage condition, the undervoltage protection logic shuts down the regulator. If the feedback voltage rises back above the undervoltage threshold plus a specified amount of hysteresis (outlined in the “Electrical Specifications” table on page 11) after the first detection and before the second, normal operation continues.
After the regulator shuts down, it enters a delay interval, equivalent to the selected soft-start interval. The undervoltage counter is reset entering the delay interval. The protection logic initiates a normal soft-start when the delay interval ends. If the output successfully soft-starts, the power-good signal goes high and normal operation continues. If undervoltage conditions continue to exist during the soft-start interval, the undervoltage counter must overflow before the regulator shuts down again. This hiccup mode continues indefinitely until the output soft-starts successfully.
Overcurrent ProtectionPilot devices integrated into the PMOS transistor of power block 2 and power block 6 sample the inductor current of each cycle. This current feedback is scaled and compared to an overcurrent (OC) threshold based on the overcurrent resistor connected from OCx to AGND. The Overcurrent Protection (OCP) is a redundant AND function of both pilot devices. This redundancy is to avoid a false OC upon an ion strike in the OCP circuitry.
If the sampled current exceeds the overcurrent threshold, an overcurrent counter increments. If the sampled current falls below the threshold before the counter overflows, the counter is reset. When the overcurrent counter reaches 2, the regulator shuts down.
After the regulator shuts down, it enters a delay interval equivalent to the soft-start interval, which allows the device to cool. The overcurrent counter is reset entering the delay interval. The protection logic initiates a normal soft-start when the delay interval ends. If the output successfully soft-starts, the power-good signal goes high and normal operation continues. If overcurrent conditions continue to exist during the soft-start interval, the overcurrent counter must overflow before the regulator shut downs the output again. This hiccup mode continues indefinitely until the output soft-starts successfully.
Component Selection GuideThis design guide provides a high-level explanation of the steps necessary to create a power converter. It is assumed the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Renesas provides an evaluation board, schematic, Bill of Materials (BOM), and an example PCB layout.
Output Filter DesignThe output inductor and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase node. The filter must also provide the transient energy until the regulator can respond. Because the filter has low bandwidth relative to the switching frequency, it limits the system transient response. The output capacitors must supply or sink current while the current in the output inductor increases or decreases to meet the load demand.
OUTPUT CAPACITOR SELECTIONThe critical load parameters in choosing the output capacitors are the maximum size of the load step (ISTEP), the load-current slew rate (di/dt), and the maximum allowable output voltage deviation under transient loading (VMAX). Capacitors are characterized according to their capacitance, ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance).
At the beginning of a load transient, the output capacitors supply all of the transient current. The output voltage initially deviates by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount shown in Equation 8.
TABLE 1. SLOPE COMPENSATION
FSEL SC1 SC0SLOPE COMPENSATION
(A/µs)
DGND DGND DGND 0.8
DGND DGND DVDD 1.6
DGND DVDD DGND 3.3
DGND DVDD DVDD 6.6
DVDD DGND DGND 1.7
DVDD DGND DVDD 3.4
DVDD DVDD DGND 6.7
DVDD DVDD DVDD 13.4
VMAX ESLdidt----- ESR ISTEP + (EQ. 8)
FN8264 Rev.11.00 Page 18 of 29Jun 11, 2019
ISL70002SEH
The filter capacitors selected must have sufficiently low ESL and ESR so that the total output voltage deviation is less than the maximum allowable ripple.
Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but larger ESR. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation.
Ceramic capacitors with an X7R dielectric are recommended. Alternately, a combination of low ESR solid tantalum capacitors and ceramic capacitors with an X7R dielectric can be used.
The ESR of the bulk capacitors is responsible for most of the output voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current, a voltage, VP-P(MAX), develops across the bulk capacitor according to Equation 9.
OUTPUT INDUCTOR SELECTIONWhen the output capacitors are selected, the maximum allowable ripple voltage, VP-P(MAX), determines the lower limit on the inductance as shown in Equation 10.
Because the output capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductor must be capable of assuming the entire load current before the output voltage decreases more than VMAX. This places an upper limit on inductance.
Equation 11 gives the upper limit on output inductance for the case when the trailing edge of the current transient causes the greater output voltage deviation than the leading edge.
Equation 12 addresses the leading edge. Normally, the trailing edge controls the inductance selection because duty cycles are usually <50%. However, both inequalities should be evaluated, and inductance should be governed based on the lower of the two results. In each equation, LOUT is the output inductance, COUT is the total output capacitance, and IL(P-P) is the peak-to-peak ripple current in the output inductor.
The other concern when selecting an output inductor is to ensure there is adequate slope compensation when the regulator is operated above 40% duty cycle. In most cases, the maximum
slope compensation setting (SC1 = DVDD, SC0 = DVDD) provides sufficient phase margin, so this is the recommended configuration.
Input Capacitor SelectionInput capacitors are responsible for sourcing the AC component of the input current flowing into the switching power devices. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the switching power devices, which is related to duty cycle. The maximum RMS current required by the regulator is closely approximated by Equation 13.
The important parameters to consider when selecting an input capacitor are the voltage rating and the RMS ripple current rating. For reliable operation, select capacitors with voltage ratings at least 1.5 times greater than the maximum input voltage. The capacitor RMS ripple current rating should be higher than the largest RMS ripple current required by the circuit.
A combination of low ESR tantalum capacitors and ceramic capacitors with an X7R dielectric are recommended. The ISL70002SEH requires a minimum effective input capacitance of 100µF for stable operation.
PCB DesignPCB design is critical to high-frequency switching regulator performance. Careful component placement and trace routing are necessary to reduce voltage spikes and minimize undesirable voltage drops. Select a suitable thermal interface material for optimum heat dissipation and to provide lead strain relief.
PCB Plane AllocationFour layers of 2-oz. copper are recommended. Layer 2 should be a dedicated ground plane with all critical component ground connections made with vias to this layer. Layer 3 should be a dedicated power plane split between the input and output power rails. Layers 1 and 4 should be used primarily for signals, but can also provide additional power and ground islands as required.
PCB Component PlacementPlace components as close as possible to the IC to minimize stray inductance and resistance. Prioritize the placement of bypass capacitors on the pins of the IC in the following order: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors), EN, PGOOD, PVINx (bulk capacitors).
Locate the output voltage resistive divider as close as possible to the FB pin of the IC. Connect the top leg of the divider directly to the POL (Point of Load) and the bottom leg of the divider directly to AGND. Connect the junction of the resistive divider directly to the FB pin.
A small series RC snubber connected from the LXx pins to the PGNDx pins can be used to damp high frequency ringing on the LXx pins if desired.
VP-P(MAX) ESRVIN VOUT– VOUTLOUT fs VIN
-----------------------------------------------------= (EQ. 9)
LOUT ESRVIN VOUT– VOUT
fs VIN VP-P(MAX)------------------------------------------------------ (EQ. 10)
LOUT
2 COUT VOUT
ISTEP 2-------------------------------------------- VMAX IL(P-P) ESR – (EQ. 11)
LOUT
2 COUT
ISTEP 2----------------------------- VMAX IL(P-P) ESR – VIN VOUT–
(EQ. 12)
IRMS IOUT
VOUTVIN
----------------- 1 13---+
VIN VOUT–
IOUT LOUT
fs----------------------------------------------------
VOUTVIN
----------------- 2
=
(EQ. 13)
FN8264 Rev.11.00 Page 19 of 29Jun 11, 2019
ISL70002SEH
PCB Layout Use a small island of copper to connect the LXx pins of the IC to the output inductor on layers 1 and 4. To minimize capacitive coupling to the power and ground planes, void the copper on layers 2 and 3 adjacent to the island. Place most of the island of layer 4 to minimize the amount of copper that must be voided from the ground plane (layer 2).
Keep all other signal traces as short as possible. For an example layout, see AN1732.
Schottky Diode Clamp and RC SnubberImplement the Schottky diode clamp at the LX node to GND as close as possible to the IC when output current is 18A or greater per phase. A diode rated for an average forward current of 3A at the maximum operating temperature is adequate.
The diode shunts current at the switching transient edges to reduce the Si die temperature approximately 22% more at an output current level of 18A than without the diode in place. It is imperative to implement adequate thermal relief in the hardware design, as the Si temp is ~135°C at an output current level of 24A with the diode clamp in place at a room ambient.
A small series RC snubber connected from the LXx pins to the PGNDx pins can be used to damp high-frequency ringing on the LXx pins. See Figure 14 on page 15.
Thermal Management for Ceramic PackageFor optimum thermal performance, place a pattern of vias on the top layer of the PCB directly underneath the IC. Connect the vias to the plane that serves as a heat spreader. To ensure good thermal contact, use thermal interface material such as a Sil-Pad or thermally conductive epoxy to fill the gap between the vias and the bottom of the IC of the ceramic package.
Lead Strain ReliefBecause the package leads protrude from the bottom of the package, the leads need forming to provide strain relief. On the ceramic bottom package R64.A, the Sil-pad or epoxy can be used to fill the gap left between the PCB board and the bottom of the package when lead forming is completed. On the heat spreader option of the package R64.C, the formed leads should be flush.
Heat Spreader Mounting GuidelinesThe R64.C package option has a heat spreader mounted on the underside of the package. Use the following JESD-51x series guidelines to mount the package:
• Place a thermal land on the PCB under the heat spreader.
• The land should be approximately the same size as to 1mm larger than the 10.16x10.16mm heat spreader.
• Place an array of thermal vias below the thermal land.
- Via array size: ~9x9 = 81 thermal vias.
- Via diameter: ~0.3mm drill diameter with plated copper on the inside of each via.
- Via pitch: ~1.2mm.
- Vias should drop to and contact as much buried metal area as feasible to provide the best thermal relief.
Heat Spreader Electrical PotentialThe heat spreader is connected to Pin 50 within the package; therefore, the PCB design and potential applied to Pin 50 define the heat spreader potential. If unconnected, the heat spreader is a floating node.
Heat Spreader Mounting MaterialsWhen using electrically conductive mounting methods (conductive epoxy, solder, etc) the thermal land, vias, and connected plane(s) below must be the same potential as Pin 50.
When using electrically nonconductive mounting methods (nonconductive epoxy), the heat spreader and Pin 50 can have a different electrical potential than the thermal land, vias, and connected plane(s) shown in the following layout.
FN8264 Rev.11.00 Page 20 of 29Jun 11, 2019
ISL70002SEH
Weight CharacteristicsWeight of Packaged Device
1.43g typical - R64.A Package
2.65g typical - R64.C Package
Die CharacteristicsDie Dimensions
8300µmx8300µm (327 mils x 327 mils)Thickness: 300µm ±25.4µm (12 mils ±1 mil)
Interface Materials
GLASSIVATIONType: Silicon oxide and Silicon nitrideThickness: 0.3µm ±0.03µm and 1.2µm ±0.12µm
TOP METALLIZATIONType: AlCu (0.5%)Thickness: 2.7µm ±0.4µm
SUBSTRATEType: SiliconIsolation: Junction
BACKSIDE FINISH Silicon
ASSEMBLY RELATED INFORMATION
Substrate and Metal Lid Potential
PGND
Heat Spreader Potential R64.C Package
Connected to Pin 50, electrically isolated
ADDITIONAL INFORMATION
Worst Case Current Density
<2 x 105 A/cm2
Transistor Count
28,160
Layout CharacteristicsStep and Repeat
8300µmx8300µm
FN8264 Rev.11.00 Page 21 of 29Jun 11, 2019
ISL70002SEH
Metallization Mask LayoutISL70002SEH
FB
ISHA
ISHREFA
ISHB
ISHREFB
ISHC
ISHREFC
AVDD
AGND
DGND
DVDD
SS
PGOOD
ISHCOM
ISHSL
ISHEN
PORSEL
TD
O
TD
I
TP
GM
GN
D
SY
NC
M/S
FS
EL
PV
IN1
0
PV
IN9
SC
0
SC
1
EN
OC
SS
B
OC
B
OC
SS
A
OC
A
RE
F
LX
10
PG
ND
10
LX
9P
GN
D9
PVIN8LX8PGND8
PVIN6LX6PGND6
PVIN7LX7PGND7
PVIN4LX4PGND4
PVIN5LX5PGND5
PVIN3LX3PGND3
PV
IN2
LX
2P
GN
D2
PV
IN1
LX
1P
GN
D1
PVI
N3
LX3
PG
ND
3
PVI
N8
LX8
PG
ND
8
ORIGIN (0,0)
PAD 48
TABLE 2. LAYOUT X-Y COORDINATES
PAD NAME PAD NUMBERX
(µm)Y
(µm)dX
(µm)dY
(µm)BOND WIRES SIZE (0.001”)
FB 1 275 7497 135 135 1.5
ISHA 2 275 7117 135 135 1.5
ISHREFA 3 275 6737 135 135 1.5
ISHB 4 275 6357 135 135 1.5
ISHREFB 5 275 5977 135 135 1.5
ISHC 6 275 5597 135 135 1.5
ISHREFC 7 275 5217 135 135 1.5
AVDD 8 335 4672 254 254 3
AGND 9 335 3972 254 254 3
DGND 10 335 3272 254 254 3
DVDD 11 335 2572 254 254 3
SS 12 275 2021 135 134 1.5
PGOOD 13 275 1671 135 135 1.5
ISHCOM 14 275 1321 135 135 1.5
FN8264 Rev.11.00 Page 22 of 29Jun 11, 2019
ISL70002SEH
ISHSL 15 275 971 135 135 1.5
ISHEN 16 275 621 135 135 1.5
PORSEL 17 275 275 135 135 1.5
TDO 18 635 275 135 135 1.5
TDI 19 995 275 135 135 1.5
TPGM 20 1355 275 135 135 1.5
GND 21 1715 275 135 135 1.5
SYNC 22 2075 275 135 135 1.5
M/S 23 2435 275 135 135 1.5
FSEL 24 2795 275 135 135 1.5
PVIN10 25 3463 336 254 254 3
LX10 26 3693 1222 254 254 3
PGND10 27 3905 2074 254 254 3
PGND9 28 5281 2074 254 254 3
LX9 29 5494 1222 254 254 3
PVIN9 30 5723 336 254 254 3
PGND8 31 6115 778 254 254 3
LX8 32 6967 566 254 254 3
PVIN8 33 7853 336 254 254 3
PGND7 34 6115 2154 254 254 3
LX7 35 6967 2366 254 254 3
PVIN7 36 7853 2596 254 254 3
PVIN6 37 7853 2965 254 254 3
LX6 38 6967 3195 254 254 3
PGND6 39 6115 3408 254 254 3
PGND5 40 6115 4784 254 254 3
LX5 41 6967 4996 254 254 3
PVIN5 42 7853 5226 254 254 3
PVIN4 43 7853 5595 254 254 3
LX4 44 6967 5825 254 254 3
PGND4 45 6115 6037 254 254 3
PGND3 46 6115 7413 254 254 3
LX3 47 6967 7625 254 254 3
PVIN3 48 7853 7855 254 254 3
PVIN2 49 5723 7855 254 254 3
LX2 50 5494 6969 254 254 3
PGND2 51 5281 6117 254 254 3
PGND1 52 3905 6117 254 254 3
LX1 53 3693 6969 254 254 3
TABLE 2. LAYOUT X-Y COORDINATES (Continued)
PAD NAME PAD NUMBERX
(µm)Y
(µm)dX
(µm)dY
(µm)BOND WIRES SIZE (0.001”)
FN8264 Rev.11.00 Page 23 of 29Jun 11, 2019
ISL70002SEH
PVIN1 54 3463 7855 254 254 3
SC0 55 2836 7914 135 135 1.5
SC1 56 2476 7914 135 135 1.5
EN 57 2116 7914 135 135 1.5
OCSSB 58 1756 7914 135 135 1.5
OCB 59 1396 7914 135 135 1.5
OCSSA 60 1036 7914 135 135 1.5
OCA 61 676 7914 135 135 1.5
REF 62 316 7914 135 135 1.5
TABLE 2. LAYOUT X-Y COORDINATES (Continued)
PAD NAME PAD NUMBERX
(µm)Y
(µm)dX
(µm)dY
(µm)BOND WIRES SIZE (0.001”)
FN8264 Rev.11.00 Page 24 of 29Jun 11, 2019
ISL70002SEH
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision.
DATE REVISION CHANGE
Jun 11, 2019 FN8264.11 Updated Figure 1.Updated Power Blocks section.Updated Synchronized 2-Phase Operation section.Updated Overcurrent Protection section.
Apr 5, 2019 FN8264.10 Updated links throughout document.Updated Features section.Updated Figure 4 on page 3.Added last paragraph in the “Switching Frequency/Synchronization” and “Synchronized 2-Phase Operation” sections.Added Figure 15 in the “Switching Frequency/Synchronization” section.Updated Disclaimer
May 31, 2018 FN8264.9 Applied new Header/Footer.Updated Related Literature section.Added ISL70002SEHDEMO1Z to Ordering Information Table on page 4Added ESD ratings (Human Body Model, Charged Device Model, and Machine Model) to Absolute Maximum Ratings on page 10. Updated Figure 1 on page 2.Clarified the Maximum Output Current constraints and recommendations on page 1 and in the Absolute Maximum Ratings on page 10.Added test condition clarification for Output Sustained Current on page 11.Added Schottky Diode Clamp and Snubber section on page 20.Removed About Intersil section and updated disclaimer.
Oct 1, 2015 FN8264.8 On page 20 in “Metallization Mask Layout”, clarified pad labels for PVIN3, LX8, PGND3, PVIN8, LX8, PGND8.Corrected XY coordinates for PVIN3, PGND3, PVIN8, PGND8 in Table 2 on page 22.
Oct 9, 2014 FN8264.7 On “EFFICIENCY 5V INPUT, 500kHz, Tcase = +25°C” on page 1: changed Figure 1 to reflect latest testing results.Pin descriptions on page 8: Clarified pin descriptions for pins 60 through 63.Figures 3 and 4 on pages 7 and 8 corrected pin numbers for PVINx, LXx AND PGNDx.
Jul 11, 2014 FN8264.6 Absolute Maximum Ratings on page 9: updated Heading by adding "Ratings in a Heavy Ion Environment".Absolute Maximum Ratings on page 9: added: Absolute Maximum Ratings without Heavy Ions values to the table section.
May 20, 2014 FN8264.5 Page 1: Added Related Literature, Updated bullets under Features section as below:• From “12A output current for a single device (at TJ = +150°C)” to “Output current for a single device 14A at
TJ = +125°C; 12A at TJ = +150°C”
• From “• 14A output current for a single device (at TJ = +125°C) • 19A output current for two paralleled devices” to “Output current for two paralleled devices 22A at TJ = +125°C; 19A at TJ = +150°C”
Feb 11, 2014 FN8264.4 On page 5 modified the pin configuration diagram to explicitly identify PIN 1.Updated POD R64.A from Rev 4 to Rev 5 to show larger corner chamfer in pin #16/17 corner.Updated POD R64.C from Rev 0 to Rev 1 to show larger corner chamfer in pin #16/17 corner.“Switching Frequency and Synchronization” on page 15 - Added text to third paragraph.
Jul 12, 2013 FN8264.3 On page 5 modified the pin configuration, and changed note from indicates changes heat spreader package R64.C to indicates heat spreader package R64.C.On page 6 modified pin 50 description from:...”the heat spreader to the power plane which offers the best thermal relief”, to....”the heat spreader to a thermal plane”.Made correction to Equations in pin description table on page 8 matching SMD for pins 60, 62 and 61, 63.
Jun 10, 2013 FN8264.2 On page 1: Added bullet, “14A output current for a single device (at TJ = +125°C)” to Feature list.Ordering information table on page 5: Added new part number ISL70002SEHVFE and ISL70002SEHFE/PROTO.Thermal Information table on page 9: Added CQFP Package R64.C JA17, JC0.7.Ordering information table on page 5: Added R46.C package outline drawing.Added POD “R46.C” to datasheet.
May 7, 2013 FN8264.1 Added the heat spreader package option to the ordering table. Also added mounting guidelines, electrical potential and mounting material sections to the datasheet.
FN8264 Rev.11.00 Page 25 of 29Jun 11, 2019
ISL70002SEH
Mar 30, 2012 FN8264.1 Figure 2 on page 1changed “Slave” to “Master” to CH1 and added “at 86.4MeV/mg/cm2" to Figure Title.“” on page 17 changed in 2nd to last sentence “...range from 8.2nF...” to “...range from 82nF...”“LAYOUT X-Y COORDINATES” on page 22 changed in Bond Wires column for “ISHB” from “1.51” to “1.5”
Mar 27, 2012 FN8264.0 Initial Release
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. (Continued)
DATE REVISION CHANGE
FN8264 Rev.11.00 Page 26 of 29Jun 11, 2019
ISL70002SEH
Package Outline DrawingsR64.A64 CERAMIC QUAD FLATPACK PACKAGE (CQFP) Rev 5, 10/13
TOP VIEW
SIDE VIEW
NOTE:
1. All dimensions are in inches (millimeters).
DETAIL “A”
BOTTOM VIEW
49
32
16
17
1
64
33
48
0.567 (14.40)0.547 (13.90)
1.118 (28.40)1.080 (27.43)
0.025 (0.635) BSC
0.006 (0.15)0.010 (0.25)
0.290 (7.37)
0.255 (6.48)
INDEX AREAPIN 1
0.547 (13.90)0.567 (14.40)1.118 (28.40)
1.080 (27.43)
0.005 (0.125)0.0075 (0.188)
0.105 (2.67)
0.075 (1.91)
SEE DETAIL "A"
0.008 (0.20) REF
64
1
0.100 (2.537)0.085 (2.157)0.370 (9.395)
0.380 (9.655)
PIN 1INDEX AREA
For the most recent package outline drawing, see R64.A.
FN8264 Rev.11.00 Page 27 of 29Jun 11, 2019
ISL70002SEH
R64.C64 CERAMIC QUAD FLATPACK PACKAGE (CQFP) WITH BOTTOM HEAT SPREADERRev 1, 10/13
NOTES:1. All dimensions are in inches (millimeters)
2. Dimension shall be measured at point of exit
49
32
16
17
1
64
33
48
64
1
0.567 (14.40)0.547 (13.90)
1.118 (28.40)1.080 (27.43)
0.025 (0.635) BSC
0.006 (0.15)0.010 (0.25)
0.290 (7.37)
0.255 (6.48)
INDEX AREAPIN 1
TOP VIEW
SIDE VIEW0.005 (0.125)0.0075 (0.188)
HEAT SPREADER
0.135 (3.43)0.111 (2.82)
0.547 (13.90)0.567 (14.40)1.118 (28.40)
1.080 (27.43)
SEE DETAIL "A"
DETAIL "A"
0.026 (0.66) MIN. 2
0.048 (1.22)REF
0.395 (10.03)
0.405 (10.29)
0.405 (10.29)0.395 (10.03)
0.100 (2.537)
0.085 (2.157)0.370 (9.395)0.380 (9.655)
PIN 1INDEX AREA
0.008 (0.20) REF
HEAT SPREADER
BOTTOM VIEW (beyond the meniscus) of the lead from the body.
For the most recent package outline drawing, see R64.C.
FN8264 Rev.11.00 Page 28 of 29Jun 11, 2019
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