Available online at www.sciencedirect.com

H O S T E D B Y

Digital Communications and Networks (2015) 1, 45–56

http://dx.doi.org/12352-8648/& 2015 Carticle under the CC

nCorresponding auE-mail addresses

kikkawat@hiroshima1Yi conducted thisPeer review under

journal homepage: www.elsevier.com/locate/dcan

IðReÞ2-WiNoC: Exploring scalable wirelesson-chip micronetworks for heterogeneousembedded many-core SoCs

Dan Zhaoa,n, Yi Wangb,1, Hongyi Wua, Takamaro Kikkawac

aThe Center for Advanced Computer Studies, University of Louisiana at Lafayette, USAbXingtera US, USAcResearch Center for Nanodevices and Systems, Hiroshima University, Japan

Received 25 November 2014; accepted 24 January 2015Available online 19 March 2015

KEYWORDSNetwork-on-Chip;RF interconnect;Topology design;Routing algorithm;Microarchitecturedesign

0.1016/j.dcan.201hongqing UniversiBY-NC-ND license

thor.: dzhao@cacs.loui-u.ac.jp (T. Kikkawwork during his Presponsibility of

AbstractModern embedded SoC design uses a rapidly increasing number of processing units forubiquitous computing, forming the so-called embedded many-core SoCs (McSoC). Such McSoCdevices allow superior performance gains while side-stepping the power and heat dissipationlimitations of clock frequency scaling. The main advantage lies in the exploitation ofparallelism, distributively and massively. Consequently, the on-chip communication fabricbecomes the performance determinant. To bridge the widening gap between computationrequirements and communication efficiency faced by gigascale McSoCs in the upcoming billion-transistor era, a new on-chip communication system, dubbed Wireless Network-on-Chip(WiNoC), has been proposed by using the recently developed RF interconnect technology. Withthe high data-rate, low power and ultra-short range interconnection provided by UWBtechnology, the WiNoC design paradigm calls for effective solutions to overhaul the on-chipcommunication infrastructure of gigascale McSoCs.In this work, an irregular and reconfigurable WiNoC platform is proposed to tackle everincreasing complexity, density and heterogeneity challenges. A flexible RF infrastructure isestablished where RF nodes are properly distributed and IP cores are clustered. Consequently, aperformance-cost effective topology is formed. A region-aided routing scheme is furtherdeigned and implemented to realize loop-free, minimum path cost and high scalability forirregular WiNoC infrastructure. To implement the data transmission protocol, the RF micro-architecture of WiNoC is developed where the RF nodes are designed to fulfill the functions of

5.01.003ty of Posts and Telecommunications. Production and Hosting by Elsevier B.V. This is an open access(http://creativecommons.org/licenses/by-nc-nd/4.0/).

siana.edu (D. Zhao), yi@xingtera.com (Y. Wang), wu@cacs.louisiana.edu (H. Wu),a).h.D. study at University of Louisiana at Lafayette.Chongqing University of Posts and Telecommunications.

D. Zhao et al.46

distributed table routing, multi-channel arbitration, virtual output queuing, and distributedflow control. Our simulation studies based on synthetic traffics demonstrate the networkefficiency and scalability of WiNoC.& 2015 Chongqing University of Posts and Telecommunications. Production and Hosting by Elsevier B.V.

This is an open access article under the CC BY-NC-ND license(http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction

Ubiquitous embedded computing is playing a key role todrive the technological evolution in the near future.System-on-chip (SoC) design has become a cost-effectiveapproach for embedded systems to integrate a number ofheterogeneous IP cores, such as processors, DSPs, GPUs,FPGA modules and embedded memories. With continuedscaling of microelectronics, future SoC devices may utilizeseveral hundreds or even a thousand of processors yieldingthe so-called many-core SoCs (McSoC). Such nanoscaleintegrated many-core platforms pave the way to theubiquitous era to accomplish such applications as mobileimage/video processing, advanced driver assistance systemsand other software intensive embedded systems e.g.,cyber-physical systems. On one hand, orders of magnitudegains in price/performance, power and form factor effi-ciency can be realized using this emerging technology. Onthe other hand, ever increasing complexity, heterogeneity,performance, and productivity, put a heavy burden on thenext-generation McSoC designs. The performance of McSoCswill be limited by the ability to efficiently interconnectheterogeneous IP cores to accommodate their communica-tion requirements.

A scalable, cost-efficient, flexible and reusable on-chipcommunication infrastructure is becoming an enablingtechnology for this McSoC paradigm. The state-of-the-artshared-bus and point-to-point connections have been shownunable to supply nanoscale SoCs with both sufficient band-width and low latency under a stringent power consumptionlimitation [1]. Network-on-Chips (NoC) are emerging as analternative communication platform for complex McSoCs toprovide plug-n-play interconnection of heterogeneous IPcores. In the meantime, the speed improvements of siliconand SiGe bipolar transistors and MOS transistors have madethe implementation of integrated circuits operating atultrahigh frequency feasible. Consequently, it becomespossible to build RF circuits operating at 90 GHz with acutoff frequency of 280 GHz at the 50 nm CMOS node [2]. Infact, a 900 μm monopole antenna on a high resistivitysubstrate has been proposed for 100 GHz intra-chip applica-tions [3]. As CMOS and BiCMOS technologies improve, thecost of building on-chip antenna and radio frequency (RF)circuits will decrease dramatically, providing a greaterfreedom to use on-chip radios. As a result, a new RF/wireless interconnect technology has been investigated forfuture intra-/inter-chip communication, such as free-spacetransmission [4], guided-wave transmission [5,6], ultrawideband (UWB) [7,8] and direct near-field coupling [9].

Among them, the UWB interconnect (UWB-I) technology isintroduced for high-data rate, low-power and short-rangecommunication. Given its ultra-short transmission range and

the isolated communication environment, an extremelywide spectrum is available, leading to great potential ofachieving supereminent data rate, ranging from 150 Gbps to1.5 Tbps [10]. Based on UWB-I, the chip-based wirelessradios can be deployed to replace the wires for increasingaccessibility, improving bandwidth utilization, and eliminatingdelay and cross-talk noise in conventional wired interconnects.A revolutionary on-chip communication infrastructure, namelywireless network-on-chip (WiNoC) is thereby established forthe communication among highly integrated heterogeneous IPcores with diverse functionalities, sizes and communicationrequirements in the nanoscale McSoCs [11]. WiNoC willprovide higher flexibility, higher bandwidth, reconfigurableintegration, and freed-up wiring when compared to NoC. Withthe uniqueness of UWB-I, the system architecture and datatransmission protocol of WiNoC must adapt to the criticalchallenges posed by both large scale integration and smalldevice geometries. The major contributions of this papercenter on:

�

Provide an insightful discussion of current state-of-the-art UWB-I technology and its recent technical advancesand design impacts on many-core on-chip communication(Section 2).

�

Present the design of application-specific communica-tion infrastructure of WiNoC, specifically the RF nodeplacement and core clustering to establish an irregularand reconfigurable wireless on-chip micronetwork(Section 4).

�

Propose a hardware efficient region-aided routingscheme for loop-free shortest path multiple hop routingaiming at developing simple and compact protocolarchitecture for micro-scale communications (Section 5).

�

Develop a RF node microarchitecture integrated withvarious mechanisms of region-aided routing, QoS enabledmulti-channel arbitration, deadlock avoidant virtualoutput-queuing and contention-aware flow control tofacilitate system implementation and performancedemonstration (Section 6).

2. On-chip ultra wideband interconnect

RF/wireless interconnect technology has emerged over thelast few years to address future global routing needs andprovide performance improvement [6,7,12]. Among them,the introduction of Ultra-Wideband Interconnect (UWB-I)brings in new opportunity for low-power, short-range com-munication, thanks to its low-cost on-chip implementation,ultra-wide frequency band, and ultra-high data rate.

47I(Re)2-WiNoC: Exploring scalable wireless on-chip micronetworks for heterogeneous embedded many-core SoCs

The UWB-I is based on transverse electromagnetic wavepropagation with the use of on-chip antennas. Since itssignal has very short pulse duration, high data rate (C) withconstant signal-to-noise ratio (S=N) is achieved by increas-ing the bandwidth (B), following Shannon's capacityequation (C¼ B log2ð1þS=NÞ). It consumes low power inthe range of a few milliwatts due to its very low duty cycle(typically o0:1%). RF circuits can also be simpler since UWBsignals are carrier free. Furthermore, pulse position mod-ulation is typically used to modulate a sequence of verysharp Gaussian monocycle pulses. Each individual pulse isdelayed in time depending on the data signal and thepseudo-random code (time-hopping sequence) assigned tothe transmitter. Therefore, N “channels” are separated tosupport N users, which simultaneously communicate withtheir corresponding receivers on the same frequency band.The received signal and the template signal are automati-cally correlated during the demodulation of multiple accesssuch as time hopping. Meanwhile, CMOS-integrated anten-nas such as various dipole antennas have been proposed foron-chip implementation.

One of the recent implementations of on-chip UWB-I as inTable 1 has achieved 1.16 Gbps data rate for single band atcentral frequency of 3.6 GHz in 0.18 μm CMOS technology[13,14]. A Si-integrated meander type dipole antenna hasbeen implemented for 1 mm range data transmission atantenna area of 2.98� 0.45 mm2. The area overhead for thetransceiver design is 0:64 mm2. A 56 GHz architecture isdescribed in [12] to enable inter-chip communications atgreater than 10 Gbps. The system employs a self-lockingreceive section which attains 6.4 pJ/bit efficiencies in40 nm CMOS.

Tab. 1 UWB interconnect in 0.18 μm CMOS.

Technology node 0.18 μm CMOS

Transmitter Power 21.6 mW Area 0.1 mm2

Receiver Power 40 mW Area 0.54 mm2

Modulation On–off keying (OOK)Data rate 1.16 Gbps (single channel)GMP centralfrequency

3.6 GHz

Supply voltage 1.8 VAntenna type Meander type dipoleAntenna Area 1.8 mm2 Distance 1 mmWireless channel Additive white Gaussian noise

(AWGN)

Tab. 2 UWB interconnect scaling.

Technology (nm) 90 6Cut-off frequency (GHz) 105 1Data rate per band (Gbps) 5.25Dipole antenna length (mm) 8.28Meander type antenna area (mm2) 0.738Power (mW) 33Energy per bit (pJ) 6

According to ITRS [2], the cut-off frequency (fT) and unitymaximum power gain frequency (fmax) are projected to beat 400 GHz and 580 GHz respectively. As the maximumoperating frequency of RF CMOS circuits increases withtechnology scaling, it is possible to implement RF circuitsoperating at �20 GHz, achieving a data rate of �20 Gbps(with the typical 1 bps/Hz bandwidth efficiency) in 32 nmtechnology. With multiple bands, the aggregate data ratecan be further improved to above 1 Tbps. The characteristicantenna dimensions are proportional to the operationwavelength. Migration of short-range wireless communica-tion to higher frequency allows smaller antennae and thusfacilitates their on-chip integration. With such scaling, therequired antenna and circuit areas will scale down. Forexample, at 400 GHz, the meander type dipole antennaewill be only about 0.19 mm2 in silicon, dramatically redu-cing the cost and increasing the flexibility of on-chipwireless interconnects. Moreover, the energy consumptionper bit is expected to scale down too. As the technologynode scales, UWB-I shows prominent scaling capability andits scaling trend is summarized in Table 2.

3. Architectural overview of WiNoC

Based on the UWB-I technology, a WiNoC platform isestablished for the communication among highly integratedheterogeneous IP cores with diverse functionalities, sizesand communication requirements in the nanoscale McSoCs.A WiNoC system architecture consists of two basic compo-nents, transparent network interfaces (TNI) and radiofrequency (RF) nodes [11] as shown in Fig. 1. TNI serves asthe interface between the IP cores and the WiNoC. Each TNI

5 45 32 2270 280 400 5508.5 14 20 27.55.12 3.11 2.17 1.580.459 0.279 0.194 0.14

40 44 54 584.7 3.1 2.7 2.1

TNI

TNI

RF nodeWireless link

TNI

TNI

TNI

TNI

TNI

TNI

Hier

arch

ical C

ore

SoC

Fig. 1 A WiNoC-based McSoC paradigm.

R

a

bc

d

R

2D

3D

1D

Fig. 2 The illustration of disk covering.

D. Zhao et al.48

may be shared by a group of cores or dedicated to a core. Itdiminishes the heterogeneity of the cores and interacts withthe network for packet assembly, delivery, and disassembly.TNI can efficiently decouple the designs of IP cores andWiNoC, thus supporting not only component reuse but alsoWiNoC plug-n-play. Through TNI along with the so-calledpoint-to-point transfer protocol, each core may deem itselfdirectly connected to other heterogeneous cores, as if theWiNoC is completely transparent. In this work, we useVirtual Component (VCI)-compatible interface for theimplementation of TNI, where the VCI embedded splitprotocol can ease the round-trip latency constraintsbetween a request-response pair.

The RF node is equipped with a radio-frequency interface(i.e., tiny low-power and low-cost UWB transceivers andantenna) for broadcast communication, and thus any nearbynodes within the transmission range may receive the signal.Each node implements the data transmission protocol stackincluding routing, channel arbitration, buffering and flowcontrol for high-speed cost-efficient on-chip communication.In a WiNoC, a number of RF nodes are properly distributedaccording to various core functionality, non-uniform coresize, and different traffic requirements between the cores,forming a multi-hop wireless micronetwork for packetizeddata communication. Each RF node communicates with eachother through one or multiple “hops” across the network.With the multi-hop scheme, some nodes operate not only as ahost but also as a router, forwarding signals to other nodes inthe network. The collection of RF nodes connected bywireless links form the RF infrastructure which is a criticaldesign issue in determining the feasibility and applicability ofWiNoC communication architecture such as wireless rout-ability, communication capacity, power and area cost.

4. WiNoC RF infrastructure design

RF infrastructure is a key design issue to establish anapplication-specific WiNoC topology. In contrast to manyNoCs that rely on regular topology, we develop a flexibleRF micronetwork infrastructure aiming to build any domain-specific topology for nanoscale McSoCs without any “wiring”concern. In such a flexible network, several IP cores mayshare one RF node and thus are grouped into a cluster or an IPcore has its dedicated RF node. The cores in a cluster arehardwired to an RF node via TNIs and share it for data/control communication. Given the short distance between IPcores and their associated RF nodes, the hard-wired connec-tion results in minimum routing cost and area overhead. Inthis work, we propose an efficient RF nodes distributionscheme that results in proper RF nodes placement and coreclustering so as to form any irregular wireless micronetworktopology that meets the application needs by tuning thewireless accessibility. We name such an irregular and recon-figurable WiNoC, IðReÞ2-WiNoC. The tunable accessibility ofRF nodes and the reconfigurable integration capability renderthe IðReÞ2-WiNoC a vital solution to on-chip communication.

4.1. RF node distribution

Problem statement: Given a McSoC model with a tentativefloor plan, each core is abstracted as a vertex located at its

central coordinates (and a large complex core may bevirtually partitioned into several subcores and each subcoreis abstracted as a vertex). Given the maximum clusteringrange of Rc, within which a RF node can be hard-wired to itsneighboring cores. The problem of RF node distribution is tofind the minimum number of RF nodes that are optimallyplaced to ensure that all cores are within the maximumclustering range of at least one RF node. The cores are thusproperly clustered, and the wireless transmission range isproperly tuned to provide full wireless coverage on chip.Without loss of generality, this problem can be formulatedinto minimum geometric disk covering [15] in a way that aclustered wireless micronetwork is abstracted as a set of Nd

disks D¼ fDijiANdg. Each disk Di is centered at a RF nodewith a radius of Rc that covers a set of Nc IP coresC¼ fCjjjANcg embedded on the Euclidean chip plane. Theobjective is to minimize the cardinality of the disk cover Nd

while ensuring full connectivity.We construct a graph GcðVc; EcÞ to represent the SoC

model. Vc is a set of vertices (jVcj ¼ Nc), each denoting anembedded core (without loss of generality, we assume thatall cores require global communication via WiNoC). Ec is aset of edges, each connecting two vertices within a distanceof 2Rc. Assuming an optimally placed RF node can assist atleast two IP cores (it becomes trivial if one RF node canassist only one core), i.e., a disk covers at least twovertices, we can always move the RF node such that thereare two vertices on the circumference of the disk, while thedisk covers the same set of vertices. For an edge connectingvertices a and b in Fig. 2 with Euclidean distance labo2Rc,there are at most two RF node placements such that a and bare on the circumference of the disks while the disksuniquely covers two sets of vertices. One disk cover is saidto be unique only if there is at least one vertex differentfrom any other disks. For two vertices c and d wherelcd ¼ 2Rc, there is only one disk covering. For jVcj ¼ Nc

vertices on the plane to be covered by diskswith radius Rc, there are at most 2jEcj possible disksplacements to be considered ( Ecj jr Nc

2

� �). The position of

each disk is specified by its center, i.e., the coordinates ofthe RF node denoted by Di(Xi;Yi) (1r ir2jEcj). By formu-lating into minimum disk covering, this problem canbe solved by a simple greedy set covering heuristic that

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49I(Re)2-WiNoC: Exploring scalable wireless on-chip micronetworks for heterogeneous embedded many-core SoCs

selects at each iteration the disk that covers the largestnumber of vertices [16].

4.2. Accessibility tunable topology formation

Once the RF nodes are properly placed, the nodes which fallwithin each other's transmission range are connected bywireless links, thus forming the WiNoC topology. Two factorsaffect the topology construction for a given SoC floor plan,namely, the core clustering range (i.e., Rc) and the wirelesstransmission range (i.e., Rt), which work interdependentlyto determine the number of RF nodes needed and theircorresponding placement to cover the data communicationof all IP cores. As the RF infrastructure counts for the majorhardware overhead of WiNoC, minimizing the number of RFnodes can effectively reduce the area cost and powerconsumption. In the meantime, large clustering of coresmay overload the associated RF node as a RF node can onlyassist one core at a time. Such performance-cost tradeoffsmust be studied in the formation of topology. Our proposedtopology formation scheme seeks the minimal number of RFnodes while ensuring workload balancing.

More specifically, a reference clustering range Rcrefbounded by the maximum number of RF nodes is set upfirst. Such a reference range is found to be the maximumpossible disk radix which ensures the maximum coverage ofnon-overlapped disks on chip. To balance the traffic work-loads, a 2-D IP core communication relationship matrix isconstructed where each entry represents the communica-tion requirement of a source-destination pair in a unit timeperiod. For example, if the McSoC application targets atuniformly distributed traffic, all matrix entries are the sameas the node injection rate divided by the number of IPcores. Once the clusters are formed, a 2-D RF communica-tion relationship matrix is constructed accordingly by sum-ming up the traffic demands of all IP cores within the samecluster. The overall traffic workloads of a RF node TLrf arethus obtained, which is the sum of all incoming and outgoingtraffic via the RF node. A high performance and costeffective topology is determined by iteratively running theRF node distribution algorithm by gradually increasing theclustering range Rc from Rcref until TLrf where each RF nodehits the maximum traffic load threshold. Note that, as a RFnode handles both local and global network traffic, we setthe threshold below 0.5 where the network works mostlyunder the saturation point. Once the RF nodes are placedon-chip, the WiNoC topology is formed by searching for theleast wireless transmission range which ensures full con-nectivity. Let S be the set with different disk covering and Dbe the disk set returned by the greedy algorithm, Algorithm1 delivers a topology design to cover all jCj ¼ Nc IP cores onthe chip plane. Fig. 3 illustrates a hypothetical WiNoCtopology with 15 RF nodes formed for an example McSoCof 30 IP cores.

Algorithm 1. RF node distribution and topology formationalgorithm.

1

C’fCiðxi; yiÞjiA jCjg; 2 S’|; 3 D’|;

4

for (i¼ 1 : jCj�1) do� 5

6

7

8

for ðj¼ 2 : jCjÞdoif ðdistðCi;CjÞr2RÞ then���

obtain at most two different disk covering;

S [ SXSXþ1 [ SXSXþ2;

end

end

�����������

�������������

3 Topology formation with enhanced disk covering.

end

9 while (Ca|) do� 10

11

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14

select set SiAS that maximizes jSi \ Sj;balance workload;

S¼ S�Si;

D¼ D [ Si;

remove the vertices covered by Si from S;

�����������

15

end 16 return D;

5. Design of region aided routing for irregularWiNoC

Data transmission protocol is an integral part of WiNoC. Tofacilitate packetized data transmission in irregular WiNoC, anefficient routing scheme is further devised to address itsunique characteristics that distinguish itself from all othernetworks developed so far. First, WiNoC has extremely limitedresources (e.g., circuit area and power) available on chip forthe implementation of routing protocol; second, it has fixednetwork topology with medium scale and density that is knownprior to implementation; third, it has very low delay tolerancefor supporting the real time applications. In this work, wedevelop a new distributed table routing scheme, namelyregion-aided routing to find the shortest multi-hop routingpath while minimizing the hardware complexity of RF nodeprotocol architecture. The overhead involved in routing mainlystems from the implementation of routing logic (i.e., therouting algorithm) and the maintenance of routing information(e.g., the neighbor list, network topology, and routing table).Aiming at hardware efficient design while achieving the qualityof service required by a wide range of on-chip applications, weenvision that this research will push the frontier of wirelesstechnology to an extreme of simple and compact design formicro-scale communications.

D. Zhao et al.50

5.1. Distributed region table routing

To ensure successful data delivery and low-cost implemen-tation of routing decision, we propose a region-aidedrouting (RAR) scheme as illustrated in Fig. 4. The basic ideais that each RF node divides the entire chip plane, from itsown perspective, into several rectangle zones, we namethem as regions. Each region has a region header which isthe neighbor of the decision node. The region border isdefined by the minimum and maximum XY-coordinatesamong all nodes within the region. Thus the four bordercoordinates of [Xmin, Xmax, Ymin, Ymax] of a region will bestored at the comparator array (as explained in Section 5.3)to uniquely identify this region. If Nr regions are delimitatedfor each RF node, an array of Nr � 4 border coordinates ismaintained at the RF node. The region borders are effi-ciently utilized to identify the region where the destinationnode is located. The regions therefore should represent thecompressed topology information to make globally opti-mized routing decision. A region can be quickly identified bycomparing the destination address [Dx,Dy] contained in thepacket header to the region borders. If Xi

minrDxrXimax and

YiminrDyrYi

max, destination D is found to be located inregion Ri and the packet will be forwarded to the header ofregion Ri. For example, an RF node A wants to send packetm to its destination node D, it forwards m to its neighbor Cwhich delimits the unique region where D is located. Werepeat this process until D is eventually reached.

5.2. Region delimitation

If the regions can be properly delimited in a region-aidedrouting scheme, the routing decision can be tightly con-trolled within the optimal solution. In this section, wedesign an efficient region delimitation (RD) algorithm todefine the regions. Since the network topology is deter-mined a prior, this algorithm runs off-line and the regions asindicated by region borders are recorded for each node.Some critical concerns should be taken to orient thedelimitation of regions. First of all, a region should reflectthe compressed topology information that gives us theability to calculate the shortest path to a destination.Second, a destination node can only appear in one regionand there is no mutual overlapping between regions. Lastbut not least, the number of regions at each decision nodeshould be minimized to reduce the hardware cost. The RDalgorithm consists of three major steps, namely, region pre-

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Full Topology Routing Decision Tree Regio

Fig. 4 The illustration of

identification, mutual overlapping elimination, and regionborder extension.

Region pre-identification: The best routing path betweena source-destination pair should be the one with theminimum path cost which is evaluated by various metrics,such as hop count, expected transmission time, and pathinterference. For WiNoC such a static network, thesemetrics can be combined together to estimate the cost. Inthis paper, we only consider hop count as the routingmetric, however the algorithm can be easy extended toincorporate various metrics.

We consider a WiNoC topology I¼ ðN; LÞ consisting of afinite set of RF nodes N and a finite set of wireless links L.Each wireless link is associated with a link cost. Theminimum cost path between any source-destination pair isfound by running the shortest path algorithm (e.g., Dijk-stra's algorithm). We obtain a routing decision tree for anynode to any other destinations as shown in Fig. 4(b). AnN�N path cost matrix (PCM) is constructed to record theminimum cost (hop count) for all source-destination pairs ina WiNoC. For each decision node S, we may derive adedicated Nneb � Ndst path cost matrix (namely N2D matrix)including all path entries from any of its neighbor to anydestination node (excluding S and the Nneb neighbors). Eachentry N2Dði; jÞ represents the minimum path cost from theith neighbor to destination node Dj. For a column j, we canalways find an entry with the minimum path cost within thecolumn which indicates that destination Dj can be minimum-cost reached by S' ith neighbor. Thus a region is created thatcontains Dj while neighbor Ni is defined as the header of thisregion. In this way, we go through every column to identifythe region header for each destination, and determineaccordingly either to create a new region when encounter-ing a new header or to expand an existing region for thesame header by adding more nodes into it. The regionborder is updated by the minimal and maximal XY coordi-nates among all nodes in the current region. Note that,unless a column contains exactly one minimum cost entry,additional effort is required to ensure that one destinationis contained only in one region.

For efficient region delimitation, two types of regionheaders are defined, irreplaceable or replaceable regionheaders. If a column in an N2D matrix contains a singleminimum entry, i.e., a destination can only be minimum-cost reached by one neighbor, such a neighbor is named asan irreplaceable region header while this destination isdefined as the identifier of the region, and this region mustexist. Otherwise, the region is replaceable and may not be

Root NodeRegion HeaderDestination NodeWirelss linkRegion Border

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region aided routing.

51I(Re)2-WiNoC: Exploring scalable wireless on-chip micronetworks for heterogeneous embedded many-core SoCs

necessary to be created. In order to minimize the number ofregions while keeping the region area as small as possiblefor accurate region delimitation, an efficient way is to firstfind all region identifiers to determine the correspondingirreplaceable regions. Then we define the regions for theremaining unidentified destination nodes. There are threecases.

�

If a node can be minimum-cost reached by either anirreplaceable region header or one or several replace-able region headers, the node is always allocated in theirreplaceable region.

�

If a node can be minimum-cost reached by more than oneirreplaceable regions headers, the node is allocated inthe irreplaceable region that results in minimum regionarea expansion. If the increased areas are the same, thenode will belong to the closest region header from S.

�

If a node can be minimum-cost reached by more than onereplaceable regions headers (the replaceable regions areempty initially), the furthest neighbor will be chosenwith the potential to cover more such unidentifieddestinations. If those regions are not empty, the onethat covers more destinations will be chosen.

Mutual overlapping elimination: It becomes essential totackle the region overlapping problem, as the rectangleborder may represent an enlarged area than the actualgeographic occupation of the nodes in the region. Over-lapping of different regions causes confusion for correctrouting decision. There are two types of overlapping, simpleoverlapping and mutual overlapping.

�

If the nodes in the overlapping area belong to only one ofthe overlapped regions, simple overlapping occurs.

�

If the nodes in the overlapping area belong to differentoverlapped regions, mutual overlapping occurs.

Region overlapping can be easily detected by introducing anNov � Nov region overlapping matrix (OVM), where Nov is thenumber of overlapped regions. If a node belonging to regionRj also falls within the border of region Ri, OVM(i; j)=1,otherwise OVM(i; j)=0. A simple overlapping is found if OVM(i; j)=1 while OVM(j; i)=0. A mutual overlapping is detectedif OVM(i; j)=OVM(j; i)=1 as shown in Fig. 5(a).

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Mutual overlap Overlap

Fig. 5 Region overlap: (a) mutu

The problem of simple overlapping can be solved bypriority decoding the decision making of overlappedregions. For example, several consecutive simple overlap-ping form a loop as shown in Fig. 5(b). We may derive adecision truth table (DTT) from the OVM simply by convert-ing (i) a ‘1’ in OVM to a ‘0’ in DTT, (ii) a ‘do not care’ in OVMto ‘1’ in DTT, and (iii) a ‘0’ in OVM to a ‘do not care’ in DTT.The region thus can be uniquely defined based on the truthtable. It is more complicated in mutual overlapping. Thefirst measurement that can be taken is to check whether thenodes in the overlapping area can also be minimum-costreached by other region headers. If so, these nodes can bereassigned to other regions. By proper reassigning, all thenodes in a mutual overlapping will belong to the sameregion or the regions can be redelimitated to eliminateoverlapping. In the worst case, new regions have to becreated for unsolvable overlapping, each containing onenode from the overlapping area with its original regionheader as the region header of the newly created region.The original regions will be redelimitated. For the exampleWiNoC, we get a total of 4 regions as shown in Fig. 4(c) withmutual overlapping being eliminated and a simple over-lapping being handled by the region decoder.

Border extension: The region border can be extended tofurther reduce the hardware cost without hurting therouting decision. For example, in order to identify theregion where a destination node is located, we need 4Nr

comparators. Even with the number of regions as small as 4,we still need 16 comparators. We observe that if the regionsdefined for an RF node share the same X or Y bordercoordinate, they may share the comparators as well. Arefinement step is pursued to extend the original borders toreach the chip edge or meet the other borders withoutintroducing any mutual overlapping problem. Clearly, theright vertical border or bottom horizontal border might beextended through a decreasing (in terms of coordinate)extension and the left vertical border or top horizontalborder can be extended through an increasing extension.We restrict the extension rule as follows. If the borders canbe extended to the chip edge, the border coordinates areset to the same as the chip edge; otherwise an extension isperformed in a way that the region borders of two oppositeregions expand towards each other by 1 at a time. Withborder extension, the required comparators are reducedfrom 16 to 4 as illustrated in Fig. 4(d), which leads to a 75%hardware cost reduction.

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Fig. 6 Hardware architecture of RAR routing decision logic.

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Fig. 7 Illustration of RF node microarchitecture.

D. Zhao et al.52

5.3. Routing decision logic implementation

The hardware implementation of the routing decision logicis illustrated in Fig. 6, consisting of three major functionalblocks of comparator array, region decoder, and neighborlist.

The neighbor list of a node contains a sequence ofaddresses of all its immediate neighbors. Upon receiving adata packet, the RF node reads in the destination address(DA) contained in the packet header. If the destinationaddress matches with an entry in the neighbor list, i.e., thedestination is a neighbor of the node, the next-hop addressis thus found that is the same as the DA. If the destinationaddress is not in the neighbor list, the RF node searches forthe next-hop address through the region decoder. Taking thedestination address as inputs, the comparator array com-pares DA with the pre-stored region borders to identify theregion. The number of comparators needed is determinedby the number of different coordinates of region bordersexcept for those at the chip edge. If the destination addressfalls within the border (XminrDxrXmax and YminrDyrYmax) of a region, the comparison result for the correspond-ing region is ‘1’, otherwise ‘0’. The comparison results arethen fed into the region decoder that implements DTT usingcombinational logic and the neighbor ID (o_port) isobtained. The neighbor ID is used to access the neighborlist to obtain the neighbor address so that the address of thenext hop can be inserted into the outgoing packets. Basedon the border definition and DTT, the VHDL code for eachnode can be automatically generated from the proposedRAR algorithm. After RTL synthesis, the maximum arearequired for the array of comparators is 40 gates, and forthe neighbor list is 161 gates.

6. RF node microarchitecture design

To facilitate WiNoC system implementation and perfor-mance demonstration, the RF node microarchitecture isdeveloped which implements the mechanisms for routing,channel arbitration, buffering and flow-control. As shown inFig. 7, the routing decision logic (RDL) implements theproposed region aided routing scheme to define the path apacket routes from a sender to a receiver. The channelarbiter implements a multi-channel synchronous and dis-tributed arbitration scheme. The flow control logic imple-ments a distributed prioritized flow control strategy to deal

with the data traffic on a channel and inside a RF node. Thebuffers are used to store packets when a channel is busy toensure lossless data transmission. To minimize buffer sizing,a virtual output-queuing scheme is applied to efficientlymanage buffering. Due to limited processing resources, a RFnode can only receive or send a packet at a time whichgreatly simplifies the intra-node routing and buffering.

6.1. Multi-channel arbitration

A synchronous and distributed arbitration scheme (i.e., SD-MAC) [11] has been proposed to resolve single channelaccess contention. Similar to SD-MAC, we propose a multi-channel counterpart to ensure collision-free transmission ona multi-channel WiNoC, dubbed multichannel SD-MAC (mSD-MAC). Again, mSD-MAC is based on synchronized dataframes, where each frame consists of two intervals: thecontention interval and the data interval. The right toaccess the data channel is granted by the negotiation inthe control channel. Such negotiation is carried out by abinary contention mechanism in replace of binary count-down handshaking in SD-MAC. As the channels are coded in away of collision avoidance, mSD-MAC is much simplified.

More specifically, in the contention interval, a node (say,X) that has data to send generates a random contentionnumber with k bits. To reduce the contention delay, multi-ple contention bits can be sent simultaneously. The conten-tion numbers received from multiple senders will becompared once at the receiver and the sender with thelargest contention number will be the winner and begranted the channel access to the receiver. Such contentionprocedure is simple, but paid at the cost of wired control-ling overhead. The mSD-MAC ensures 100% collision freewhile retaining the same features of high-efficiency, sim-plicity, robustness, fairness, and QoS capability as SD-MAC.Moreover, mSD-MAC greatly improves the network capacityand enhances end-to-end performance by ensuring moreparallel transmissions than SD-MAC.

6.2. Virtual output queuing

In order to differentiate packet flows, we use an outputqueuing architecture. More specifically, the buffers are

53I(Re)2-WiNoC: Exploring scalable wireless on-chip micronetworks for heterogeneous embedded many-core SoCs

organized in a virtual output queuing strategy with adynamically shared linked buffer, where each virtual queuecorresponding to one neighboring node temporarily storesthe packets going to the neighbor. In addition, a sharedbuffer stores the incoming packet before its next-hop isdetermined by the RDL and consequently the packet isdynamically linked to the corresponding virtual outputqueue. To minimize the buffering cost, we determine thesmallest buffer size for ensuring the transmissions free ofdeadlock. With the Nc credit-based backpressure scheme,only Nc packets can be delivered from a node to any one ofits downstream neighbors. The worst case scenario happenswhen multiple flows crossing at a node contend for the samenext-hop, requiring ðNnei�1Þ � Nc buffer units, where Nnei

denotes the number of neighbors. Similarly, the node itselfmay also serve as the downstream node of its neighbors,calling for again a total of ðNnei�1Þ � Nc buffer units.Besides, Nc buffer units are needed for the self-injectedpackets, summing up to a total of ð2Nnei�1Þ � Nc bufferunits required to guarantee deadlock freedom.

6.3. Distributed flow control

An efficient flow control and congestion alleviation strategyis essential to improve WiNoC end-to-end performance dueto the severe congestion resulted from the close interactionbetween wireless channel contention and traffic overflow. Acustomized distributed flow control and congestion controlstrategy as in [17] is seamlessly integrated into mSD-MACthat involves multiple mechanisms, such as fast forwardingby prioritized channel arbitration and credit-based back-pressure congestion control. The fast forwarding schemegrants higher priority to a downstream node which justreceives a packet to increase its winning probability for thenew round of channel arbitration. To resolve receiver-basedchannel contention, a receiver-prioritized forwardingscheme is developed and incorporated into mSD-MACscheme by assigning prioritized contention numbers inbinary countdown. The Nc-credit based backpressure con-gestion control blocks the up-stream node from continu-ously forwarding packets unless the previous upstreampackets have been released to or consumed by the down-stream node, thus resolving intra-flow contention.

In a nutshell, when a packet arrives at a RF node, thepacket header which contains the destination address issent to RDL to determine the next-hop and to generate anew header while the data payload is sent to the dedicatedvirtual queue combined with the new header. Upon theround-robin scheduling, one of the packets waiting at thehead of the virtual queues will be sent the channel accessrequest, i.e., the mSD-MAC contention number to itscorresponding down-stream node. In the meantime, a nodewill receive multiple requests from its neighbors and thenode's channel arbiter will grant authorization to one ofrequesters. As a result, a channel is established betweenthe winning sender and the receiver and the chosen packetwill be transmitted to its next-hop immediately. Note that,limited number of channels are distributed beforehand toenhance transmission concurrency while providing sufficientchannel bandwidth. In addition, the packet queuing processfor the next packet including intra-node routing, buffering

and output scheduling can be launched in parallel with thechannel competition of the current packet.

7. Simulation study and performanceevaluation

A WiNoC simulator with identical and omnidirectional radiorange is built up to cover the communication among the IPcores within an McSoC model. Specifically, the IP coreplacements are randomly generated on the chip plane.The RF nodes are optimally distributed and consequently,the wireless topology is formed by running the optimizationalgorithm as discussed in Section 4. The RF node micro-architecture developed in Section 6 is implemented at eachnode that runs our proposed data transmission protocol forsuccessful multi-hop data/control communication inirregular WiNoC.

7.1. Routing efficiency and routing costevaluation

In our simulation model, 100 randomly generated networktopologies with the number of RF nodes ranging from 16 to116 are used to evaluate the performance of RAR algorithm.The routing decision on all these topologies is 100% loop-free. The total hop count for all source-destination pairs onany topology is exactly the same as the hop count obtainedfrom the shortest path algorithm. The performance of RARis guaranteed by properly grouping the destination nodesinto regions based on the minimum path cost.

Proposition 1. RAR based routing decision achieves mini-mum path cost.

Proof. It is clear that any one-hop decision is correct. LetCSD be the minimum path cost for an n-hop path (n41) fromnode S to node D based on the predefined routing metric.Let CSDR be the path cost by running RAR algorithm, whereCSDR ¼ CSDþc (c40). There is at least one intermediatenode I along the path that satisfies CSIR ¼ CSI, andCIDR ¼ CIDþc. When node I makes routing decision accordingto the routing decision tree obtained from the shortest pathalgorithm, it must ensure that CIDR ¼ CID, thus c=0, andCSDR ¼ CSD. □

Proposition 2. RAR based routing decision guarantees loop-free.

Proof. Since the minimum cost from the node to itself isinfinite, based on Proposition 1, if there exists a path loopfrom S to S, CSSR ¼ CSS ¼1. For any intermediate node Ialong this path loop, CSIR þCISR ¼ CSIþCIS ¼1. Either CSI orCIS should be infinite, which is impossible for a connectednetwork. We may simply conclude that a path built by RAR isloop-free. □

The performance of RAR routing scheme is compared withtable driven routing (TDR) [18] and location based routing(LBR) [19]. TDR relies on a central node to maintain arouting table and to make the routing decision. Thisapproach involves high overhead stems from a centralizedrouting algorithm, large packet size (the entire pathinformation should be contained in packet header), and

D. Zhao et al.54

large routing table, thus leads to low scalability. LBRreduces routing algorithm complexity by making routingdecision at the intermediate node based on the geographicdistance to the destination. Neither the routing table northe network topology needs to be maintained. However, LBRresults in much higher hop count than the ideal case due tolocalized decision. Further, LBR may fail at concave nodes,thus partial flooding should be performed to ensure 100%delivery. Flooding will limit the network efficiency since itoccupies the capacity of the whole network. Moreover, dueto the uncertainty accompanied with flooding, the imple-mentation complexity is high. The three types of routers areimplemented and their performance are compared in termsof delay and area cost as illustrated in Fig. 8. In theexperiments, all topologies use 10 bits address to representthe node location. The designs are synthesized throughMentor Graphics LeonardoSpectrum level 3 based on theSCL05u technology. For fair comparison, the timing con-straint for synthesis is set to ensure that the decision logicsmeet their minimum delay requirements. From the compar-ison we can see that RAR achieves the best performancewhile the scalability of the network is ensured.

7.2. IðReÞ2-WiNoC network performanceevaluation

The experiments are carried out to evaluate the networkperformance of the proposed IðReÞ2-WiNoC under three

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synthetic traffics: uniform, one-hot spot and two-hot spot.Under uniform traffic pattern, each RF node has the samechance to receive a packet. Under one-hot (or two-hot) spottraffic pattern, one randomly selected node (or two nodes)will accept 50% (or 1/3 per node) of the total generatedtraffic while the remaining traffic is uniformly distributedamong all other nodes. During the simulation, the packetsare injected in frame times where the unit of injection rateis determined by the number of packets per node per frametime. When a packet is generated at a node, its destinationis randomly assigned. Each RF node is associated with arandom traffic generator that generates the above threedifferent traffic patterns. After a WiNoC system is warmedup by running 1000 frame times, 20,000 packets aregenerated under certain traffic patterns and injection rates.Once all packets reach their destinations, the WiNoC systemperformance is evaluated in terms of throughput and delayunder a 10 Gbps network bandwidth.

The performance improvement is apparent when shiftingfrom a single channel WiNoC to a multi-channel network. Asshown in Fig. 9a, the concurrency level of multi-channelingis more than doubled when compared with the singlechannel alternative. As a result, the network capacitydoubles under uniform traffic. Under hot-spot traffic, theperformance bottleneck is the processing speed of the hotspots. Thus, the throughput difference between the multi-channel and single channel configurations tends to shrink.As observed, the throughput is comparable under both one-hot and two-hot spot traffics. The comparison of latency in

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Fig. 10 Network performance comparison under different network scales: (a) network throughput; (b) end-to-end latency.

55I(Re)2-WiNoC: Exploring scalable wireless on-chip micronetworks for heterogeneous embedded many-core SoCs

Fig. 9b again demonstrates that the multi-channel config-uration brings in performance improvement over the singlechannel counterpart. The frame-based channel arbitrationinterleaves contention handshaking and data transmissionand thus ensures high utilization of wireless bandwidth,leading to great end-to-end performance even for largeirregular WiNoCs. We evaluate the scalability of WiNoCunder 3 different network sizes: 4� 4, 6� 6 and 8� 8. Aswe can see from Fig. 10, the network throughput scalesup while the latency scales down when the network sizeincreases.

8. Conclusion

The complexity and heterogeneity nature of nanoscaleMcSoCs promote the idea of cost-effective and power-efficient wireless NoC for the on-chip communication amongdiverse, mixed technology IP cores. This paper centers onthe design of WiNoC RF infrastructure with the features ofreconfigurable integration and wireless tunable accessibil-ity. This paper has further presented the design and hard-ware implementation of a loop-free, minimum costguaranteed distributed table routing scheme for irregularWiNoC. An efficient and low-cost RF node microarchitecturewas implemented, aiming to devise simple and compact RFnodes for establishing WiNoC under extremely limitedresources. The RF nodes are properly distributed andwireless topology is optimally built up by striving forbalance between performance and cost. The simulationstudy demonstrated that both the performance and scal-ability of the network are ensured and low-cost and high-efficiency design of WiNoC RF infrastructure is achievable.We have demonstrated that the heterogeneous nature ofon-chip cores and energy efficiency requirements of highperformance embedded ubiquitous computing call forWiNoC paradigm.

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