Ip Library for Amba Interconnect

IP LIBRARY FOR AMBA INTERCONNECT

The National Semiconductor IP Library for AMBA Interconnect is a collection of AMBA 2 compliant building blocks providing both the AMBA bus fabric and a rich set of peripheral functions.

The AMBA IP Library components connect to the AMBA 2 AHB and/or APB and are suitable for use with any AMBA 2 compatible controllerfor example, the National Semiconductor CR16CP. The CR16CP is also available from IPextreme; however, AMBA IP Library components can be used with or without the CR16CP.

Example System Showing All Components

IP FOR A VARIETY OF FUNCTIONS

AMBA IP Library components implement a wide range of functions, enabling rapid development of complete subsystems. Available functions include:

AMBA bus fabric (AHB and APB)

System functions such as DMA, interrupt control, real-time clock, timers, and wakeup

Standard interfaces such as USART, CAN, I2S, I2C, Smart Card, GPIO, and an advanced audio interface

Several of the components support DMA operation for reduced CPU utilization. To support system debug, several of the peripherals also have a freeze input signal to halt the activity of the peripheral.

Each component implements clock gating for low-power operation and offers suitable configuration options for device-specific features.AMBA BUS FABRIC IP

AHB BACKBONEThe AHB Backbone provides the AHB fabric to connect AHB masters and slaves. It consists of two main modules: Arbiter and Decoder.

The Arbiter ensures that only one bus master can initiate data transfers at any given time. It contains an optional register interface for allocating priorities and algorithms, and for selecting the default AHB master.

The Decoder generates a select signal for the selected slave, based on the address driven by the current AHB master. The Decoder supports up to 8 address regions for each slave.

AHB WATCHERThe AHB Watcher monitors the AHB and logs bus errors as well as attempts to access illegal address locations by any of the AHB bus masters (for example, a CPU or DMA controller). The AHB Watcher status can be checked by polling or through a maskable interrupt.

AHB-to-APB BridgeThe AHB-to-APB Bridge provides the interface between the AMBA AHB and APB, acting as a slave on the AHB and as the bus master on the APB. It supports up to 16 APB slaves, 16 or 32-bit APB bus widths, and AHB:APB clock ratios ranging from 1:1 to 16:1 (in integer intervals).

SYSTEM FUNCTIONS (AHB)

DMA CONTROLLERThe DMA Controller attaches to the AMBA AHB and provides up to 16 DMA channels for transferring blocks of data between memory and I/O devices with minimal CPU intervention. The DMA Controller supports hardware DMA requests from up to 64 sources. In addition, each DMA channel supports a software DMA request.

RAM CONTROLLERThe RAM Controller also attaches to the AHB and enables connection of on-chip RAM, providing a generic interface compatible to a single-port, synchronous SRAM.

SYSTEM FUNCTIONS (APB)

INTERRUPT CONTROLLERThe Interrupt Controller receives internal and external interrupt sources and generates maskable and non-maskable interrupts to the CPU when required. For non-maskable interrupts (NMIs), the Interrupt Controller supports:

1-7 internal NMI sources

External NMI

External In-System Emulator (ISE) interrupt (optional)

For maskable interrupts, the Interrupt Controller supports:

1-127 level-sensitive or software-triggered interrupt sources

CPU vectored-interrupt mode

Fixed priority allocation between interrupt sources

Enabling/disabling of individual interrupt sources

Polling of interrupt sources through a status register, regardless of whether the interrupts are enabled or disabledTIMER AND WATCHDOGThe Timer and Watchdog generates the clocks and interrupts used for periodic functions in the system and provides watchdog protection of software execution. Features include:

Programmable input clock prescaler

16-bit programmable interrupt timer

8-bit watchdog counter

Detection and watchdog signal generation for a variety of conditions

Watchdog freeze input

Lock option for fully protected watchdog

Data match mechnanism for watchdog service

MULTI-FUNCTION TIMERThe Multi-Function Timer is a 16-bit timer that can be programmed to support a wide range of application requirements. It contains two independent 16-bit timer/counters and two 16-bit reload/capture registers. The independent timer/counters can operate from several clock sources in PWM mode, input capture mode, pulse accumulate mode, PWM pulse train mode, or as system timers.

VERSATILE TIMERThe Versatile Timer controls eight I/O pins, each of which can function either as a PWM output with programmable output polarity or as a capture input with programmable event detection and timer reset. The Versatile Timer supports a flexible interrupt scheme with four separate system-level interrupt requests and a total of 16 interrupt sources, each with a separate interrupt pending flag and interrupt enable bit. It can be configured to provide up to:

Eight fully independent 8-bit PWM channels

Four fully independent 16-bit PWM channels

Eight 16-bit input capture channels

The Versatile Timer implements four timer subsystems, each of which contains:

One 16-bit counter

Two 16-bit capture/compare registers

One 8-bit fully programmable clock prescaler

Each timer subsystem can operate in the following modes:

Low-power mode (all clocks stopped)

Dual 8-bit PWM mode

16-bit PWM mode

Dual 16-bit input capture mode

MULTI-INPUT WAKEUPThe Multi-Input Wakeup module provides a wakeup signal interface to exit from various low-power modes. It supports 32 wakeup or interrupt sources and provides signal conditioning and grouping of external interrupt sources.

REAL-TIME CLOCKThe Real-Time Clock module provides real-time information to the system. It implements a real-time counter and provides alarm functions that can trigger periodic system interrupts or can be used to return the system from a low-power mode at predetermined times. Features include:

Programmable input clock divider

16-bit prescaler counter

32-bit main real-time counter

Compare registers with interrupt capability upon match

Interrupt generation for individual events

Combined interrupt output

STANDARD INTERFACES

USARTThe USART module is a full-duplex synchronous/asynchronous receiver-transmitter capable of operating in either synchronous or asynchronous (UART) mode. It supports a wide range of software programmable baud rates and data formats, parity generation, error detection, flow control, and wakeup pattern detection. It can generate interrupts for several conditionseach with a separate enableand supports DMA for both transmit and receive (also with separate enables).

I2S AUDIO INTERFACEThe I2S Audio Interface provides a dedicated serial link between an APB subsystem and off-chip audio devices. The I2S Audio Interface complies with theI2S Bus specification, Philips Semiconductors, February 1986 (Revised June, 1996). Features include:

Bidirectional synchronous transceiver operation in either master or slave mode

Support for a variety of audio data widths and sample rates

Four 8-bit FIFOs (left/right transmit and left/right receive)

Interrupt and DMA support

ADVANCED AUDIO INTERFACEThe Advanced Audio Interface provides a serial, synchronous, full-duplex interface to codecs and similar serial devices. It is functionally similar to a Motorola Synchronous Serial Interface (SSI). However, it only provides a subset of a standard Motorola SSI implementation. Features include:

Synchronous or asynchronous receive/transmit paths

8 or 16-bit data words

16-word receive and transmit data FIFOs

DMA support for reduced CPU utilization

A variety of clocking and frame synchronization options

CAN CONTROLLERThe Controller Area Network (CAN) Controller implements Full-CAN functionality compliant withCAN SpecificationRevision 2.0 Part B. It supports applications that require a high-speed (up to 1 Mbit/s) or a low-speed interface with CAN bus master capability. Features include:

Programmable bit rate

Standard or Extended Frames

15 message buffers, each configurable for transmit or receive, with one message buffer providing an optional Basic-CAN path

Remote Frame support

Acceptance filtering

Interrupt capabilities

Diagnostic functions

MICROWIRE/SPI CONTROLLERThe MICROWIRE/SPI Controller is compatible with all MICROWIRE peripherals and SPI peripherals. It enables several devices to be connected on a three-wire system. At any given time, one device is the master and the others are slaves. The MICROWIRE/SPI Controller is capable of operating as either a master or a slave and in either 8-bit or 16-bit mode.

SMART CARD INTERFACEThe Smart Card Interface provides a communication interface to a Smart Card, meeting all of the requirements defined in the ISO 7816-3 T=0 protocol and supporting the T=1 protocol through software. Features include:

16-byte transmit/receive (half-duplex) FIFO

Software-configurable interrupts

DMA support for transmit and receive

GENERAL PURPOSE I/O CONTROLLERThe General-Purpose I/O Controller provides a bidirectional port, with alternate function capablity, to an external off-chip interface. As an external interface, the General-Purpose I/O Controller is designed for direct connection to I/O pads. Features include:

Programmable pin direction; each pin can function as an input or output port

Internal weak pull-up, pull-down

Direct low-impedance analog input

Read back on all registers

Each pin may be controlled by other modules through its software-selectable alternate function as an alternate source

Selectable high drive current option

I2C INTERFACEThe I2C Interface provides a two-wire serial interface compatible with the ACCESS.bus physical layer, enabling easy integration of a wide range of low-cost memories and I/O devices such as EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips, and peripheral drivers.

The I2C Interface is also compatible with Intel's System Management Bus (SMBus) and Philips' I2C bus. It can be configured as a bus master or slave, and can maintain bidirectional communications with both multiple master and slave devices.

The I2C Interface can be used with polling or interrupt.

DELIVERABLES

Each AMBA IP Library component is delivered in technology-independent RTL source code format. Components purchased from the IPextreme Core Store are delivered in encrypted source code format. Each product package includes:

Synthesizable Verilog source code (encrypted if purchased from the Core Store)

Integration testbench and tests

Documentation

Automatic configuration through the IPextreme IP Distribution and Support Portal

Scripts for simulation and synthesis with support for commonly used EDA tools

RAM CONTROLLER

The RAM Controller (RAMC) provides connectivity between an AMBA 2 AHB and a synchronous RAM (SRAM). It features single-cycle, pipelined access to 32-bit SRAM and supports 8, 16, and 32-bit data accesses. It is the same RAM Controller IP proven in high-volume devices from National Semiconductor.

The host interface of the RAMC complies with the AMBA 2 AHB protocol. The AHB data bus width is 32 bits, while the AHB address bus width is configurable (332 bits). The RAMC does not generate wait states on the AHB; each data phase is one clock clock cycle.

The RAMC connects to a synchronous RAM through a generic RAM interface. The RAM must support byte-write operation and can be implemented either as a single 32-bit RAM or as four 8-bit RAMs.

The RAMC does not pass the 2 least significant bits of the AHB address (HADDR [1:0]) to the RAM address output. Therefore, byte-addresses on the AHB address bus become 32-bit word addresses at the RAM interface. For write accesses, the RAMC automatically generates the correct RAM byte write enables according to the values of AHB signals HADDR[1:0] and HSIZE[2:0].

For read accesses, the RAMC always reads a 32-bit word and returns the full 32 bits on HRDATA[31:0].

If a read access occurs while a write access to the same address is pending, the RAMC returns the internally registered write data for the byte(s) that have not yet been written to the RAM.

FEATURES

AMBA 2 AHB compliant host interface

Single-cycle pipelined read/write accesses to 32-bit SRAM

8, 16, or 32-bit accesses

Configurable address width

SRAM can be implemented as single 32-bit RAM or four 8-bit RAMs

Little endian data interface

Local clock gating for minimal power consumptionTimer and Watchdog control

The Timer and Watchdog from National Semiconductor generates clocks and interrupts that can be used to time periodic functions in a system. It also provides watchdog protection for software execution.

A programmable down-counter provides the timer function. The timer clock source is derived from a slow clock input signal that is processed by a configurable clock prescaler. Upon reaching zero, the timer generates an interrupt and, if programmed to do so, restarts counting from the programmed start value.

The watchdog function generates a watchdog error if the watchdog service occurs too early, too late, or upon a data mismatch. Watchdog error signals can be used to initiate a system recovery; for example, a non-maskable interrupt or system reset.

A register lock feature provides protection against erroneous software action. After setting the Timer and Watchdog configuration, software can lock selected registers to prevent write access. Once a section of the Timer and Watchdog is locked, only a system reset can release it.

The host interface of the Timer and Watchdog complies with the AMBA 2 APB protocol. Control registers within the Timer and Watchdog provide CPU control of clock prescaler, timer preset, timer restart, data match value for watchdog service, register lock, interrupt enable.

Status registers indicate terminal count status and, in functional test mode, the current timer and watchdog counter values.

FEATURES

Slow clock input, typically 32.768 kHz

5-bit prescaler counter

16-bit programmable periodic interrupt timer

8-bit watchdog counter

Watchdog input clock selector

Configuration lock option for fully protected watchdog

Data matching mechanism for watchdog service

Detection of the following failures:

Watchdog service performed too early

Watchdog service performed too late

Wrong data used in a watchdog service

Debug support: Freeze or suspend Timer and Watchdog activity

INTERFACES

AMBA 2 APB host interface

16-bit read/write data buses

10-bit address bus

Clock interface

APB clock for registers and wakeup signal generation

Slow clock input for timer

Interrupt and wakeup signals

Watchdog error signals to interrupt controller or reset generator

One asynchronous reset input

Freeze/suspend interface

Input signla to indicate functional test mode

DFT signals

USART

The USART is a full-duplex synchronous/asynchronous receiver-transmitter proven in high-volume devices from National Semiconductor and available exclusively from IPextreme as synthesizable IP.

The USART supports a wide range of software programmable baud rates and data formats and operates in either Synchronous or Asynchronous (UART) mode. It implements automatic parity generation and several error detection schemes. The USART is capable of detecting a wakeup pattern to selectively enable the receiver and implements flow control logic for hardware handshaking.

The host interface of the USART complies with the AMBA 2.0 APB protocol. Control registers within the USART provide CPU control of baud rate, frame format, wakeup pattern detection, operating mode, and enabling/disabling interrupts. Status registers provide interrupt and error status. In addition, there are registers that hold the transmit/receive data.

In Asynchronous (UART) mode, the USART communicates with other devices using two signals: transmit (TDX) and receive (RDX). In Synchronous mode, the USART communicates with other devices using three signals: transmit (TDX), receive (RDX), and clock (CKX); data bits are transferred synchronously with the CKX signal. Flow control is available in both Asynchronous and Synchronous modes through RTS/CTS signaling.

To reduce chip-level pin count, the USART interface signals can be shared with other on-chip functions through a General Purpose I/O (GPIO) Controller.

FEATURES

Full-duplex double-buffered receiver/transmitter

Synchronous operation using the CKX clock pin

CKX can be generated internally or externally

Asynchronous (UART) operation

Programmable baud rate between CLK/2 and CLK/32768 baud

Programmable frame formats

7, 8, or 9 data bits

1 or 2 stop bits

Odd, even, mark, space, or no parity

Hardware support of parity-bit generation during transmission and parity-bit check during reception

Software-controlled break transmission and detection

Interrupt on transmit buffer empty, receive buffer full, receive error, and delta clear-to-send (flow control mode) conditions, each with a separate interrupt enable

Internal diagnostic capability

Automatic error detection

Parity error

Framing error

Data overrun error

9-bit Attention mode

DMA support for transmit and receive with separate enables

Hardware flow control functions

Clear-to-send (CTS)

Request-to-send (RTS)

Wakeup pattern detection according to ISO14230/KWP2000

Debug support: Freeze/suspend USART activity

INTERFACES

AMBA 2.0 APB host interface


10-bit address bus

USART pins (CKX, TXD, RXD, CTS, RTS) through chip I/O pads (optionally through a GPIO Controller)

DMA interface

One transmit DMA channel

One receive DMA channel

Clock interface

APB clock for registers, DMA, interrupt functions, and for baud rate generation in Asynchronous mode

Baud rate clock input for Synchronous mode with external baud rate generation

Baud rate clock output for Synchronous mode with internal baud rate generation

Interrupt interface (four interrupts)



DFT signals

I2C Interface

The I2C Interface (I2C) provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS.bus physical layer, with additional support for the SMBus protocol, including Packet Error Checking (PEC). Through its I2C compatibility, it provides a simple interface to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips, and peripheral drivers. The I2C is the same I2C Interface IP proven in high-volume devices from National Semiconductor.

The host interface of the I2C Interface complies with the AMBA 2 APB protocol. Control registers provide CPU control of Serial Clock Line (SCL) frequency, start and stop condition generation, PEC byte generation, I2C address assignment, 7-bit or 10-bit addressing, and enabling/disabling interrupts. Status registers indicate current operating mode, packet error, and interrupt status. A serial data register shifts the serial I2C data into and out of the I2C Interface during receive and transmit operations.

The I2C serial interface consists of the standard bidirectional I2C signals: Serial Clock Line (SCL) and Serial Data Line (SDA). At the I2C IP level, there are separate unidirectional signals (scl_in_pin/scl_outandsda_in_pin/sda_out). To reduce chip-level pin count, the I2C bus interface signals can be shared with other on-chip functions through a General Purpose I/O (GPIO) Controller.

FEATURES

Compliant to SMBus (versions 1.1 and 2.0), ACCESS.Bus, and I2C (version 2.1)

Supports Standard Mode, Fast Mode (F/S), and High Speed (Hs) Mode

Programmable master or slave operation

Multi-master capable

One software-defined slave address

7-bit or 10-bit slave addressing

Global Call (broadcast) address support

Specific SMBus features:

SCL Timeout detection

Packet Error Checking (PEC)

Alert Response Address

Supports polling and interrupt-controlled operation

Wakeup signal generation upon detection of a start condition while in power-down mode

Local clock gating for minimal power consumption

ABOUT THE I2C PROTOCOL

The I2C protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines, SCL and SDA, are connected to a positive supply through pull-up resistors. Any device connected to the bus uses open-collector or open-drain drivers and can only pull the respective bus line low. Therefore, both the SCL and SDA are wired-AND type signals.

The device that initiates the transaction becomes the master of the bus. The bus master generates SCL and terminates the transaction once finished. One data bit is transferred on SDA during each pulse on SCL. Data is sampled during the high state of SCL and can change while SCL is low.

Each data transaction is composed of a start condition, a number of byte transfers, and a stop condition to end the transaction. Each byte is transferred with the Most Significant Bit (MSB) first. After each byte (8 bits), an acknowledge signal must follow.

A slave device can stall the master by extending the low period of the SCL clock while it handles the previous data or prepares new data. This process can occur after each bit is transferred or on a byte boundary. The slave stalls the bus by pulling SCL low to extend the clock-low period. Typically, slaves extend the first clock cycle of a transfer if a byte read has not yet been stored or if the next byte to be transmitted is not yet ready.

SMBUS FEATURES

The SMBus protocol (supported by the I2C Interface) is a superset of the I2C protocol and adds the following features:

SCL Timeout detection If the SCL low period exceeds the SCL timeout value, the device aborts the current operation

Packet Error Checking (PEC) through the use of a Cyclic Redundancy Check (CRC) byte

Alert Response Address, which provides slave-only devices an interrupt capability

INTERFACES



10-bit address bus

I2C bus interface pins (SCL and SDA) through chip I/O pads (optionally through a GPIO Controller)

System (APB) clock

One interrupt signal


One wakeup signal

Signals to control idle mode and halt mode

DFT signals

BLUETOOTH 2.1 CORE

The BlueMoon 2.1 solution is a complete, production-proven, certified Bluetooth HCI IP solution based on the industry leading Infineon PMB8763 single-chip Bluetooth IC. It is ideal for system-on-chip (SoC) applications that benefit from an integrated Bluetooth solution.

BlueMoon 2.1 supports all features of the Bluetooth 2.1 + EDR standard and supports integration with all Bluetooth compliant 3rd-party protocol stacks and applications.

The solution consists of three primary components:

Bluetooth 2.1 + EDR radio hard macro implemented in a 130-nm commercial process

Synthesizable digital baseband controller

Firmware-based implementation of the Bluetooth protocol stack (up to the HCI transport level) that can be committed to ROI

Key Features and Benefits

Bluetooth 2.1 + EDR including:

Enhanced data rate

Superior adaptive frequency hopping

Secure simple pairing

Sniff subrating

Extended inquiry response

Encryption pause/resume

Firmware up to HCI

Patch area in RAM for firmware upgrades

Bluetooth radio in 130-nm CMOS technology

Bluetooth power class 2 (+6 dBm typical at chip)

High RF sensitivity (90 dBm @ 0.1% BER)

Dynamic control of output power

Class 1 prepared with control lines for external power amplifier

Small number of external components required

Highly configurable UART and PCM interfaces

WLAN coexistence interface

Advanced audio processing features for superior sound quality

Support for external 32-KHz clock for ultra low power modes

The BlueMoon 2.1 solution can be upgraded to support the Bluetooth 3.0 standard by modification of the BlueMoon firmware. Future roadmaps include support for Bluetooth low energy.

Figure 1:BlueMoon Block Diagram

Interfaces

High-speed 3 and 4-wire UART (3.25 Mbaud)High-speed 3 and 4-wire UART (3.25 Mbaud)

Wake-up lines

Dual bi-directional PCM/I2S

I2C

Control lines for external power amplifier and switch for class 1 operation

Reference clock and low-power clock

GPIOs for key entries and LEDs

3-wire WLAN coexistence interface

50 balanced antenna interface

BlueMoon 2.1 Development Kit

The BlueMoon Development Kit provides a complete platform for evaluation and development of software for BlueMoon ICs and SoCs built using BlueMoon IP. The kit includes:

HCI tool box software

1 pair of evaluation boards

USB, UART, and PCM interfaces

Reference design

Documentation

Deliverables

Synthesizable VHDL source code for baseband controller

GDSII for Bluetooth radio

ANSI-C source code for Bluetooth firmware

SPI

The MICROWIRE/SPI Controller is a synchronous serial communication controller compatible with all MICROWIRE peripherals and SPI peripherals. It is the same MICROWIRE/SPI Controller proven in high-volume controllers from National Semiconductor and is available exclusively from IPextreme as synthesizable IP.

Originally developed to reduce the number of connections and, therefore, the cost of communicating with peripherals, the MICROWIRE/SPI protocol allows several devices to be connected on one three-wire system. At any given time, one device operates as the master while all other devices operate as slaves. The three-wire system includes two bidirectional serial transmit/receive signals (MDIDO: master mode data in/slave mode data out; and MDODI: master mode data out/slave mode data in). The serial clock (MSK) is driven by the current master.

The MICROWIRE/SPI Controller also implements slave select signals (MSC0LE and MS1LE at the chip-level I/O) to efficiently enable the target slave device. MSC0LE is a slave select output signal in master mode and a slave select input signal in slave mode; MS1LE is a slave select output signal used only in master mode. To reduce chip-level pin count, the MICROWIRE/SPI interface signals can be shared with other on-chip functions through a General Purpose I/O (GPIO) Controller.

The host interface of the MICROWIRE/SPI Controller complies with the AMBA 2.0 APB protocol. Control registers within the MICROWIRE/SPI Controller provide CPU control of master or slave mode, 8 or 16-bit data transfers, clock mode, shift clock frequency in master mode, slave select signal polarity, and enabling/disabling interrupts. Status registers indicate shift register busy, read buffer full, and receive overrun. In addition, there are registers that hold the transmit/receive data.

FEATURES

Supports master and slave operation

8 or 16-bit transfers

16-bit read buffer

Programmable shift clock frequency in master mode

One slave select input for slave mode

Two slave select outputs for master mode

Programmable echo back operation in slave mode

Flags for busy, read buffer full, and receive overrun with separate interrupt enables

DMA support for transmit and receive with separate enables

Programmable clock modes

Normal mode: Shift transmit data out on MSK rising edge; sample receive data on MSK falling edge

Alternate mode: Shift transmit data out on MSK falling edge; sample receive data on MSK rising edge

MSK can be high or low when idle

Debug support: Freeze or suspend MICROWIRE/SPI Controller activity

INTERFACES

AMBA 2.0 APB host interface


10-bit address bus

MICROWIRE/SPI pins (MDIDO, MDODI, MSK, MSC0LE, and MS1LE) through chip I/O pads (optionally through a GPIO Controller)

DMA interface

One transmit DMA channel

One receive DMA channel

Clock interface

APB clock for registers, DMA, interrupt functions, and for shift clock generation in master mode

Shift clock input for slave mode

Interrupt interface (one interrupt signal)



DFT signals

GPIO

The General Purpose I/O Controller provides sharable connections to chip I/O pads, supporting either 16 or 32 I/O channels. Each channel connects a chip I/O pad to either:

Data input/output registers within the General Purpose I/O Controller (general-purpose I/O function), or One of two selectable peripheral devices (alternate functions A and B)

For example, a single chip-level I/O pin can be shared, under software control, between general-purpose I/O and up to two on-chip peripheral devices such as a USART and/or other component from the National Semiconductor IP Library for AMBA Interconnect.

The General Purpose I/O Controller provides control and data signals to each I/O pad to select data direction (through separate input and output enables), send or receive I/O signal data, and control the I/O pad for weak pull-up, weak pull-down, and high drive.

Each input pin can be enabled to provide level-sensitive interrupt capabability, with programmable polarity. The interrupt output signal from the General Purpose I/O Controller is the logic OR of all interrupt-enabled inputs.

A functional test feature enables the I/O pins to be controlled and driven by user-implemented test logic, independent of the programming of the GPIO Controller and the state of any alternate function peripherals.

The host interface of the General Purpose I/O Controller complies with the AMBA 2 APB protocol. Control registers within the General Purpose I/O Controller enable per-channel control of general-purpose I/O or alternate function mode, alternate function source selection (A or B), pull-up/pull-down and high drive signalling, and interrupt functionality. Data in/out registers hold the pin input/output data for general-purpose I/O.

FEATURES

16 or 32 I/O channels; each channel corresponds to one off-chip interface pin connected to the General Purpose I/O Controller through an I/O pad

Programmable pin direction

Internal weak pull-up, pull-down

Direct, low-impedance analog input

Read-back on all registers

Each pin may be controlled by other modules through its software-selectable alternate function and alternate source

Selectable high drive current option

Functional test mode to directly control the pad interface signals from user-implemented test logic.

INTERFACES


16 or 32-bit read/write data buses (depending on number of I/O channels)

10-bit address bus

Pads interface to I/O pads

Peripherals interface to on-chip peripherals for alternate functions

Functional test mode interface

Clock interfaceAPB clock

Interrupt signal


DFT signals

MICROPROCESSOR

The ColdFire V4 Core (CFV4CORE) is a high-performance implementation of the ubiquitous ColdFire architecture from Freescale Semiconductor, offering over 500 DMIPS of performance. Fully code compatible with ColdFire V1 and V2 devices, the ColdFire V4 Core offers high-end features such as cache and Memory Management Unit (MMU), plus advanced arithmetic units including hardware divider (DIV), enhanced MAC (EMAC), and an optional Floating Point Unit (FPU).

Like all ColdFire processor cores available from IPextreme, the ColdFire V4 Core is a production-proven design. The ColdFire V4 Core is the same IP implemented in Freescales MCF5441x microcontrollers. By either including or excluding the FPU, you can configure the ColdFire V4 Core to match either the V4e or V4m processor configuration used in Freescale MCF54xx devices. And, like the ColdFire V1 and V2 cores, the ColdFire V4 Core benefits from the extensive ecosystem of development systems, tools, and software supporting the ColdFire architecture.

INDUSTRY-LEADING 32-BIT PERFORMANCE

The ColdFire V4 Core achieves best-in-class 32-bit processor performance through a combination of features including a 9-stage pipeline with limited superscalar (dual-issue) instruction execution. The 9-stage pipeline consists of a 4-stage Instruction Fetch Pipeline (IFP) and 5-stage Operand Execution Pipeline (OEP) decoupled by a FIFO instruction buffer. The optional FPU executes instructions in parallel with the OEP. Separate clocks for the CPU and system bus enable the V4 ColdFire Core to operate at a higher frequency than the rest of the system.

The ColdFire V4 Core achieves 1.54 DMIPS/MHz and can run at up to 345 MHz in a 90-nm process technology.

Local RAM and cache, running at the CPU clock rate, further maximize system efficiency by reducing the overall number of system bus accesses, leaving more system bus bandwidth available for other system resources such as other another processor or DMA controller. The system bus is the industry standard AMBA 2 AHB. The ColdFire V4 Core includes both an AHB master port and an AHB slave port, which enables an external AHB master to access the ColdFire V4 local RAM, either while the ColdFire V4 Core is running or while it is in low-power STOP mode.

APPLICATIONS

Processors based on the ColdFire architecture can be found in over 500 million devices worldwide, powering systems ranging from cameras and printers to robotics and factory automation. The superior performance of the ColdFire V4 Core makes it suitable for the most demanding applications such as high-end home entertainment, network storage, telecommunications, and networked gaming devices. Tightly integrated DIV and EMAC units support DSP-like algorithms for applications such as VoIP. For applications requiring floating-point calculations, the optional FPU provides IEEE-754 compliant floating-point support, operating on 64-bit, double-precision floating-point data and supporting single-precision and signed-integer input operands.

FEATURES

32-bit address and data paths

Variable-length RISC architecture for maximum code density

ColdFire ISA Revision C plus dedicated instructions for integrated arithmetic hardware (DIV, EMAC, and FPU)

Branch acceleration for minimal change-of-flow execution time

Big-endian data organization

Up to 64 KB of local RAM with single-cycle access

Separate instruction/data caches (up to 32 KB each)

MMU with variable page sizes (up to 16 MB)

AMBA 2 AHB system bus with master and slave ports

Master port for ColdFire V4 accesses

Slave port for external AHB master access to ColdFire V4 local RAM

Bootable from local RAM or system (AHB) memory

STOP mode for low-power operation

ColdFire Debug Architecture Revision D+

Background Debug Mode (BDM)

Real-Time Trace (RTT)

Real-Time Debug (RTD)

On-chip, 128-entry trace buffer for low-cost trace over BDM

Fully synchronous, synthesizable, scannable design

MEMORY ARCHITECTURE

The ColdFire V4 Core supports up to 4 GB of physical memory, including system memory accessed through the AMBA 2 AHB system bus and up to 64 KB of local RAM connected directly the processor high-speed local bus for single-cycle access. The size of the local RAM is configurable (specified by input pin value) and may be 0 (no local RAM), 4, 8, 16, 32, or 64 KB.

The ColdFire V4 Core supports separate instruction and data caches, also connected to the processor high-speed bus with single-cycle access. The caches are independently sized, non-blocking, four-way set-associative with 16-byte line sizes. Each cache can be configured to be 0, 2, 4, 8, 16, or 32 KB (also specified by input pin value).

The MMU provides virtual-to-physical address translation using separate, software-managed instruction and data translation-lookaside buffers (TLBs), which are implemented as flip-flops within the ColdFire V4 Core. The MMU supports software-configurable memory page sizes of 4 KB, 8 KB, 1 MB, and 16 MB. The MMU is disabled upon exit from reset and must be enabled by software before it can be used.

Documents

Ip Library for Amba Interconnect