INVESTIGATION OF STATIC AND TRANSIENTCHARACTERISTICS OF 4H-SiC IGBT USING HIGH-K

DIELECTRICS

Thesis submitted in partial fulfillmentof the requirements for the degree of

Masters in Science by Researchin

Electronics and Communication Engineering

by

G VIDYA NAIDU201432658

vidya.naidu@research.iiit.ac.in

International Institute of Information TechnologyHyderabad - 500 032, INDIA

JULY 2017

Copyright c© G.VIDYA NAIDU, 2017

All Rights Reserved

To my family

Acknowledgments

Foremost, I express my thanks and gratitude to my thesis advisors Dr. Sivaprasad Kotamraju andDr. Srivastava Jandhyala for their continuous advice they had provided me during the course of mywork. Without their support and guidance, it would not have been possible for me to continue my work.I would not have reached the completion stage if not for their immense patience with me. Thanks tomy aunt, uncle, and brother Nihar, who were home away from home for me for this entire duration oftime. Thank you for being with me through everything and I will always cherish my memories with youall. This would not have been possible without constant support and motivation of my sister Divya andbrother Sai Krishna. Finally, I dedicate this thesis to my parents for providing me with unconditionallove and having trust in me. I express my deepest gratitude for being with me throughout this journey.

v

Abstract

SiliconCarbide(SiC) is a wide band gap semiconductor with high thermal conductivity, high electronsaturation velocity and high critical electric field properties. Silicon based devices, if replaced by SiCdevices, could reduce the switching losses and improve the power conversion efficiency in grids becauseof their high frequency capability. However, the main limitation of SiC based MOS devices is their in-ability in handling higher electric fields at the oxide interface. An alternative to overcome this limitationis to replace the conventionally used SiO2 with the high-K dielectrics that can sustain high electricfields. High-K dielectrics ZrO2 and HfO2, with a dielectric constant of about 25, have been chosen forthis study, as SiO2, with a dielectric constant of 3.9, cannot sustain high electric fields. This approachhas been attempted earlier with HfO2 as the gate dielectric in the case of SiC power MOSFETs. Previousstudies of SiC MOSFETs with HfO2/SiO2 stacking gate dielectric have shown significant improvementin the electronic performance. The electric field in the high-K dielectrics does not exceed the safe oper-ational value, even when the underneath SiC has exceeds high electric field values. In order to addressthese concerns, an asymmetric trench gate SiC IGBT using high-K dielectrics such as HfO2 and ZrO2

as alternatives to the conventionally used SiO2 has been studied. While supporting high electric fieldis one aspect, in this work it is investigated whether replacement of SiO2 with the high-K dielectricsconsidered has any influence on the switching characteristics of IGBTs such as rise time, fall time, andturn OFF time using TCAD (Technology Computer-Aided Design) simulations.

The static and switching characteristics of the SiC IGBT have been explored using technology basedtwo-dimensional numerical computer simulations. ZrO2 and HfO2 exhibited better forward transcon-ductance ratio and reduced tail current thereby indicating improved power losses. The power dissipationcurves were found to be consistent with the results obtained. However, these high-K dielectrics have lowband offset as compared to SiO2-SiC interface. A lower band offset could lead to a high gate leakagecurrent, which was resolved by introducing a thin layer of SiO2 between SiC and high-K dielectrics.Power dissipation has been analyzed for IGBT with SiO2, HfO2 and ZrO2 layers by applying a pulsesignal. In addition, the power dissipation is simulated for temperature range of 300-600K for differentdielectric layers as the switching performance of a device is supposed to deteriorate with increase intemperature. HfO2 and ZrO2 demonstrated good temperature stability. The work in this paper is anattempt to correlate the power dissipation with the static and dynamic characteristics for the respectiveoxide layers.

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Contents

Chapter Page

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Brief History of SiC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Physical Properties of Silicon Carbide . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2.1 Bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.2 Critical Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.3 Saturated Drift Velocity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.4 Thermal Conductivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.5 Figures of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Structure of Silicon Carbide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3.1 Basic Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3.2 Polytypism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 Challenges for SiC Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.5 High-K Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.5.1 Challenges to MOS Technology Scaling . . . . . . . . . . . . . . . . . . . . . 71.5.2 Need of High-K Gate Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . 71.5.3 Band gap and Dielectric Constant . . . . . . . . . . . . . . . . . . . . . . . . 91.5.4 Thermal Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5.5 Quality of Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.5.6 Evolution of High-K Materials . . . . . . . . . . . . . . . . . . . . . . . . . 101.5.7 Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.6 High-K Gate Dielectrics in SiC UMOSFET . . . . . . . . . . . . . . . . . . . . . . . 11

2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.1 The Introduction of IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2 Insulated Gate Bipolar Transistor (IGBT) . . . . . . . . . . . . . . . . . . . . . . . . 182.3 Basic IGBT Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.4 Trench Gate IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.5 Silicon Carbide IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.6 IGBT: Benefits and Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.7 Packaging of IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.8 Application Spectrum of IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

vii

viii CONTENTS

3 Simulation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.1 Sentaurus Structure Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.1.2 Sentaurus Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.2.1 Basic Sentaurus Device . . . . . . . . . . . . . . . . . . . . . . . . 263.1.2.2 Mixed-mode Sentaurus Device . . . . . . . . . . . . . . . . . . . . 27

3.1.3 TCAD Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.2 Modeling of SiC IGBT in Sentaurus TCAD . . . . . . . . . . . . . . . . . . . . . . . 29

3.2.1 Structure Generation of SiC IGBT . . . . . . . . . . . . . . . . . . . . . . . . 293.2.2 Physics Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.2.3 Maths Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.2.4 Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364.1 Static Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1.1 Stability of Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384.2 Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2.1 Timing Analysis of Output Collector Current . . . . . . . . . . . . . . . . . . 424.3 Switching Power Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.4 Gate Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515.1 Disclaims . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

List of Figures

Figure Page

1.1 Structures of the basic unit of Silicon Carbide crystal. The second structure is 180◦

inverted about c-axis with respect to first structure[2]. . . . . . . . . . . . . . . . . . . 51.2 Illustration of three closely-packed planes of spheres. The first layer is of A spheres. In

the second layer, B spheres occupy the spaces which are the depression of first layer.The third layer consists of C layer occupying depression spaces of B layer. The figureshown is of 3C-SiC structure[2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 The trend of scaling of gate length and oxide thickness in transistors (ITRS InternationalTechnology Roadmap for Semiconductors)[9]. . . . . . . . . . . . . . . . . . . . . . 8

1.4 Dielectric constant vs. band gap for various gate oxides[15]. . . . . . . . . . . . . . . 91.5 Schematic cross section of a classical UMOSFET[2]. . . . . . . . . . . . . . . . . . . 12

2.1 Schematic illustration of an IGBT[38]. . . . . . . . . . . . . . . . . . . . . . . . . . 182.2 Equivalent circuit and symbol of an IGBT[38]. . . . . . . . . . . . . . . . . . . . . . 182.3 Basic IGBT Device Structures[40]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.4 Trench Gate IGBT Structure[40]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.5 Commercially available IGBT Packages[39]. . . . . . . . . . . . . . . . . . . . . . . 232.6 Application Spectrum of Silicon Carbide IGBT[51]. . . . . . . . . . . . . . . . . . . 24

3.1 Structure of project folder[55]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.2 Structure of a Sentaurus Device command file for single device simulation[55]. . . . . 273.3 Mixed-mode Sentaurus Device[55]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.4 Simulation Packages of Sentaurus TCAD[55]. . . . . . . . . . . . . . . . . . . . . . 283.5 Schematic illustration of the SiC IGBT . . . . . . . . . . . . . . . . . . . . . . . . . 293.6 Meshing of the 2D-SiC IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.1 Illustration of the gate dielectric stack made up of 1nm SiO2 and 20nm(actual thickness)high-K dielectrics (HfO2 / ZrO2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.2 Transfer Characteristics of SiC IGBT for different dielectrics and combinations. . . . 374.3 Output Characteristic of SiC IGBT with different dielectrics of actual thickness of 20nm. 384.4 Variation of threshold voltage of the SiC IGBT with temperature (K) for different di-

electrics with actual thickness of 20nm. . . . . . . . . . . . . . . . . . . . . . . . . . 394.5 Variation of SiC IGBT threshold voltage with increasing thickness of interface SiO2

layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.6 Clamped inductive load drive circuitry for the SiC IGBT . . . . . . . . . . . . . . . . 41

ix

x LIST OF FIGURES

4.7 Curent and Voltage waveforms of SiC IGBT depicting Turn ON and Turn OFF times[59]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.8 Path of tailing collector current[61]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 424.9 Switching waveforms of an IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434.10 Turn ON and Turn OFF timings of the SiC IGBT with 20nm SiO2 gate dielectric. . . . 444.11 Dynamic characteristics of the SiC IGBT with 20nm(actual thickness) HfO2 gate di-

electric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.12 Dynamic characteristics of the SiC IGBT with 20nm(actual thickness) ZrO2 gate dielec-

tric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.13 Tail part of collector current magnified and redrawn in fig 4.15 to illustrate the improve-

ment in turn OFF time by using high-K dielectrics. . . . . . . . . . . . . . . . . . . . 464.14 Tail current measurement for different dielectrics of 20nm (actual thickness) at 300 K. 474.15 Power dissipation as a function of time plotted for various dielectrics, obtained at dif-

ferent temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.16 Power Dissipation trend for different dielectrics considered with increasing temperature. 484.17 Gate Leakage current for various gate dielectrics under consideration. . . . . . . . . . 49

List of Tables

Table Page

1.1 Thermal Conductivity of SiC at room temperature[2]. . . . . . . . . . . . . . . . . . . 31.2 Figures of Merit for Si,common SiC prototypes and GaAs[2]. . . . . . . . . . . . . . 41.3 Properties of potential candidates for Gate Dielectrics in SiC UMOSFET(obtained on

the basis of experimental and theoretical data)[2]. . . . . . . . . . . . . . . . . . . . . 13

2.1 Comparison of MOSFETs and Bipolars. The table is taken from ‘IGBT: Theory andDesign’ by V. Khanna[39]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.2 Properties of NPT-IGBTs and PT-IGBTs. The table is taken from ‘IGBT: Theory andDesign’ by V. Khanna[39]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 Timing Analysis of different dielectrics considered in the SiC IGBT. All numbers are innano-seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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Chapter 1

Introduction

Silicon Carbide has proved itself as a superior alternative to commonly used Silicon. It is a boon tothe area of power electronics. SiC devices can operate in severe conditions of high temperatures andelectric field. SiC also exhibits improved efficiency. Due to all these features, the material is gainingmuch interest by worldwide researchers.

1.1 Brief History of SiC

Gallium Arsenide (GaAs) and Silicon (Si) are the first and second-generation semiconductor mate-rials, respectively. Silicon carbide (SiC) is the next generation semiconductor material which is a wideband gap material. SiC was discovered by Berzelius in 1824 while conducting his diamond synthesisexperiment. SiC was first used as an abrasive and then later used in electronic applications. Primitiveradios made use of SiC detectors. On application of voltage to SiC, colorful emissions were observed atthe cathode. Upon this observation, H.J.Round invented a SiC LED in 1907. SiC has many extraordi-nary electronic properties such as larger critical electric field, higher thermal conductivity, higher elec-tron saturation velocity, chemical inertness and radiation hardness. Due to these properties possessed bySiC semiconductor, the material is highly suitable for high-voltage, high-power and high-temperatureapplications. The research of SiC power devices began in the 1970s and remarkable advancement inSiC crystal quality and fabrication technology was achieved by the 1980s. Diverse SiC devices werethen explored and developed. Now, the commercial SiC device production is in the development phaseas the theoretical research of the SiC devices is towards completion stage. Infineon Corporation startedsupplying SiC Schottky diodes 2001 onwards. Today, SiC diodes, MOSFETs, JFTs, BJTs and other SiCdevices are commercially available. CREE, Toshiba, STMicroelectronics and other electronic firms areinto manufacturing of the SiC power devices. The major challenge in the development of commercialSiC devices is the cost factor. The target is to obtain desired quality at a feasible cost which is compar-atively higher than the Silicon process technology. With the ongoing development of the SiC processtechnology, it is possible to obtain 4H-SiC layers(epilayers and substrates) of good quality. For instance,100-mm 4H-SiC substrates and epilayers have already been developed that could be used in the power

1

devices[1]. As massive research is being pursued on SiC materials, huge cost reduction is expected thatwould eventually encourage the growth of SiC power devices.

1.2 Physical Properties of Silicon Carbide

Silicon carbide (SiC) is a semiconductor favoring high-power, frequency and high-temperature ap-plications. Along with properties such as high breakdown electric field strength, high saturated driftvelocity and thermal conductivity, SiC can exist as a native substrate of reasonable size, and it can read-ily be grown. SiC can also be doped by n- and p-types. Similar to Silicon (Si), SiC has SiO2 as its stable,native oxide. This is a very important feature for the semiconductor industry, both from a processingaspect and also for metal-oxide-semiconductor (MOS) technology. Therefore, these properties makeSiC ideally suitable for a wide range of applications[2].

1.2.1 Bandgap

The SiC bandgap varies according to the polytype. The value is between 2.39 eV for 3C-SiC to3.33 eV for 2H-SiC. The most commonly used polytype is 4H-SiC, having a band-gap of 3.265 eV[2].Owing to wide band gap, SiC devices can be operated at high temperatures. In SiC, the electrons donot get thermally ionized from valence band to conduction band due to its wide band gap even at hightemperatures. This has been the major drawback in case of Silicon.

1.2.2 Critical Field

For power-device applications, one of the very important properties is breakdown electric fieldstrength. Breakdown electric field strength the measure of the maximum electric field that the mate-rial can sustain before breakdown takes place. This type of breakdown is also known as catastrophicbreakdown. The maximum electric field for any semiconductor device varies with doping concentra-tion. For a doping of approximately 1E16 cm-3, maximum electric field of SiC is 2.49 MV/cm [3]. ForSi, the value of the maximum electric field is about 0.401 MV/cm for the same doping [4]. By theseresults, the maximum electric field for SiC is six times that of Si and not ten times the higher criticalfield strength, as asserted. The inconsistency is because critical fields between devices having the sameblocking voltage should be compared. Thus, a Si device having a blocking voltage of 1 kV would havea critical field strength of about 0.2 MV/cm, which should be compared with the 2.49 MV/cm of SiCand hence the maximum electric field for SiC is 10 times higher critical field strength than Silicon[2].

2

1.2.3 Saturated Drift Velocity

For high-frequency applications, the property responsible is saturated drift velocity. In SiC, this is2e7 cm/sec, which is twice that of Si[2]. Large channel currents can be attained with high saturated driftvelocity. And hence SiC can be incorporated in high gain solid state devices.

1.2.4 Thermal Conductivity

The thermal conductivity of SiC is the parameter governing power and high-frequency device appli-cations. Physical properties of device change with the rise in temperature which is usually undesirable.Carrier mobility varies inversely with temperature. Resistive losses lead to increased temperature andso operation must thus be conducted away from the device and into the package. At room temperature,the thermal conductivity of copper is less than that of SiC. The thermal conductivity value of SiC ishigher and hence much better than most of metals. Copper has the thermal conductivity value of is4.0 W/(cm-K) and silver of 4.18 W/(cm-K). By in-depth studies, the thermal conductivity of SiC hasbeen determined in different crystal directions. The purity of the crystal and the crystal direction alsodecide thermal conductivity value. With advanced technologies, as a higher-quality material is grown,values close to the theoretical values are measured by methods such as laser flash technique. High-purity semi-insulating (SI) SiC material has the highest reported thermal conductivity with a value of4.9 W/(cm-K)[2]. For the doped crystals, even the lower values of thermal conductivity are above 4W/(cm-K) at room temperature. Table 1.1 shows thermal conductivity of SiC for different directions.

Table 1.1: Thermal Conductivity of SiC at room temperature[2].

Sample Type Direction Carrier Concentration (cm-3) Thermal Conductivity (W/cm-K)4H SI ‖ to c SI 3.34H n ‖ to c 2E18 3.34H n ⊥ to c 5E15 4.86H n ‖ to c 1.5E18 3.06H n ‖ to c 3.5E17 3.26H n ⊥ to c 3.5E17 3.86H p ⊥ to c 1.4E16 4

6H slack ⊥ to c 1E17 5

1.2.5 Figures of Merit

It is necessary to have some measure for comparison of material and their properties for power andhigh-frequency purposes. To enable the assessment, Johnson proposed a figure of merit, and henceJohnson Figure of Merit (JFOM). JFOM predicts the power bearing capability and high- frequencycompetence of a device. The JFOM takes into consideration the critical field and saturated drift velocity,as shown in the following mathematical equation[5]:

3

JFOM =E2Bvsat

2

4π2(1.1)

where EB and vsat are the critical field strength and saturated drift velocity, respectively. Not be-ing satisfied with the JFOM ability to take into consideration the material thermal properties, Keyesintroduced another figure of merit, the Keyes Figure of Merit (KFOM) [6]:

KFOM = κ

√cvsat

4πε(1.2)

where κ, c, and ε are the thermal conductivity, the speed of light in vacuum, and the dielectricconstant, respectively. None of the above formulae was found to be accurate for power devices andBaliga came up with a figure of merit for low-frequency applications, called the Baliga Figure of Merit(BFOM)[7]:

BFOM = εµE3B (1.3)

where µ is the carrier low-field mobility. Table 1.2 lists the figures of merit for SiC polytypes, Si andGaAs semiconductors. All values are with respect to Si.

Table 1.2: Figures of Merit for Si,common SiC prototypes and GaAs[2].

Material JFOM KFOM BFOM

Si 1 1 1

GaAS 9 0.41 22

6H-SiC 900 5 920

4H-SiC 1640 5.9 1840

1.3 Structure of Silicon Carbide

1.3.1 Basic Structure

SiC has a crystalline structure. The constituent unit of the crystal of Silicon carbide is of tetrahedronstructure consisting of four carbon atoms with a Silicon atom at center(Figure 1.1). There also exists asecond type rotated 180◦ with respect to the first. Carbon and Silicon atom are separated by 1.89A andthe Carbon atoms by 3.08A. The crystalline structure is formed by joining these units at the corners[2].

4

Figure 1.1: Structures of the basic unit of Silicon Carbide crystal. The second structure is 180◦ invertedabout c-axis with respect to first structure[2].

1.3.2 Polytypism

Silicon carbide displays 2D polymorphism called polytypism. All polytypes have a hexagonal struc-ture of SiC bilayers. The hexagonal structure can be imagined as layers of similar spheres touching eachother, as depicted in Figure 1.2. All the layers are similar for all lattice planes. However, the planesare so placed above or below the other plane such that to fit in the groove of the adjacent layer in aclose-packed arrangement. Thus, there are two inequivalent positions for the adjacent layers of the SiCstructure. By assigning names to the possible combinations as A, B and C, polytypes can be constructedby positioning them in a specific repetitive manner. The cubic polytype that can be formed in SiC is 3C-SiC, which has ABCABC... stacking sequence. 2H-SiC has a stacking sequence ABAB... 6H-SiC hasstacking sequence of ABCACBABCACB...and 4H-SiC has stacking sequence ABCBABCB... 6H-SiCand 4H-SiC are very important and most often used polytypes.

In the SiC notation, C stands for cubic, H stands for hexagonal and R stands for rhombohedra. Allthese polytypes of the SiC consist of same ratio of Silicon and carbon atoms, but due to the variationin stacking sequence between planes, the electronic and optical properties vary. The bandgap is, forexample is 2.39 eV for 3C-SiC, 3.023 eV for 6H-SiC, and 3.265 eV for 4H-SiC[2].

Compared to 6H-SiC, 4H-SiC has higher carrier mobility for both holes and electrons, shallowerdopant ionization energies, and lower intrinsic carrier concentration. In addition, 4H-SiC has an intrinsicadvantage over 6H-SiC for vertical power device configurations because it shows much lower electronmobility anisotropy(0.83) compared to 6H-SiC(∼5) [8]. Along with superior electrical characteristics,rapid advancements in processing techniques of 4H-SiC have enabled adoption of the 4H polytype asthe preferred SiC polytype.

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Figure 1.2: Illustration of three closely-packed planes of spheres. The first layer is of A spheres. Inthe second layer, B spheres occupy the spaces which are the depression of first layer. The third layerconsists of C layer occupying depression spaces of B layer. The figure shown is of 3C-SiC structure[2].

1.4 Challenges for SiC Power Devices

To reduce or eliminate the defects is a complex task for SiC, which is the key issue restricting thewafer dimension. There has been a significant development in reducing and eliminating defects density.Cree has been manufacturing 4-inch SiC wafers with zero micro-pipe since 2007. Now, the dislocationeffects are being researched upon so as to minimize the defects. Some of the dislocation effects arescrew dislocation, basal plane dislocations, edge dislocation and other defects on the characteristics ofthe devices.

The critical issues faced by SiC power devices are low carrier mobility in the channel and reliabilityof gate oxide at high temperatures and/or electric fields. The recently noted electron mobility is 30-250 cm2/V-s, which does not allow the SiC MOSFET benefits to be utilized. So, new gate oxidationtechnologies are required in order to eliminate the SiC/SiO2 interface defects and boost the electronmobility in the inversion layer. Post-oxidation annealing in the H2 environment, and gate oxidation orannealing in NO or N2O environment are the few methods.

The packaging of SiC power devices is also a major concern. The packaging affects the circuitperformance once the material and process challenges are dealt with. Packaging reliability is very im-portant for the devices operating at high temperatures(≥ 200◦C). Also, coolant temperature is requiredfor an operating temperature above 150◦C. For example, the engine coolant used by automotive motordrives, oil and gas drilling and extraction, avionics power supplies, space power supplies, and militaryapplications etc. By increasing the power handling capability expensive chip area and cooling cost canbe reduced. Thus, new packaging materials are required which can withstand the harsh conditions[1].

6

Switching power can be minimized by boosting the frequency of switching. When SiC power devicesare applied in the fast switching arena, the internal electromagnetic parasitic issues between the deviceand package arise which significantly affect the performance.

In SiC power devices, the effect of high electric field in all the materials included in the deviceshould be considered. As a high electric field develops inside the device, the electric field developed inthe dielectric layer and at the surfaces of the chip is very high. The electric field at the interface terminaledge is approximately three times higher than the SiC diode. With such high surface electric fields,any contamination in the form of particles or mobile ions may lead to possible electrochemical drivencorrosion processes. Any material defect in the passivation layers and any delamination could becomeextremely critical and thus making the insulation technology advanced becomes very essential[1].

1.5 High-K Dielectrics

1.5.1 Challenges to MOS Technology Scaling

The success of modern integrated circuits could only be accomplished by the persistent efforts toreduce the size of MOS transistors. By the reduction in the size of these devices, the package densitiesincreased which also lead to increased circuit speed and decreased power dissipation. This advancementwas obtained by scaling down the gate dielectric physical thickness(Tox) and length of gate(LGATE)[9].From Fig 1.3[9], it can be seen that, the rate of scaling of the LGATE and Tox reduces with technologynodes. Silicon oxide (SiO2) is the most commonly used gate dielectric because of the various fascinatingproperties it offers. The properties are excellent interface compatibility, thickness controllability, highthermal stability and good reliability. SiO2 has reached its physical limitations for the newer MOSnanotechnologies (where gate length is less than 90nm) due to which higher leakage current issues andreliability concerns have arisen. For the thickness of 11-15A electrons can directly tunnel through theoxide, leading to excessively high gate current or leakage current. Leakage current is an importantparameter as it affects the power consumption of the device. For high gate leakage current, the staticpower can exceed the active power. In-order to limit the increase in active power, VDD needs to belimited[10].

1.5.2 Need of High-K Gate Dielectrics

Silicon dioxide (SiO2) has been the conventionally used gate oxide from a long time. As the transistorsize decreases, the gate oxide thickness is also reduced which leads to a rise in gate capacitance value.As a result the drive current increases, further improving the device performance. Up to oxide thicknessof 2nm the device operation is reliable. But as oxide thickness of the device is scaled below 2nm, theleakage currents shoot up as a consequence of tunneling. Higher leakage currents also lead to increasedpower consumption and lower device reliability.

7

Figure 1.3: The trend of scaling of gate length and oxide thickness in transistors (ITRS InternationalTechnology Roadmap for Semiconductors)[9].

While using high-K dielectrics, a thicker layer can be included, that could lead to reduced parasiticcapacitance. By using high-K dielectrics instead of the Silicon dioxide as the gate oxide, the gate capac-itance can be increased without deteriorating the leakage currents. Silicon dioxide (SiO2) is commonlyused as a passivation layer to protect device surface from any gate dielectric process. SiO2 can be grownon top of SiC surface by thermal oxidation. The basic inherent limitation of using SiO2 as gate dielec-tric in SiC devices is the dielectric constant, which is nearly 2.5 times lower than that of the SiC. Theinterface compatibility of SiO2 with SiC is also very poor. As a result of dielectric mismatch, very highelectric field develops in the dielectric layer as compared to that in the substrate layer beneath. Hence,dielectrics with dielectric constant similar to SiC material and lower interface state densities(Dit) aredesired for device applications[11]. Due to the gap in dielectric constants value, the device operationis limited to electric fields much lower than the SiC material critical field strength so as to avert thepremature breakdown of SiO2.

Various oxidation nitridation methods have been adopted to improve SiO2/SiC interfaces for MOS-FETs(and for BJTs as well). But the commercialization is still limited by low channel mobility dueto a high interface state density near the conduction band. The interface density at the interface of theSiO2/SiC is at least two to three orders of magnitude higher (1012 eV-1 cm-2) compared to the relativelymatured Si/SiO2 interface[12]. The basic essential features of a dielectric are good insulating and ca-pacitive properties. Gate dielectrics are often stacked together and when stacked they should have thecapability to avoid diffusion of n-type and p-type dopants. It is also desired that gate dielectric materialshave fewer electrical defects as the defects affect the breakdown performance. The other features of

8

gate dielectric materials are good thermal stability, high recrystallization temperature, sound interfacequalities etc[13].

1.5.3 Band gap and Dielectric Constant

As far as capacitance performance is concerned, the dielectric constant(K) of gate dielectric materialshould be greater than 12. The most preferred range is 25 to 30[13]. An optimum value of k signifiesreasonable physical thickness of the dielectric. An optimum value is very important as thinner gateoxide will lead to gate leakage and too thick will hinder physical scaling. In MOS technology, a veryhigh k-value is not desirable as they can lead to large fringing fields at the source and drain regions[14].Fig. 1.4[15] shows that the k values of some oxides vary inversely with the band gap, so a relatively lowk value is needed. So, a compromise needs to be done between bandgap and dielectric constant.

Figure 1.4: Dielectric constant vs. band gap for various gate oxides[15].

1.5.4 Thermal Stability

In the current MOS technology processes, gate dielectric stacks are subjected to rapid thermal an-nealing(RTA) for 5secs at 1000◦C. So, the thermal and chemical stability of the gate dielectrics and alsowith the materials in contact is very essential.

9

Lanthanides and group II, III, IV elemental oxides having high heat of formation with respect toSiO2 could be of use. Examples of these oxides are as SrO, CaO, BaO, Al2O3, ZrO2, HfO2, Y2O3,La2O3[13]. Moreover, group II oxides are reactive with water and hence are not preferable. Thus, asfar as thermal stability of dielectric materials is concerned, only Al2O3, ZrO2, HfO2, Y2O3, La2O3,Sc2O3 and some lanthanides such as Pr2O3, Gd2O3 and Lu2O3 are suitable [12]. Some materials withhigher heat of formation than SiO2 may also be slightly reactive with Si such as ZrO2 , forming thesilicide, ZrSi2 [16, 17]. Among all the favorable high-k dielectric materials, HfO2 is highly suitable asit possesses both high dielectric constant(K) value and is chemically stable with H2O and Silicon.

1.5.5 Quality of Interface

The interface quality can lead to high fixed charge density, causing a huge shift in the flat bandvoltage (Vfb), severely affecting the performance and reliability of the MOS transistor. Mostly high-kdielectric materials have Dit ∼1011 to 1012 eV/cm2, exhibiting considerable flatband voltage variationmore than 300 mV[18]. So, it is very important to improve the interface quality.

The interface bonding configuration is quite important. SiO2/Si interface has high quality interface.The properties of this high quality interface can be made use of even with the inclusion of high-kdielectrics. Different high-k material can be used on top of the interfacial layer[13]. By sandwichinga thin SiO2 layer between Si and high-k dielectrics, the critical and high-quality nature of the SiO2/Siinterface can be preserved, while providing a higher-k gate dielectric simultaneously.

1.5.6 Evolution of High-K Materials

To deal with gate leakage issues and extend the benefits of SiO2 dielectrics, Nitrogen is introduced inSiO2 material. Many ways exist by which Nitrogen can be incorporated into SiO2. Some of the methodsare obtaining a Nitride-oxide stack structure by post deposition annealing in Nitrogen atmosphere. Bythe introduction of Nitrogen into SiO2, the dielectric constant value increases and the resultant dielectricbehaves as a better barricade preventing boron penetration. Moreover, by using the Nitride/Oxide stackstructure, good quality of interface between the Oxide and substrate can be maintained[19, 20]. In spiteof the enormous development in-case of SiO2, the dielectric constant of the oxynitrides is still very lowand thus comparatively thicker layer is required so as to prevent direct tunneling of the current. Andhence, dielectric materials having high-K dielectric constant are being explored upon so as to avoid tun-neling current for the same dielectric thickness. The required capacitance value for given thickness canbe obtained by using high-K dielectrics[21]. Oxides of group II, III, IV namely Al2O3, Y2O3, La2O3,Sc2O3 and some lanthanides such as Pr2O3, Gd2O3 and Lu2O3 are the potential dielectrics having high-K values. The shortcomings imposed by low power applications, scalability of MOS transistors, orreactions with the substrate restrict their usage as gate dielectrics. The only suitable high-K dielectricssatisfying all the above criteria are oxides and silicates of Hf and Zr. So the hunt of alternative gate di-electrics has been shortlisted to HfO2, ZrO2 and their silicates due to the excellent electrical properties

10

they offer and high thermal stability while in contact with Silicon[22]. Although, another complication,i.e. low crystallization temperature, is related to the oxides of Hf and Zr. HfO2 and ZrO2 easily crys-tallize under standard MOS processes. Due to these crystalline structures, the gate leakage can increaseby folds of magnitude and provide way for diffusion of dopants leading to dielectric breakdown. Tilldate, efforts are being taken to improve the crystallization temperature of these oxides. Elements suchas N, Si, Al, Ta and La are being incorporated into these high-k oxides to obtain higher crystallizationtemperature. Hf-based oxides have high preference over Zr-based oxides as the crystalline temperaturefor Hf-based oxides is relatively higher[13].

1.5.7 Defects

While the high-K oxides are deposited, bulk defects arise which severely affect the device perfor-mance. The number of fixed charges due to defects increase sharply. The trapped charges in the defectscause the threshold voltage of the MOS transistor to vary. The threshold voltage being the primary mea-sure of performance gets affected due to the traps. Also, the trapped charges are time variant and thusthe threshold voltage also varies with time. This leads to negative bias temperature instability (NBTI)and positive bias temperature instability (PBTI) in the device.

Due to trapped charges, the charge carriers in the channel are also scattered causing lowered carriermobility. Additionally, these defects are the beginning of electrical failures and dielectric breakdown[13].These defects house excessive or deficient oxygen, impurities, etc. Most high-k dielectric oxides com-monly have more interface defects and bulk defects when in contact with substrate as compared toSiO2[23]. Studies are being pursued to resolve the defect density concerns.

1.6 High-K Gate Dielectrics in SiC UMOSFET

The classical U-groove n-channel power MOSFET transistor (UMOSFET) in SiC is a vertical device,comprising of grown thick n- drift region and p-type base region grown by epitaxy. The N+ source andP+ body contact regions can be either grown by epitaxy or ion implantation. Dry plasma etch can beused to form a trench, and a thin dielectric layer is then thermally grown or deposited followed bymetal or polySilicon gate deposition to define a vertical MOS channel. The schematic of n-channelUMOSFET device structure is shown in Figure 1.5. 4H-SiC UMOS transistor structure offers severaladvantages over other transistor designs. Some of them are as follows:

[1] Vertical configuration, As the JFET region is absent in vertical configuration, maximum advan-tage can be obtained from the fine blocking/conductive properties of the SiC drift layer[24];

[2] As it is a simple structure, it can be fabricated by self-aligned fabrication process that in-turnwould lead to significant rise in channel packing density;

[3] By epitaxial growth, all the different doping concentrations of the device structure can be realized.

11

Figure 1.5: Schematic cross section of a classical UMOSFET[2].

Particularly, a detailed analysis of the performance, advantages and limitations of 4H-SiC powerUMOSFET structure has been made by Agarwal in 1996 [25]. The main issues addressed in his workwere:

[1] The On-state dielectric reliability due to much smaller conduction band offset of SiC to SiO2 ascompared with that of Silicon [25, 26, 27];

[2] High electric field in the gate dielectric in Off-state due to electric field intensification at the edgesof the U-shaped trenches;

[3] Low inversion channel mobility on the vertical sidewall of the trench part due to high interfacedensity at the P-SiC/SiO2 interface and high fixed charge density in the insulator.

Assuming that the entire reverse voltage drop occurs over the drift region, the minimal drift regionresistance value offered by UMOS is:

RdrMIN(Vb,Eb) =27Vb

2

8ε0εrµEb3

(1.4)

where Vb is the blocking voltage of the device , Eb is the maximum electric field, µ is low-fieldelectron mobility , εo and εr are the dielectric permittivity of vacuum and the relative dielectric constantof semiconductor (9.8 for 4H-SiC), respectively[2].

As can be seen from equation 1.4, the minimum on-state resistance is inversely proportional to thethird power of the maximum electric field in SiC. And in UMOSFET structure, to satisfy Gauss’ law(∆.ε ε0 E = 0), the product of the relative dielectric constant and the normal field of two materials

12

should be constant at the interface which implies that the electric field in the gate oxide would be 2.5times greater than the underlying SiC layer. As the operating electric field of thermally grown SiO2 islimited to 2 MV/cm [25], the maximum field in the underlying SiC layer should be less then 0.8 MV/cm,which is only 20 % of its critical value. From equation 1.4, it can be seen that this limitation leads to thedrift region resistance of the 4H-SiC UMOSFET with SiO2. since the gate dielectric is 64 times higherthan its theoretical minimum. Due to this reason, the inherent advantages of SiC UMOS transistors aresubdued over Silicon counterparts. And hence to resolve this issue alternative gate dielectrics have tobe found, which satisfy the relation[2]:

εo,oxideεop,oxide ≥ εo,SiC ≈ 30MV/cm (1.5)

Several publications [27, 28, 29] have discussed the benefits and limitations of incorporating high-kdielectrics as gate oxides in power SiC UMOS transistors. A comparative analysis of different gatedielectrics in SiC MOSFETs has been done earlier in 1998 by Lipkin and Palmour [29]. Recently,various emerging high-k dielectrics have attracted attention to be used as gate insulators in the upcominggeneration of Si MOS logic(e.g. [30]).

Table 1.3: Properties of potential candidates for Gate Dielectrics in SiC UMOSFET(obtained on the

basis of experimental and theoretical data)[2].

Material Dielectric Constant(εo) Critical Field Operating Field(Eop) εoEop

(MV/cm) (MV/cm)

SiC 10 3 3 30

TiO2 30-40 6 ∼0.2 ∼6-8

Ta2O5 25 10 ∼0.3 ∼7.5

SiO2 3.9 11 2 7.8

Si3N4 7.5 11 2 15

HfO2 20-40 ∼5 ∼2.6 ∼52-104

The experimental and theoretical data for several dielectric materials having high dielectric constant,including one of the most promising, HfO2 are listed in table 1.3. The product of the relative dielectricconstant and the operating field of hafnium dioxide (HfO2)is much higher than that of SiC (Table 1.3),which potentially makes it an ideal gate dielectric in power SiC UMOSFETs. Till now only a fewattempts have been made exploring the use of high-k dielectric materials as the gate dielectric in SiCdevices(e.g., [29, 31, 32]).

13

The discontinuous junction formed at sharp corners of gate trenches is a major concern in designingof the SiC UMOS transistors. As a result, the maximum electric field in SiC bulk increases drastically.Lightly doped, thicker drift region is required to meet oxide reliability condition, which leads to re-markable increase in the device ON-state resistance. With increasing depth of the trench section in then-drift layer, the electric field intensifies at the corner of trench gate. By using high-k gate dielectric, theelectric field can be moderated at trench gate corner with the same gate control. Additionally, by usingspecial plasma etch rounded trench corners of the U-groove gate can be obtained which would reducethe factor of field enhancement.

By 2D numerical simulations of a 1.2-kV 4H-SiC UMOSFET with a 600-A layer of HfO2 as gatedielectric, it has been confirmed that high-k gate dielectrics in SiC UMOS transistors are beneficial. Asexpected, the electric field in the HfO2 gate does not go beyond the safe operational value even when theelectric field in the underneath 4H-SiC layer becomes 2.8 MV/cm. The electric field enhancement canbe avoided by using trench gate with rounded corners. By minimizing the electric field in the dielectricto its safe value along with improved blocking capability of 4H-SiC, allows for the achievement of driftregion resistance close to its theoretical minimum value.

To avoid premature gate dielectric breakdown, thicker dielectric layer at bottom of trench is desirableto limit electric field in oxide layer. The sidewall thickness of the oxide in the trench part has to besmall enough to obtain a reasonable value of threshold voltage. While in case of thermally grownSilicon dioxide gate dielectric, the situation is reverse. Since the oxidation rate on sidewalls of thetrench is almost five times higher than that on the Si-face on the bottom, sufficient oxide breakdownstrength can be achieved only at the expense of threshold voltage, which may rise to very high values.To overcome the problem of anisotropic oxidation, a thin polySilicon layer can be initially depositedand then converted into Silicon dioxide, resulting in uniformly thick gate dielectric across the trench[33, 34]. Another way to resolve this problem might be a high-k gate dielectric deposited using spin-ontechnique. This approach can be highly beneficial, because in this case the corners will be filled witha dielectric, providing extra protection in the regions of the highest electric field. A serious concernassociated with the use of high-k gate dielectrics in SiC power MOSFETs is the very low conductionband offsets between SiC and high-k metal oxides compared with Silicon dioxide.

One of the most important factors limiting commercialization of power SiC MOSFETs is channelresistance of the MOS that results from the extremely low inversion channel mobility in 4H-SiC [35].This problem may become especially significant in the case of 4H-SiC UMOSFETs, where the oxide-semiconductor interface is severely damaged by plasma etch when the trenches are formed. In general,there are two major approaches to minimize the channel component of on-resistance:

[1] Improve channel mobility,

[2] Increase channel packing density.

Higher channel packing density can be obtained either by use of high- precision lithography or/andby implementing self-aligned fabrication process. As very few power SiC switches and devices are

14

manufactured, it may not be possible to incorporate expensive photo-lithographic equipment. On theother hand, unlike double-diffused MOSFET (DMOS) configuration, SiC UMOS transistor structure isideally suitable for self-aligned fabrication processes that can be adopted by the Silicon industry. Forexample, scaling down a pitch width from todays 15 µm[36] to 1 µm is very realistic. Such increasein the channel packing density would be equivalent to a 15-fold increase in inversion channel mobility,which may not be feasible in the near future. Another benefit that can be realized from downscalingthe pitch width is the reduction of the electric field in the gate oxide. It has been shown in Ref. [37]that by closely spacing the UMOS trenches, the electric field enhancement at the trench corners can bepartially eliminated, which allows the use of thinner and heavier doped drift region. So the increase inthe packing density is a powerful tool to reduce the overall resistance of the UMOS structure.

From reference, it was concluded that Silicon dioxide is incompatible with Silicon carbide in UMOSconfiguration. Various transistor designs designed so as to avoid high electric field intensification inSiO2 gate dielectric layer in SiC UMOSFETs resulted only in complicated transistor structures, insteadof resolving the major problem of incompatibility of the products of the dielectric constants and oper-ating electric fields ε0Eop for SiC and SiO2. Use of high-k dielectric materials such as HfO2 for thegate dielectric are expected to realize the inherent advantages of SiC as a building material for powerUMOSFETs over other semiconductors[2].

15

Chapter 2

Literature Review

2.1 The Introduction of IGBT

Power MOSFETs were thought to be a challenge to the power bipolar transistors. In high frequencycircuits, power MOSFETs in-particular are useful for high speed switching applications. But, due tohigher ON state resistance per unit area in MOSFETs, the ON state losses are also higher. This isespecially true in case of high voltage devices (>500V) which limit the utilization of MOSFETs in lowvoltage and high frequency circuits (eg. SMPS). The features of MOSFETs and BJTs are compared intable 2.1[38].

Due to the above factors it was concluded that power MOSFETs were not a superior option to replacethe BJT and hence attempts were made to blend the two technologies and obtain a hybrid device structurehaving high input impedance and low ON state resistance.

In the initial attempts, npn BJT and MOSFET were connected in Darlington configuration such thatthe input MOSFET drives the output npn BJT. For this, a high voltage power MOSFET with appreciablecurrent carrying capability is desired in order to overcome low current gain of the output npn bipolartransistor. Additionally, as there is no pathway for the negative base current for the output npn bipolartransistor, the turn off time increases.

An alternative approach was pursued at GE Research center. The latch up of a four layer thyristorwas triggered by MOS gate structures. Still, this device could not be an alternative to BJT, as the devicecould no longer be controlled by gate once it latched up.

After lot of research, it was understood that, MOSFET and BJT device technologies need to becombined at the basic level to obtain better results. This was done by the GE Research Laboratory bythe introduction of the device IGT and by the RCA research laboratory with the device COMFET[39].The IGT device was improvised many times to procure the modern Insulated Gate Bipolar Transistor(IGBT). These devices have almost ideal performance for high voltages (above 100V) and mediumfrequency (below 20 kHZ) applications. IGBT along with the MOSFET(at low voltage high frequencyapplications) are capable in wiping out the BJT completely[39].

16

Table 2.1: Comparison of MOSFETs and Bipolars. The table is taken from ‘IGBT: Theory and Design’

by V. Khanna[39].

S.no MOSFET Bipolar

1 Single-carrier device Two-carrier device

2 Operates by majority carrier drift Works by minority-carrier diffusion

3 Voltage driven Current driven

4 Drain current ∝ channel width Collector current ∝ emitter length

5 Higher breakdown voltage is achieved using

lightly doped drain region

Higher breakdown voltage requires lightly

doped collector region

6 Current for particular voltage is higher at

lower voltages and lower at higher voltages

Current for given voltage drop is medium,

and severe trade-off exists with the switching

speed

7 Square-law current-voltage characteristics at

low current and linear I-V at high current

Exponential I-V characteristics

8 Negative temperature coefficient of drain cur-

rent

Positive temperature coefficient of collector

current

9 No charge storage Charge stored in base and collector

10 High Input Impedance Low Input Impedance

11 Minimal drive power. No DC current required

at gate

Large drive power. DC current needed at base

continuously

12 No thermal runaway Prone to thermal runaway

13 Less susceptible to second breakdown Vulnerable to second breakdown

14 Maximum operating temperature 200◦C Maximum operating temperature 150◦C

15 Very low switching losses Medium to high switching losses depending

on trade-off with conduction losses

16 High switching speed, which is less

temperature-sensitive

Lower switching speed, which is more sensi-

tive to temperature

17 High ON resistance Low ON resistance

18 Low transconductance High transconductance

17

2.2 Insulated Gate Bipolar Transistor (IGBT)

Figure 2.1: Schematic illustration of an IGBT[38].

The point of difference of IGBT and corresponding MOSFET cell structure is the P+ layer or in-jecting layer. A PN junction is formed between drain and injecting layer and minority charge carriersare injected into drain region. The drain region has two levels of doping. The N-drain region whichis lightly doped is called the drain drift region and the heavily doped N+ region is called the bufferlayer. The doping concentration and thickness of drain layer determine the forward blocking voltageof the IGBT which in-turn depends on the reverse break-down voltage of J2 junction. The ON statevoltage drop stays unaffected due to conductivity modulation effect. This design of the IGBT is calledPunch Through(PT) design. The N+ buffer layer is absent in the Non-Punch Through(NPT) design. ThePT-IGBT offers low ON state voltage drop as compared to the NPT-IGBT in particular for low voltagedevices. However, it is obtained at the expense of lower reverse break down voltage of the device, as thereverse break down voltage of the junction J1 is small. A PT-IGBT is shown in fig 2.1[39].

The rest of the device design is analogous to that of a vertical MOSFET along with the insulatedgate structure and the shorted body (P type) emitter (N+ type) structure. The doping concentration and

(a) Equivalent Circuit (b) Symbol

Figure 2.2: Equivalent circuit and symbol of an IGBT[38].

18

physical geometry of the p-type body region however, is substantially different from that of a MOSFETin order to overcome the latch up process of a parasitic thyristor embedded in the structure of IGBT.Figure 2.2 shows the approximately equivalent circuit and the circuit symbol for an IGBT[39].

2.3 Basic IGBT Designs

Basically there are two types of IGBT device structures, namely Non Punch Through(NPT) andPunch Through(PT) devices. These are also known as symmetric blocking and the asymmetric blockingIGBTs. The symmetric blocking IGBT device supports high voltage in the first and third quadrant. Thisdesign of the device offers high forward and reverse blocking capacity. This feature is very much desir-able for power devices in high-voltage AC power applications. On the contrary, asymmetric blockingdevice structure can support high voltage only in the forward blocking mode. This structure is optimizedfor applications that utilize a high-voltage DC power bus. The N-buffer layer present in the asymmetricIGBT allows reduction of the N-drift region thickness by which on-state voltage drop and switchingtime can be improved. Figure 2.3 shows IGBT device structure for both symmetric and asymmetricdevices[40]. Table 2.2 compares various features of punch through(PT) and non-punch through(NPT)IGBTs.

Figure 2.3: Basic IGBT Device Structures[40].

19

Table 2.2: Properties of NPT-IGBTs and PT-IGBTs. The table is taken from ‘IGBT: Theory and Design’

by V. Khanna[39].

S.no Feature NPT-IGBT PT-IGBT

1 Process technology

and feasibility

Fabrication using diffusion

method. Less expensive.

Manufactured in an N-epitaxial

wafer. More expensive.

2 Buffer region and Base

layer

Thick N base. No N-buffer

layer. Space charge spreads

across the wide N-base to with-

stand the voltage. NPT structure

provides bidirectional blocking

capability.

Thin N base. N-buffer layer

is present. Broad N-base is

not required as the depletion re-

gion penetrates into the buffer

region. PT-IGBTs have lower

reverse blocking capability.

3 Carrier lifetime in base

region and conductiv-

ity modulation

High carrier lifetime leading to

lower forward drop.

Lower lifetime able to provide

adequate conductivity modula-

tion as the N base is thin. For-

ward drop is determined by the

carrier lifetime in N-base and the

injection efficiency of P+ sub-

strate.

4 Collector doping and

turn-off time

Collector is lightly doped (P

only). Electron back injection

from N-base into P collector

gives satisfactory turn-off time.

Heavy doped collector (P+).

Lifetime killing in N base is nec-

essary to achieve the required

turn-off time. Injection effi-

ciency reduction of the P+ sub-

strate by the buffer layer makes

its fall time and the current tail

shorter.

5 Turn-off loss Less temperature-sensitive. More temperature-sensitive.

6 Thermal stability High Low

20

2.4 Trench Gate IGBT

The structure of trench-gate IGBT device is illustrated in Fig. 2.4. A trench is created by etchingthe upper surface of IGBT. The gate oxide is placed in the trench region which isolates gate from thesemiconductor substrate. The trench-gate structure is also known as U-metal oxide semiconductor (U-MOS) gate structure as the shape of the trenches etched in the semiconductor is similar. Under positivecollector voltage application, the trench-gate IGBT structure supports voltage at the reverse biased J2junction(Fig 2.4). To turn on the IGBT, a channel is created in the P-base region on the vertical surfaceof the trench[40].

Figure 2.4: Trench Gate IGBT Structure[40].

Through the channel the electrons are transported from N+ emitter to the N-drift region. This be-comes the base current which drives the PNP bipolar transistor in the IGBT structure. The basic principleof operation of the trench gate IGBT structure is the same as that for the D-MOS IGBT structure. Alower ON-state voltage drop can be obtained by the trench-gate structure because of smaller cell-pitchand elimination of the junction field effect transistor (JFET) region. By deep trenches, lower on-statevoltage drop can be obtained due to improved minority carrier profiles. These deep trench gate IGBTstructures are called injection-enhanced IGBTs (IEGTs) [40].

21

2.5 Silicon Carbide IGBT

To utilize the high breakdown field strength property of SiC material, power devices with SiC arebeing explored. The specific ON resistance of the drift region of the vertical power device structure isbased on some of the semiconductor properties which is given by[41]:

RON−Specific =4BV 2

εsµnE3c

(2.1)

where BV is the breakdown voltage, εs is the dielectric constant, µn is the electron mobility, and Ec

is the critical electric field for breakdown. The denominator of the equation is the Baliga’s Figure-of-Merit (BFOM) for semiconductors. Based upon previous knowledge on the Silicon carbide properties,a BFOM of approximately 2000 is predicted for the 4H-SiC polytype [42]. SiC-based IGBTs have thebenefit of a smaller drift region width, due to which reduced on-state voltage drop and the reduced storedcharge are observed. The development of n-channel SiC IGBTs was obstructed by the high resistance ofthe P-type substrates which must behave as collector region. Subsequently, p-channel, asymmetric SiCIGBTs were first designed with 9.9 kV to 12 kV forward blocking capability using thick p-type regiongrown on n-type substrates with high doping concentration[43, 44, 45]. A channel mobility of 6.5cm2/V-s was observed for holes in these devices. Asymmetric n-Channel SiC IGBTs were subsequentlydeveloped [46] with blocking voltage of 13 kV. A electron channel mobility of 18 cm2/V-s was found inthese devices. The study of 15 kV symmetric blocking IGBTs[47] showed that the performance of thesedevices is as good as the asymmetric devices. The blocking voltage for p-channel asymmetric 4H-SiCIGBTs has been extended to 15 kV[48]. For blocking voltages higher than 9 kV, the performance ofN-channel IGBT is found to be superior than SiC power MOSFETs for motor drive applications[49].By this study, the highest MVA rating for the N-channel SiC IGBT structure can be be obtained at ablocking voltage around 20 kV[41].

2.6 IGBT: Benefits and Limitations

IGBT is obtained by combining the MOS and bipolar transistor technologies in monolithic form. Itintegrates the finest characteristics of MOS and bipolar device families in-order to obtain optimal deviceattributes, roughly conforming the benchmark of an ideal power switch.

Additionally, no integral diode exists in IGBT as in MOSFET. As no diode is present, the userscan choose an external fast recovery diode suitable for a particular application or purchase a ”co-pak”having IGBT and diode in the same package. Also, in an IGBT, issues related to diode junctions suchas the P-base and N-drift junctions are absent. The major challenge while using MOSFET is the reverserecovery characteristic of the diode. In MOSFETS, charge carriers have high carrier lifetime in theN-drift region which slows down the reverse recovery of diode slow along with large recovery charge.For higher voltage ratings, due to the existence of integral diode in MOSFET, the reverse recovery

22

charge and reverse recovery time are higher and thus the losses are also higher. High reverse recoverycurrents are produced increasing the di/dt, due to the high charge. And due to the high current throughthe transistors, power dissipation and thermal stress increases. To obtain improved reverse recoverycharacteristics, electron irradiation is applied along with subsequent annealing of positive oxide chargeat a temperature around 200◦C. Even after the processing, the integral diode in the MOSFET causesproblems due to the presence of a bipolar transistor in the structure. The voltage drop developed acrossthe base resistance of the bipolar transistor in the structure is due to the current flowing during reverserecovery which also forward biases the emitter-base junction of the transistor. Due to the high voltagedeveloped across transistor, there are more chances of second breakdown. So, the bipolar transistorplays critical role during diode reverse recovery posing serious threat to power MOSFETs.

The IGBT offers high input impedance (which is a feature of MOS), along with large current-carryingcapability(feature of Bipolar), while supporting high voltage. IGBT is a device having input charac-teristics of MOS and output characteristics of voltage-controlled BJT. Due to these features the drivecircuitry of IGBT is simplified to a large extent. Also, the complexity of protective snubber circuitsis reduced[38]. Simple, lightweight, and economic power electronic systems can be constructed withIGBTs.

Figure 2.5: Commercially available IGBT Packages[39].

2.7 Packaging of IGBT

A package of any device should possess the properties such as good electrical performance, thermalperformance, long life, high reliability, and low cost. Moreover, for any module, the base plate shouldbe electrically isolated from the semiconductor die so that both the halves of a phase leg are enclosedin one package. This is very much desired so that the modules switching in different phases can bemounted on the same heat sink. Also from safety point of view it is favourable for grounding heat sink.IGBTs are generally packaged in three types of commercially available packages (Fig.2.5): (i) Discretepackages such as TO-220, TO-247, TO-264 and SOT-227B. These packages contain a single device andare used for low-power applications, (ii) Power module package: These package multiple dice and areavailable in several configurations such as half-bridge, full-bridge, and three-phase bridge, (iii) Presspack[38].

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2.8 Application Spectrum of IGBT

IGBTs can be utilized in applications over wide spectrum of current and voltage levels. Their char-acteristics of IGBT are ideal for applications operating higher than 200V. Typical applications includelamp ballasts, consumer appliances utilizing motors and electric vehicle drives. Other applications ofIGBTs are high-power motor control in steel mills and for traction in electric trains. Power transmis-sion and distribution systems also employ IGBTs. The on-resistance of commonly used Silicon powerMOSFETs is very high to serve all these applications. Therefore, all these applications take advantageof Silicon IGBTs. Silicon carbide (SiC) IGBT is a very good option for high blocking voltage(above10–15 kV) applications such as in smart grid applications[50]. In IGBTs, the current ratings of the de-vice increase along with increase in voltage rating for these applications with the exception of the smartgrid.In Silicon IGBTs, this issue is resolved by using multichip press-pack modules. The smart gridapplications are unique and require very high voltage devices with low current ratings. These applica-tions can be addressed by incorporating SiC-based IGBTs[40]. The only limitation of SiC is low chipmanufacturing yield and high cost of SiC wafers. These SiC IGBTs can operate at higher frequencies.This results in a smaller size for the magnetic elements used in the power circuits. SiC IGBTs have widerange of applications(Fig.2.6.)[51].

Figure 2.6: Application Spectrum of Silicon Carbide IGBT[51].

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Chapter 3

Simulation Methodology

This part of the report discusses the simulation tools and explains, in detail the physical setup, prop-erties and corresponding mathematical models considered in modeling of the SiC IGBT. The simulationsoftware used to perform the above task is Sentaurus TCAD software Version K-2015.06. To start with,brief information on the software is provided in section 3.1. The corresponding physical and mathemat-ical models are discussed later in this chapter.

3.1 Introduction

Technology Computer-Aided Design (TCAD) refers to computerized simulations for developmentand optimization of semiconductor devices and technologies. According to Sentauraus training manual,“TCAD simulation tools solve fundamental, physical partial differential equations, such as diffusionand transport equations for discretized geometries, representing the silicon wafer or the layer systemin a semiconductor device”. Due to the deep physical methodology TCAD involves, the simulationsgive results with predictive accuracy levels. And hence it is advisable to perform TCAD computersimulations instead of costly and time-taking wafer tests while developing and characterizing a newsemiconductor device or technology. Semiconductor industry relies largely on TCAD simulations. Withthe increase in complexity of the technologies, the dependence of semiconductor industry on TCADsimulations has also increased as it allows cost savings and accelerates the processes of research anddevelopment. Additionally, TCAD is used by semiconductor manufacturers for the analysis of yield,i.e. monitoring, analyzing, and optimizing the process flows of the IC, besides analyzing the affect ofvariation in the IC processes[52].

3.1.1 Sentaurus Structure Editor

Sentaurus Structure Editor is device editor for both 2D and 3D structures. The modes of operator ofthe editor are editing of 2D structure, editing of 3D structures and process emulation of 3D structures.The GUI allows the creation of 2D and 3D device structures by using basic geometrical shapes such as

25

rectangles, polygons, cuboids, cylinders, spheres etc. 3D regions can also be created either by exclud-ing 2D objects or by including the 2D objects. Sentaurus Structure Editing tool offers most advancedvisualization. Structures can be viewed as they are constructed. The tool also has powerful view filterswhich allows the user to select only a subset of regions or make certain regions transparent. Doping pro-files and meshing approached can be defined collectively. Placements can be viewed as semitransparentstructures for easy understanding and verification. The mesh generation tool- Sentaurus Mesh provideswide range of doping and meshing choices[53].

3.1.2 Sentaurus Device

Device simulations are the virtual measure of electrical performance of any semiconductor device,for example- a transistor or a PN junction diode. The device is treated as finite-element structure. Eachdevice node has its corresponding properties, like the type of material type and level of doping. Carrierdensity, current, electric field strength, rate of generation and recombination are computed for eachof the device node. Electrodes are considered as section on which boundary conditions are appliedlike applied input voltages etc. The simulating tool solves equations such as the Poisson equationand the carrier continuity equation (and some other equations). Once the equations are solved, theresultant device currents at the contacts are determined. The electrical, thermal and optical behaviorof silicon-based devices and compound semiconductor devices can be analyzed by Sentaurus device.The electrical characteristics can be simulated either by considering a single semiconductor device inisolation or a circuit in which various devices are embedded[54].

3.1.2.1 Basic Sentaurus Device

Figure 3.1: Structure of project folder[55].

In this section, the simulation of single isolated device(without external circuitry) has been explained.The mesh generator(Sentaurus Mesh etc) require the grid command files(*.mdr,*.cmd, etc.) and bound-ary files for the creation of the device structure for the device simulation. These files should be createdand saved in the folder grid under a project folder, as displayed in figure 3.1. The grid file defining the

26

structure of IGBT is given as input to Sentaurus Structure Editor where meshing is done. The outputfile of meshing is given as input to Sentaurus Device to run the simulations. In order to run the simula-tion, the command file for Sentaurus Device (*des.cmd) needs to be saved in the folder Input. To startthe simulation, we should go to the project folder and type the command sdevice input/*des.cmd underLinux terminal. Figure 3.2 illustrates the sections of a Sentaurus Device command file.

Figure 3.2: Structure of a Sentaurus Device command file for single device simulation[55].

The left section in the Figure 3.2 defines the specifications of the device. Device specificationsinclude meshing profile and doping level(defined in File section), contacts and thermodes(defined inElectrode and Thermode sections), and the physical models(defined in Physics section) that can beselected globally or mentioned specifically such as material wise, regions wise, interface wise. Themiddle block in Figure 3.2 specifies the desired output of the simulation. Plot and CurrentPlot sectionsdefine the results to be saved for a given simulation. The rightmost section in Figure 3.2 describes thesimulation. Different types simulations are defined in the Solve section. The respective parameters forvarious methods are defined in the Math section[55].

3.1.2.2 Mixed-mode Sentaurus Device

Figure 3.3: Mixed-mode Sentaurus Device[55].

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In the previous section, single device simulation command file is described. But Sentaurus Deviceis also capable of mixed-mode device and circuit simulations. In this section, the command file of themixed-mode device simulation is discussed.

The command file for circuit simulation consists of the mesh (defined in File section), contacts(defined in Electrode and Thermode Sections) physical models (defined in Physics Section) for eachdevice present in the circuit[55]. All the devices are defined under the Device sections. Furthermore, acircuit netlist must be defined in the command file that connects each device of the circuit as showed inFigure 3.3. The additional section required for mixed-mode device simulation is the ‘System section’.Under the System section new elements(R,L,C or user defined voltage sources etc.) can be defined andcreated. The System section also defines the circuit connections. Another point of difference of mixed-mode device simulation from a single device simulation is that the Solve section is specified to solve thewhole system of devices(circuit).

3.1.3 TCAD Simulation Flow

Synopsys TCAD is a elaborate product suite that consists of processing tools, simulation tools, in aGUI simulation environment that enables the simulation tasks and analysis of simulation results[55].

Figure 3.4: Simulation Packages of Sentaurus TCAD[55].

Figure 3.4 illustrates the structure of simulation flow of Sentaurus TCAD. From fig. 3.4, it can beunderstood that the boundary and command files are given as input to the mesh generator which createsthe grid and doping files for Sentaurus Device. After command file is run in Sentaurus Device, theresults can be viewed and analysed by ‘svisual’ in the form of images and/or the data can be exported.

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3.2 Modeling of SiC IGBT in Sentaurus TCAD

The tool flow starts with the creation of the trench gate n-IGBT device using Sentaurus StructureEditor as shown in Figure 3.5. Sentaurus Device simulates the electrical characteristics of the device,and Sentaurus Visual visualizes the obtained results.

3.2.1 Structure Generation of SiC IGBT

As asymmetric trench gate IGBT offers several advantages and exhibits superior performance incomparison with a typical IGBT. An asymmetric trench gate IGBT structure has been chosen for mod-eling of a SiC IGBT device in TCAD as lower ON-state voltage drop could be obtained by using trenchgate structure and asymmetric structure of IGBT could improve switching time along with ON-statevoltage drop[40]. The half-cell structure of the generated asymmetric trench gate 2D-SiC IGBT isshown in fig 3.5.

Figure 3.5: Schematic illustration of the SiC IGBT

In the asymmetric trench gate 2D-SiC IGBT, the gate is formed by deep trench with slanted sidewallsfilled with polysilicon. The vertical depth of trench gate region is about 4µm. The total vertical thicknessof the IGBT is 70µm. In a trench gate IGBT, the length of trench-gate is always very small as comparedto the total length of the device. The horizontal width of the device is 5µm. Drift region forms themajor portion of the device structure extending from 4µm to 67µm(vertically). Metallic contacts arecreated in Sentaurus Editor at the device terminals –gate, emitter and collector terminals. The device

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substrate material is 4H-SiC polytype. The p-doped region besides trench gate is doped with gaussianprofile doping pattern with minimum doping of 1017 cm-3 to maximum doping of 1020 cm-3. The driftregion is n-type doped with doping concentration of 1015 cm-3. The buffer layer has n-type dopingof 1019 cm-3. The n-type region below emitter terminal has doping concentration of 1021 cm-3. Thep-type injection layer above collector terminal has doping concentration of 1020 cm-3. The geometricdefinition of device, materials used, contacts, doping concentrations and meshing all are defined in‘.dvs’ command file. The structure as defined can be viewed as well in the structure editor of TCAD.

4H-SiC has the largest value of figure of merit for all measures(JFOM, KFOM and BFOM). Thetrench gate is made up of polysilicon, so that the applied gate voltage reaches uniformly deep inside thetrench region. The outer region of trench gate consists of few nanometers oxide layer. In the IGBT, theoxide layer insulates the polysilicon from the SiC substrate. The oxide layer is very critical and playsvery important role, as variation in any of the parameters of the layer such as thickness, oxide materialetc affect the performance of the device. In this work, the device behavior is analyzed for differentdielectric oxides- SiO2, HfO2 and ZrO2. The IGBT device as shown in fig.3.5 is defined in structureeditor of TCAD. The device structure is defined in ‘.dvs’ command file. On successful meshing, ‘.tdr’file is created by the structure editor. Fig.3.6 shows the device after meshing.

Figure 3.6: Meshing of the 2D-SiC IGBT

In SiC devices, Aluminum is used as dopant for p-type doping and Nitrogen is used as dopant forn-type doping. The energy required for the dopant to be activated in the base material is defined asthe dopant activation energy. Activation energies for Nitrogen and Aluminum in the 4H-SiC crystalare 0.07 eV [56] and 0.265 eV[57], respectively. Due to the deep impurity levels compared to thermalenergy(kT/q) available at room temperature, only a fraction of dopants are active. Moreover, the avail-ability of dopants is dependent on the applied bias. The Sentaurus Device models take into account

30

the bias-dependent and temperature-dependent activation of dopants through the incomplete ionizationmodel.

3.2.2 Physics Section

In Sentaurus TCAD, various physical models are added to specify the physics of the device to re-semble the real device behavior. These models govern the transport of the charge carriers under thecumulative result of numerous boundary conditions such as lattice temperature, electrostatic potentialsand fields, external forces, hetero-structures band gap variations and quantum effects. These models arerequired to be incorporated in the model section to perform simulations and do reliable predictions withrespect to the device characteristics. In this section, various models present in the software are discussedbriefly.

To simulate SiC-based devices, the following models are essential: anisotropic model, incompleteionization of dopants in SiC, ShockleyReadHall (SRH) recombination with doping dependency andtemperature dependency, mobility models that include mobility degradation due to doping, surfaceroughness, acoustic phonon scattering and high-field saturation, bandgap narrowing using OldSlotboommodel and interface charge traps at SiC/SiO2 interface. The SiC/SiO2 interface has imperfections andcontains interface traps. To simulate a realistic scenario, a fixed charge of 2x1012 cm-2 is placed on theinterface.

Silicon carbide, the electrons and holes may exhibit different mobilities along different crystallo-graphic axes. In a 2D simulation, the regular mobility µ is observed along the x-axis, and µaniso isobserved along the y-axis. The anisotropy factor r is defined as the ratio[58]:

r =µ

µaniso

(3.1)

The total anisotropic option (Total) is used to capture the anisotropic mobility. In this option, theanisotropy factor(r) for electron and hole mobility can be specified in the Physics section of the Sentau-rus Device command file as follows:

Physics { Aniso (

eMobilityFactor(Total)= re

hMobilityFactor(Total)= rh ) }

where the anisotropy factor (r) is defined as the ratio of regular mobility (µ) to the anisotropic mo-bility (µaniso).

Sentaurus TCAD offers a number of transport models to suit various modeling designs and require-ments. Depending on the type of material being used, all these methods can be generalized into threecarrier transport models: Drift-diffusion (DD), Thermodynamic (TD) and Hydrodynamic (HD)[58].Although all three of the above mentioned models are based on an all-inclusive Boltzmann Transport

31

Equation (BTE) differentiated by inclusion or exclusion of some specific physical phenomenon in BTE.The Drift-diffusion (DD) model is Sentauruss default transport model which approximates, in a BTE,that the carrier flow inside the device is due to their drift and/or diffusion under an external lateral orlongitudinal field concurrently with recombination and generation of carriers. The current density underthis model is described by the relation[58]:

Jn = −nqµn∆Φn (3.2)

Jp = −nqµp∆Φp (3.3)

where µn and µp are the electron and hole mobility respectively, Φn and Φp are the electron and holequasi-Fermi potentials. In this work, Drift-Diffusion mobility model and the corresponding equationsare considered in all the simulations.

According to Sentaurus Device User Guide, except Indium rest all other dopants in Silicon can beassumed to be completely ionized at room temperature as the the impurity level is not very deep. Inthe case when the impurity levels are deep in comparison to thermal energy KT, incomplete ioniza-tion needs to be accounted. Indium acceptors in Silicon and Nitrogen donors and Aluminum acceptorsin Silicon carbide come under the above category. Also the manual states that for the simulations atreduced temperatures, incomplete ionization model should be included for all dopants. In such cir-cumstances, “Sentaurus Device has an ionization probability model based on activation energy. Theionization (activation) is computed separately for each species present[58].”

The incomplete ionization model can be activated with the keyword IncompleteIonization in thePhysics section:

Physics{

IncompleteIonization }

The concentration of ionized impurity atoms is given by FermiDirac distribution[58]:

ND =ND,0

1+GD(T )exp(

EF,n−Ec

KT

) (3.4)

NA =NA,0

1+GA(T )exp(−

EF,p−Ev

KT

) (3.5)

where GD(T) and GA(T) are the ionization factors, ND,0 and NA,0 are the substitutional (active) donorand acceptor concentrations[58].

Recombination through deep defect levels in the gap is usually labeled ShockleyReadHall (SRH)recombination. In Sentaurus Device, the following form is implemented:

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RSRHnet =

np−(ni,eff )2

τp(n+n1)+τn(p+p1)(3.6)

n1 = ni,effexp(Etrap

KT

)(3.7)

p1 = pi,effexp(−Etrap

KT

)(3.8)

where Etrap is the difference between the defect level and intrinsic level.From measurements of the recombination lifetime:

τ = δn/R (3.9)

In power devices (δn is the excess carrier density under neutral conditions, δn = δp ), it was concludedthat the lifetime increases with rising temperature. Such a dependence was modeled either by a powerlaw:

τ(T ) = τ0

( T

300K

)α(3.10)

In Sentaurus Device, the power law model, can be activated with the keyword TempDependence inthe SRH statement:

Physics{

Recombination(

SRH( DopingDependence

TempDependence))}

For device simulation, the basic property governing the operation of a semiconductor is its bandstructure. In Sentaurus Device, the band structure is simplified to four quantities: the energies of theconduction and valence band edges (or, in a different parameterization, band gap and electron affinity),and the density-of-states masses for electrons and holes (or, parameterized differently, the band edgedensity- of-states).

According to Sentaurus Device User Guide, “the band gap is the difference between the lowestenergy in the conduction band and the highest energy in the valence band. The electron affinity is thedifference between the lowest energy in the conduction band and the vacuum level”.

The bandgap model can be selected in the EffectiveIntrinsicDensity statement in the Physics section,for instance:

33

Physics {

EffectiveIntrinsicDensity

(BandGapNarrowing (Slotboom)) }

activates the Slotboom model.Sentaurus Device models the lattice temperaturedependence of the band gap as:

Eg(T ) = Eg(0)− αT 2

T+β(3.11)

The effective band gap results from the band gap reduced by bandgap narrowing:

Eg,eff(T ) = Eg(T )− Ebgn (3.12)

For OldSlotboom, the affinity is temperature dependent and is affected by bandgap narrowing as:

χ(T ) = χ0 +(α+α2)T 2

2(T+β+β2)+Bgn2Chi.Ebgn (3.13)

where χ0 and Bgn2Chi are adjustable parameters. Bgn2Chi defaults to 0.5 and, therefore, bandgapnarrowing splits equally between conduction and valence bands.

Bandgap narrowing for the Slotboom model (keyword Slotboom or OldSlotboom) in Sentaurus De-vice reads:

∆E0g = Eref

{ln(Ntot

Nref

)+

√{ln(Ntot

Nref

)}2+ 0.5

}(3.14)

The models are based on measurements of µnni2 in n-p-n transistors (or µpni

2 in p-n-p transistors)with different base doping concentrations and a 1D model for the collector current[58].

3.2.3 Maths Section

One key difference between 4H-SiC and Si is an extremely large difference in intrinsic carrier con-centration due to a much larger band gap in SiC. In Silicon, the intrinsic carrier concentration is 1x1010

cm-3, while in 4H-SiC, it is much lower, close to 1x10-7 cm-3. A much lower intrinsic carrier concentra-tion necessitates a change in the default values for the Math parameters that are related to the intrinsiccarrier concentration value.

For SiC simulations, the transient mode at times can provide a faster simulation speed because evena very small displacement current, induced due to a slow ramp rate of 1 V/s, can improve convergence incertain ultralow current regimes, while having no adverse affect in higher current regimes. For transientsimulations, the backward Euler (BE) method is used, which utilizes a first-order approximation over

34

the time step and is known to be a stable method. In terms of computation time, the BE method is fasterthan the default composite trapezoidal rule backward differentiation formula (TRBDF) method[58].

The transient simulation approach is used to simulate both IcVc(output) and IcVg(transfer) char-acteristics. In the Electrode section, the applied input voltage is ramped in first 1sec. Once the inputterminal voltage(Vx) reaches maximum value, the output terminal voltage(Vy) is swept from 0 to maxi-mum value in the next few seconds. Vx is the Sentaurus Workbench input variable for the input terminalvoltage at which the output terminal voltage(Vy) is ramped to maximum value. A large ramp rate is cho-sen (1V/s) so that the displacement current component (dQ/dt) does not dominate the extremely smallDC leakage current in the device off-state.

Extended-precision floating-point arithmetic is useful in resolving the extremely small quantitiesdue to a low intrinsic carrier concentration in SiC devices. The default 64 bits might be insufficientto resolve such extremely small quantities. Using the Sentaurus Workbench parameter precision, therequired number of bits can be set. The two suggested values for precision are 80 and 128. Extend-edPrecision(128) uses 128 bits with a precision of 2.47x10-32, although it may result in a 10 timesincrease in computation time. Due to this significant slowdown, it is advised to begin with 80 bitsfor simulations of wide-bandgap devices before proceeding with 128 bits. For anisotropic simulations,the recommended approach is to use the TensorGridAniso algorithm with the total anisotropic mobilitymodel. The TensorGridAniso algorithm gives the most accurate results if the current flows along themesh edge. Therefore, a layered mesh around the trench corner has been used with TensorGridAniso togive accurate and robust results.

Since the intrinsic carrier concentration in SiC is small, the ErrRef(electron) and ErrRef(hole) valueshave been reduced to 1 from the default value of 1x1010. Similarly, the CDensityMin value has beenmodified from the default of 3x10-8 A/cm2 to 1x10-30 A/cm2.

To control the convergence criteria that are based only on the relative and absolute error, RHSMinis set to a very small value, 1.0x10-30 (RHS, which is referred to as the residual of the equations). Intransient simulations of wide-bandgap semiconductors, the maximum value of RHS and the factor bywhich the RHS changes during a single Newton step can be large. For this reason, both RHSMax andRHSFactor are set to 1x1030.

3.2.4 Device Simulation

The Sentaurus project simulates the static(output characteristics and transfer characteristics) anddynamic/transient characteristics of the n-IGBT device. All the simulations are obtained by keeping theEmitter terminal grounded(0 V) and at temperature of 300 K. For the simulation of the n-IGBT devicecharacteristics, appropriate physical models, mathematical models and a set of model parameter valuesfound in the literature for the models are used.

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Chapter 4

Results

4.1 Static Characteristics

Transfer characteristic of any device depicts the variation of output parameter with respect to vari-ation in input parameter. In simple words, the characteristic represents the electrical behavior of anydevice under applied input conditions. The transfer characteristic for an IGBT, is the variation of outputcollector current(Ic) with respect to applied input gate voltage(Vg) values[59]. Simulations have beenperformed to obtain the transfer characteristics of the 2D-SiC IGBT for each SiO2, HfO2(EOT∼3nm)and ZrO2(EOT∼3nm) gate dielectrics with actual thickness of 20nm.

Initially, the collector voltage(Vc) is ramped to 5 Volts in 1 sec and once the collector voltage(Vc)attains 5 Volts, gate voltage(Vg) is varied from 0 Volts to 5 Volts in the next 5sec. For obtaining thetransfer characteristics, Vc is the Sentaurus Workbench input variable for the collector voltage at whichthe gate voltage is ramped to 5V.

Figure 4.1: Illustration of the gate dielectric stack made up of 1nm SiO2 and 20nm(actual thickness)

high-K dielectrics (HfO2 / ZrO2).

36

Same set of simulations are repeated by adding a thin layer of SiO2 layer between SiC substrate andthe high-K dielectrics (HfO2 , ZrO2). The interface SiO2 layer is of 1nm thickness. Fig.4.1 illustratesthe gate dielectric stack. For the applied gate voltage values, lower collector current is observed in-caseof the gate dielectric stack as compared to individual high-K gate dielectrics (HfO2 / ZrO2).

The gradient of transfer characteristic at a given temperature is a measure of the transconductance ofthe device at that temperature[59]. The slope of the transfer characteristic curve depicts the transconduc-tance ratio. From the obtained transfer characteristics for high-K dielectrics(HfO2 and ZrO2), SiO2 andthe gate dielectric stack (high-K dielectrics and SiO2), it can be seen that SiO2 has minimum transcon-ductance value. Individual high-K gate dielectrics (HfO2, ZrO2) exhibited maximum transconductancevalue but the transconductance value reduced with insertion of SiO2 interface layer.

Collector current as a function of gate bias is plotted(in Fig.4.2) for SiO2, HfO2 and ZrO2 as gatedielectrics at room temperature. For the same applied simulation settings, the IGBT with high-K gatedielectrics(HfO2 and ZrO2) displayed much lower threshold voltage as compared to SiO2 of same thick-ness. It can also be inferred from Fig.4.2 that high-K dielectrics (individually placed on SiC substrate)allow IGBTs to exhibit a better forward transconductance ratio. High transconductance along with alower threshold voltage could lead to better switching capability of the device. And hence improved

Figure 4.2: Transfer Characteristics of SiC IGBT for different dielectrics and combinations.

switching performance of an IGBT is expected while using high-K dielectrics(HfO2 and ZrO2).Additionally, from the results, it can be seen that the transconductance ratio reduces with insertion ofinterface SiO2 layer. Still the transconductance ratio of high-K dielectrics with interface SiO2 layeris much higher than the transconductance ratio of individual SiO2 gate dielectric. The same trend isexpected from the switching characteristics of the IGBT for different dielectrics.

37

In an IGBT, the output characteristic of a device is defined as characteristics in which the collectorcurrent (Ic) is measured as a function of collector-emitter voltage (Vc) with the gate-emitter voltage(Vge) kept constant[59].

Figure 4.3: Output Characteristic of SiC IGBT with different dielectrics of actual thickness of 20nm.

Inorder to obtain output characteristics of the SiC IGBT, first the gate voltage(Vg) is ramped from0 V to 5 V in 0 s to 1 s in the Electrode section of ’sdevice’ command file. Once the gate terminalvoltage reaches 5 V, the collector terminal voltage is swept from 0 V to 10 V in the next 10 s. Vg is theSentaurus Workbench input variable for the gate voltage at which the collector voltage is ramped from0 V to 10V.

High-K dielectrics exhibit much higher Ic for any given Vc which could be beneficial from the devicepoint of view leading to lower ON resistance during conduction mode.

4.1.1 Stability of Dielectrics

Threshold voltage of an IGBT is the minimum gate-emitter voltage at which collector current startsflowing. Threshold voltage can be obtained from the device transfer characteristics. Threshold voltage isextracted from transfer characteristics as the gate voltage for which the collector current attains value of1µA. The same threshold voltage extraction method has been adopted for all the cases. The knowledgeof threshold voltage for any device is very essential as it conveys the voltage at which the device becomesON or starts conducting.

The threshold voltage of any device decreases with increases in temperature. The threshold voltageis a negative temperature coefficient quantity.

38

Power IGBTs are expected to work reliably even at very high temperatures and hence there should beminimal affect of temperature on device performance. To study the thermal stability of gate dielectricsconsidered (HfO2, ZrO2 and SiO2), threshold voltage variation for each case is analyzed. By the rateof threshold voltage variation, thermal stability of the dielectrics can be understood. The variation inthreshold voltage with temperature of each of the gate dielectrics(HfO2, ZrO2 and SiO2) is analyzed.The variation in threshold voltage with increasing temperature from temperature range of 300 K to 450K is shown in fig.4.4.

Figure 4.4: Variation of threshold voltage of the SiC IGBT with temperature (K) for different dielectrics

with actual thickness of 20nm.

From the plot, it can be seen that the variation in threshold voltage with respect to temperature forthe high-K dielectrics (HfO2 and ZrO2) is very small as compared to SiO2. The voltage shift for SiO2 is∼0.35 Volts whereas for HfO2 it is ∼0.167 Volts and ∼0.11 Volts for ZrO2. HfO2 and ZrO2 exhibitedmuch better thermal stability than SiO2 for the same applied input conditions.

IGBT is expected to work in harsh conditions and hence it is desirable that, the performance of theIGBT be unaffected by the external conditions such as temperature etc. Thermal stability is a veryimportant and essential feature of any IGBT and hence HfO2 and ZrO2 can be used instead of SiO2

in-order to obtain minimized effect of temperature on the device performance. From the threshold

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Figure 4.5: Variation of SiC IGBT threshold voltage with increasing thickness of interface SiO2 layer.

characteristics it can be concluded that as far as thermal stabilty is concerned, HfO2 and ZrO2 are betterchoice over SiO2 as gate dielectrics in a SiC IGBT.

Another analysis with threshold voltage of the IGBT has been done for SiC IGBT with SiO2 in-between SiC substrate and the 20nm(actual thickness) high-K dielectrics (HfO2 and ZrO2). The vari-ation in threshold voltage of the IGBT is analyzed with increasing in thickness of interface SiO2. Thesimulations have been done for SiO2 gate oxide thickness 1nm to 4nm. Fig 4.5 depicts threshold voltagevariation of the IGBT with increasing increasing thickness of SiO2 interface.The gate leakage currentincreases exponentially with decreasing oxide thickness[60].

4.2 Transient Analysis

To understand the dynamic behavior of the SiC IGBT with different dielectrics, simulations havebeen performed. The simulation conditions and circuit is defined in ’.des’ command file. The circuitsimulator and mixed mode device features of Sentaurus TCAD are utilized in this section.

Mixed-mode environment is used for the simulations. Under mixed mode environment, the IGBTis not simulated as isolated IGBT, but as device in an external circuit. The dynamic characteristics ofthe IGBT are obtained by embedding the device in an external gate drive circuit. The applied drivecircuit consists of a clamped inductive load at the collector terminal which is connected to a DC voltagesource(Vcc) of 400 V. The gate is connected to a time-dependent voltage source(Vgg). The switchingcharacteristics of the IGBT is obtained by applying a voltage pulse of magnitude 15 Volts to the gateapproximately for 1µsec. The pulse voltage is defined as piecewise linear, i.e. by a list of time-voltagevalues. The emitter terminal of IGBT is grounded. Gate resistance(Rg) is connected between gate

40

Figure 4.6: Clamped inductive load drive circuitry for the SiC IGBT

voltage source and gate terminal. Inductor is connected in parallel with a diode. The parallel circuitis connected between Vcc and collector terminal. The external drive circuitry is defined under systemsection of ’.des’ command file. All the simulations are performed at room temperature.

Figure 4.7: Curent and Voltage waveforms of SiC IGBT depicting Turn ON and Turn OFF times [59].

41

4.2.1 Timing Analysis of Output Collector Current

Simulations have been performed to study the transient characteristics of the IGBT with 20nm(actualthickness) HfO2, ZrO2 and SiO2 gate dielectrics individually placed on top of the SiC substrate. Anotherset of transient analysis simulations have been done by sandwiching 1nm SiO2 between SiC and thehigh-K dielectric layers.

When a low voltage is applied to the gate of the MOSFET present in IGBT equivalent circuit, there isno pathway for base current of BJT current to flow. By the base current value the OFF state is decided.However for faster turn off base current needs to be forced into base terminal of the BJT, but no suchmechanism exists for sweeping the carriers out of the base. This is the reason for the slow turn off ofBJT which leads to occurrence of current called tail current as the charges stored in the base regionmust be cleared off in the form of emitter current[61]. Figure 4.9 illustrates the flow of tailing collectorcurrent.

Figure 4.8: Path of tailing collector current[61].

From the collector current (Ic) waveform, the tail current is measured as that part of the current whereIc continues to flow after an initial abrupt downfall. The starting point of the tail current part in collectorcurrent is the point when the rate of change of collector current visibly reduces.

The turn-off losses of the IGBT increase due to presence of tail current, as the tail current occurswhen collector voltage(Vce) is high. When clamping inductive load switching circuit is considered asthe drive circuitry, the IGBT collector voltage(Vce) already reaches the power supply(Vcc), when thetail current starts flowing in the device.

The minority carriers present in the N-layer, or the base of the PNP transistor in IGBT equivalentcause the tail portion in the collector current waveform of an IGBT at turn-off[62]. Once the channel ofthe MOSFET stops conducting, no electron current flows and the IGBT collector current falls drasticallyto the hole recombination current level that marks the inception or beginning of the tail[62]. The tailis important mainly because it leads to increase in switching losses. This happens as tail current flowswhen the voltage(Vc) across the IGBT is at its maximum level[62].

42

Figure 4.9: Switching waveforms of an IGBT

And hence the the analysis of collector current is very essential so as to predict and understandthe switching losses. The collector current of IGBT is obtained for different dielectrics by applying avoltage pulse at the gate terminal. The turn ON time and turn OFF time for each case is observed andanalyzed.

Turn ON time (T(ON)) of the IGBT is the sum of turn ON delay time(Td(ON)) and the rise time(tr)of the collector current under application of pulse gate voltage.

Turn ON delay(Td(ON)) is calculated as the time period from 10% of applied rising gate voltage to10% of maximum collector current.

Rise time(tr) is calculated as time period taken by collector current to rise from 10% to 90% of itsmaximum value.

T(ON)=Td(ON)+tr

Turn OFF time (T(OFF)) of the IGBT is the sum of turn OFF delay time (Td(OFF)), fall time (tf)and tail current.

Turn OFF delay(Td(OFF)) is calculated as the time period from 90% of applied falling gate voltageto 90% of maximum collector current.

Fall time(tf) is calculated as time period taken by collector current to fall from 90% to 10% of itsmaximum value.

Tail current is approximately the time period taken by collector current to fall from 10% to zerovalue[62].

T(OFF)=Td(OFF)+tf+tail current

43

The output collector current waveforms of IGBT with 20nm(actual thickness) HfO2, ZrO2 and SiO2

gate dielectrics have been studied. Turn ON and OFF times are analysed for each case.

The transient analysis simulations are repeated for gate dielectric stack of 20nm(actual thickness)HfO2/ ZrO2 and 1nm SiO2.

It is observed that by incorporating the high-K dielectrics the turn ON time is comparable but theturn OFF time is greatly reduced.

Table 4.1 lists the switching times for SiC IGBT for different gate dielectrics and combinations.

Table 4.1: Timing Analysis of different dielectrics considered in the SiC IGBT. All numbers are in

nano-seconds.

Dielectric Rise time(tr) Td(ON) T(ON) Td(OFF) Fall Time(tf) Tail Current T(OFF)

HfO2 7.2 129 136 151 149 380 680

ZrO2 6.6 135 141 92 186 380 658

SiO2 35 103 138 157 548 1070 1775

HfO2+1nm SiO2 10.6 115 126 136 189 485 810

ZrO2+1nm SiO2 10.1 123 133 147 183 510 840

Figure 4.10: Turn ON and Turn OFF timings of the SiC IGBT with 20nm SiO2 gate dielectric.

44

Figure 4.11: Dynamic characteristics of the SiC IGBT with 20nm(actual thickness) HfO2 gate dielectric.

Figure 4.12: Dynamic characteristics of the SiC IGBT with 20nm(actual thickness) ZrO2 gate dielectric.

45

As the objective is to study the switching characteristics with high-K dielectrics, none of the parame-ters related to the IGBT (such as doping, thickness etc) and the drive circuit are varied. Figures 4.14 and4.15 show the comparison of turn OFF characteristics of the device with fixed dielectric thickness of20nm(actual thickness). A clean break is observed during the current turn OFF indicating the inceptionof tail current.

Figure 4.13: Tail part of collector current magnified and redrawn in fig 4.15 to illustrate the improvement

in turn OFF time by using high-K dielectrics.

Tail current is observed due to the minority carrier holes that are trapped in the base region whichslowly recombine with electrons causing a delay in the turn off process. From Fig. 4.15, the tail currentduration is approximately observed to be 1070 nano-seconds for SiO2. For the same drive circuit andsimulation conditions, the tail current for the high-K dielectrics(HfO2/ZrO2) is observed to be 380 nano-seconds. Table 4.1 lists switching times for the different dielectrics that are under consideration in thisstudy, with SiO2 showing the longest turn OFF time. While there is not much difference with respectto turn ON time, evidently there is considerable reduction in the turn OFF time for high-K dielectrics.Even after inserting 1nm SiO2 between SiC and HfO2/ZrO2, the tail current duration is much smallerthan 1070 nano-seconds. This improvement in turn OFF time will enhance the switching frequency andhence reduces the power dissipation during switching. This can be attributed to the inclusion of high-K dielectric, which had eventually led to the reduction of minority carrier lifetime in the base region.Moreover, this improvement can also be attributed to high transconductance and low threshold voltagevalues obtained using high-K dielectrics. The switching time taken by the dielectrics is found to be inthe order as it was anticipated from the transconductance ratios obtained from transfer characteristics.The switching times of dielectrics are in agreement with the transfer characteristics results. The high-Kdielectrics exhibited maximum transconductance ratio which reduced on insertion of SiO2 layer andwas found to be minimum in-case of individual SiO2 dielectric layer. And thus, the descending orderof switching time duration is SiO2 layer, high-K dielectrics with SiO2 interface and individual high-Kdielectrics(HfO2 and ZrO2).

Since there has been improvement in the rise time, fall time, and turn OFF time, there must be someimprovement in power dissipation in the case of high-K dielectrics when compared to SiO2.

46

Figure 4.14: Tail current measurement for different dielectrics of 20nm (actual thickness) at 300 K.

4.3 Switching Power Losses

In power electronics, switching power losses typically contribute a significant amount to the totalsystem losses. The switching losses are dependent on the switching frequency. Tail current durationadds to the power loss because this is the part of collector current that exists when collector voltage ishigh. Even small values of collector current(tail current) when multiplied with high collector voltagevalues lead to significant power dissipation values.

Power loss of an IGBT is calculated as the product of output collector current(Ic) and collectorvoltage(Vc).

P(Watts) = Ic(Amp) x Vc(Volts) (4.1)

In order to understand the switching loss trend, power dissipation is plotted as a function of time byapplying a voltage pulse at the gate input as shown in Fig. 4.16. Power dissipated is approximately 2Watts in the case of ZrO2/HfO2 as compared to 2.5 Watts for SiO2 at 300K. At 300K the power curvesof ZrO2/HfO2 and SiO2 almost overlap with each other. Upon close observation the power dissipationfor SiO2 is slightly higher than the power dissipation of high-K dielectrics(ZrO2/HfO2).

Since the IGBTs are supposed to operate at higher temperatures in real time applications and in-orderto confirm the power dissipation trend obtained at 300 K, the power dissipation measurements were re-peated for temperatures 500 K and 600 K. The switching power losses for high-K dielectrics(ZrO2/HfO2)were observed to be much lower than SiO2 even at higher temperatures. With increasing temperature,the difference in power dissipation between high-K dielectrics and SiO2 became quite evident. As SiO2

47

Figure 4.15: Power dissipation as a function of time plotted for various dielectrics, obtained at differenttemperatures.

has the longest tail current duration, the switching losses are also highest. The obtained switching powerloss results are in accordance with the switching time results obtained earlier.

Figure 4.16: Power Dissipation trend for different dielectrics considered with increasing temperature.

48

Fig. 4.17 demonstrates the power dissipation for high-K dielectrics(ZrO2/HfO2) and SiO2 dielectricswith increasing temperature. From the figure it can be seen that the power dissipation gap betweenhigh-K dielectrics(ZrO2/HfO2) and SiO2 widens with increase in temperature. At 600K, the powerdissipation is almost 10 Watts lower in the case of high-K dielectrics as compared to SiO2. In additionto handling high electric fields, this study clearly shows the benefit of using ZrO2/HfO2 dielectric interms of switching characteristics.

4.4 Gate Leakage Current

In electronic devices, leakage is a quantum phenomenon where mobile charge carriers (electrons orholes) tunnel through an insulating region[60]. Simulations have been performed to determine the gateleakage current(Ig) of the SiC IGBT for 20nm(actual thickness) HfO2, ZrO2 and SiO2 gate dielectrics,placed individually on top of SiC substrate and then by sandwiching 1nm SiO2 layer in-case of high-Kdielectrics. The results were obtained for 5 Volts collector voltage(Vce) at room temperature.

Two kinds of tunneling mechanisms accountable for the gate leakage current are Fowler-Nordheimtunneling current and direct tunneling current[63]. In this work, FN tunneling model has been taken intoaccount for the assessment of the gate dielectrics. Direct tunneling is not considered in the simulationsas it exists only in-case of very thin dielectrics(less than 3nm).

Figure 4.17: Gate Leakage current for various gate dielectrics under consideration.

High-K dielectrics could lead to higher gate leakage currents due to lower band offsets[64]. Fig.4.18shows the gate leakage current as a function of gate voltage for different dielectrics at room temperature.Evidently the high-K dielectrics(ZrO2/HfO2) have high leakage current compared to SiO2 at any gate

49

voltage, and with the insertion of 1nm SiO2 the gate leakage current drastically reduces to a lower valuecompared to SiO2. By inserting a thin layer of SiO2 between SiC and high-K dielectric layer, the highband offset of SiO2 could still be retained[64]. The leakage current curves of ZrO2 and HfO2 are foundto be almost overlapping.

Improved switching characteristics can be obtained by the individual high-K dielectrics but the gateleakage current of the high-K dielectrics is very high as compared to SiO2. This is due to the lower bandoffset and compatibility concerns of the high-K dielectrics with SiC substrate. Improved switchingperformance for the SiC IGBT along with minimum leakage loss can be obtained by including a thinlayer of SiO2 between high-k dielectrics and SiC substrate. By incorporating an interface SiO2 layerbetween high-k dielectrics(ZrO2 and HfO2) and SiC substrate in the SiC IGBT, optimum results forswitching as well as gate leakage current can be obtained.

50

Chapter 5

Conclusion

Silicon carbide(SiC) based power devices provide superior thermal and electrical capabilities, due toa wide band gap, a high critical electric field, and a high saturation velocity compared to that of Silicon.Therefore, compared to silicon, SiC is a more suitable candidate for high-power, high-frequency andhigh-temperature device applications.

The insulated gate bipolar transistor (IGBT) offers features such as a MOS gate that could be easilycontrolled along with lower conduction losses. And hence is the device of choice over power bipolartransistors for high-current and high-voltage applications. Trench gate IGBTs are preferred over theirplanar counterparts due to lower ON-state resistance for a given voltage-blocking capacity, especiallyfor devices with high switching speed.

IGBT is utilized in industrial applications such as lamp ballasts, HVDC light, SVC light, wind powergenerators, UPS, motor drives, power transmission and so on. Many applications today rely on the IGBTdevice. As IGBT exhibits near ideal characteristics at high voltages and frequencies, the device attractsattention from researchers worldwide.

To obtain further benefits of the IGBT, SiC IGBTs are ventured upon. In this thesis, a 2D 4H-SiC n-type IGBT device is characterized for different gate dielectrics using TCAD Sentaurus tools. This workdeals with fine tuning of the performance of IGBT by replacing the conventional materials by materialshaving superior properties.

This thesis work is based on device simulation results. Various aspects such as static characteristics,dynamic characteristics, power loss and leakage currents have been studied for an asymmetric trenchgate 2D-SiC IGBT. The performance of the IGBT has been analyzed by altering various attributes.SiC-4H prototype offers innumerable advantages and exhibits better performance than Silicon. Themost commonly used dielectric material i.e. SiO2 in Silicon devices is incapable of withstanding highelectric fields when used along with SiC. The gate dielectrics greatly influence the device performance.And also due to increased pressure of scaling, high-K dielectrics have been the obvious alternatives.Among the high-K dielectrics, HfO2 and ZrO2 were the most appropriate dielectrics because of theproperties possessed by them. And hence, HfO2, ZrO2 and SiO2 have been considered as the gatedielectric candidates in the device simulations. The performance of SiC IGBT with gate dielectrics

51

HfO2 and ZrO2 along with conventional SiO2 is analyzed by the Sentaurus TCAD simulations andthe results have been analyzed. A reliable comparison between high-K dielectrics and SiO2 has beenconducted in order to reveal the nature and degree of benefit provided by using high-K dielectrics forSiC based asymmetric trench gate IGBTs.

The transconductance ratios and threshold voltage values of the SiC IGBT were gathered from thestatic characteristics for the dielectrics. It has been observed that ZrO2 along with HfO2 has high for-ward transconductance and lower gate threshold voltage compared to SiO2. The low threshold voltagevalues and high transconductance ratios offered by the high-K dielectrics(HfO2 and ZrO2) suggestedimproved switching characteristics. The switching characteristics of a SiC IGBT have been carefullyanalyzed using a drive circuit with an inductive load. The switching characteristics curves obtainedfor the dielectrics were found to be in accordance with the static characteristics results. Due to mini-mized tail current duration, the high-K dielectrics exhibited improvement in the switching frequency.Since switching power dissipation depends on the switching time taken by the IGBT, reduced switchingtime predicted cutback in the switching power dissipation. The expected outcomes were observed fromthe simulations performed for power dissipation. The power dissipation trend of the IGBT for variousdielectrics have been correlated with the static and dynamic characteristics of the device.

One of the drawbacks of high-k dielectrics is high gate leakage current. This has been resolved byadding a thin SiO2 layer in-between the high-K dielectrics and SiC substrate. Although the switchingperformance of the dielectric stack is slightly compromised as compared to individually placed high-Kdielectrics, the performance is much improved with respect to SiO2 gate dielectric. By this approach,lower gate leakage current for SiC IGBT can be attained along with improved switching performanceand reduced switching losses.

While there could be some variation in measurement results between simulated and fabricated struc-ture, the obtained evidence confirms the critical role of high-K dielectrics for future SiC power devices.

52

5.1 Disclaims

Static and dynamic characteristics of SiC IGBT have been obtained by TCAD simulations for threedielectrics namely HfO2, ZrO2 and SiO2. Static characteristics obtained are under conditions of fixedtemperature of 300 K, constant gate voltage (Vge) of 5Volts for output characteristics( Ic vs Vce) andconstant collector voltage (Vce) of 5Volts for transfer characteristics ( Ic vs Vge) respectively. Trans-fer characteristics have been obtained for the three dielectrics for fixed temperature of 300K. Later,power dissipation trend of SiC IGBT is determined for temperatures of 300K, 500K and 600K bythe tool. Gate leakage current of SiC IGBT is found for each dielectric at temperature of 300K.

SiC IGBT performance has not been validated for the following below conditions and the simulationscan be extended for the same. The conditions are as follows:

1. The variation of transconductance value - gfs(gradient of transfer characteristic at a given tempera-ture) can be found as a function of gate voltage(Vge) for different dielectrics and combination(HfO2/ZrO2

and SiO2). This would give a better understanding of current handling capacity of each case. By the plotof transconductance value gfs with respect to gate voltage(Vge), the threshold variation trend can be un-derstood. This has not been done in this work.

2. The switching characteristics of the SiC IGBT have been obtained for different dielectrics for atemperature of 300K. The same analysis can be performed for different temperatures. And the results ob-tained could confirm the precision of the existing results.

3. The switching characteristics have been obtained for applied input pulse gate voltage. The risetime of the gate input pulse is 20µsec and the fall time is 20µsec. The rise time and fall time of the ap-plied input pulse could affect the switching characteristics. This analysis has not been done. As an exper-iment, the rise time and fall time of the input gate pulse can be varied and by the simulation results, theeffect of increasing or decreasing rise or fall time can be understood on the on-time T(ON) and off timeT(OFF) of SiC IGBT.

4. Switching analysis in this work has been done for single pulse. The affect has not been analyzedfor train of pulses.

5. The switching analysis has been done for fixed pulse duration. The affect has not been analyzed fordifferent width of the pulse.

6. In the present work, the gate leakage current of SiC IGBT has been obtained at temperature of300K. Leakage current analysis has not been done for higher temperatures. By the gate leakage current,thermal stability of dielectrics can be understood. More the gate leakage current less is the dielectric sta-

53

bility at corresponding temperatures.

7. The static characteristics (transfer characteristics and output characteristics) can be analyzed athigher temperatures. Also, by these curves at higher temperatures the thermal stability of dielectrics canbe determined. These curves can also be obtained at different voltage levels. The characteristics obtainedare at 300K.

8. The combination of gate resistance (Rg) and capacitance (Cge) is a simple RC circuit whose con-stant time τ=RC affects charge and discharge time. Rg is a one of the key factors contributing to the turnon/off time. In this case, with inductive load, the power dissipated by the device with higher Rg is ex-pected to be bigger than the standard Rg device because the switching slowdown, especially at turn-off,produces an additional current or the tail current. In the obtained switching characteristics the effect ofgate resistance and capacitance has not been considered.

9. Breakdown voltage of SiC IGBT can be found as function of temperature can be determined for thethree dielectrics. Higher the critical field of material used, higher will be the breakdown voltage of thedevice. Breakdown analysis has not been performed in this work.

10. As IGBT capacitance impact the switching characteristics. Input ( Cge + Cgc) and outputcapacitance(Cec + Cgc) can be obtained as function of collector voltage(Vce). Capacitance variationcan be found at different temperatures and related with the switching times. The capacitance valueshave not been obtained in this work.

54

Appendix

;———————————————————————-;

Structure Definition of SiC IGBT(.dvs command file)

20nm thick Gate Dielectric

;———————————————————————-;

(sdegeo:set-default-boolean "BAB")

(sdegeo:create-polygon (list

(position 2.0 0.0 0)

(position 2.1 3.19 0)

(position 2.7 3.19 0)

(position 2.788 0.0 0)

(position 2.0 0.0 0))

"PolySi" "R.PolyGate")

(sdegeo:fillet-2d (find-vertex-id (position 2.1 3.19 0)) 0.2)

(sdegeo:fillet-2d (find-vertex-id (position 2.7 3.19 0)) 0.2)

;----------------------------------------------------------------------;

20nm Gate Dielectric layer

;----------------------------------------------------------------------;

(sdegeo:create-polygon (list

(position 1.98 0.00 0)

(position 2.08 3.22 0)

(position 2.72 3.22 0)

(position 2.808 0.00 0)

(position 1.98 0.00 0))

"Oxide" "R.Gox")

(sdegeo:fillet-2d (find-vertex-id (position 2.08 3.22 0)) 0.2)

(sdegeo:fillet-2d (find-vertex-id (position 2.72 3.22 0)) 0.2)

(sdegeo:create-polygon (list

55

(position 2.00 0.02 0)

(position 1.50 0.02 0)

(position 1.30 0.22 0)

(position 0.00 0.22 0)

(position 0.00 -0.18 0)

(position 1.30 -0.18 0)

(position 1.50 0.00 0)

(position 2.00 0.00 0)

(position 2.00 0.02 0))

"Oxide" "R.LOCOS")

(sdegeo:fillet-2d (find-vertex-id (position 1.3 0.22 0)) 0.15)

(sdegeo:fillet-2d (find-vertex-id (position 1.3 -0.18 0)) 0.15)

(sdegeo:create-rectangle

(position 2.8 -0.3 0.0 )

(position 3.1 0.0 0.0 )

"Oxide" "R.Spacer")

(sdegeo:create-rectangle (position 0.0 0.0 0.0 )

(position 2.8 -0.3 0.0 )

"PolySi" "R.PolyCont" )

(sdegeo:create-rectangle

(position 0.0 0.0 0.0 )

(position 4.8 70.0 0.0 )

"SiliconCarbide" "R.SiC" )

(sdegeo:define-contact-set "Emitter" 4 (color:rgb 1 0 0 ) "**" )

(sdegeo:define-contact-set "Collector" 4 (color:rgb 1 0 0 ) "**" )

(sdegeo:define-contact-set "Gate" 4 (color:rgb 1 0 0 ) "**" )

(sdegeo:define-2d-contact (find-edge-id (position 3.5 0.0 0.0)) "Emitter")

(sdegeo:define-2d-contact (find-edge-id (position 3.5 70.0 0.0))

"Collector")

(sdegeo:define-2d-contact (find-edge-id (position 1.0 -0.3 0.0)) "Gate")

;----------------------------------------------------------------------;

Profiles

;----------------------------------------------------------------------;

; - Substrate

(sdedr:define-constant-profile "Const.Substrate"

56

"NitrogenActiveConcentration" 1e+15 )

(sdedr:define-constant-profile-material "PlaceCD.Substrate"

"Const.Substrate" "SiliconCarbide" )

(sdedr:define-constant-profile "Const.PolyGate"

"NitrogenActiveConcentration" 1e+21 )

(sdedr:define-constant-profile-material "PlaceCD.PolyGate"

"Const.PolyGate" "PolySi" )

(sdedr:define-refinement-window "BaseLine.pbody" "Line"

(position 3.0 0.0 0.0)

(position 5.0 0.0 0.0) )

(sdedr:define-gaussian-profile "Impl.pbodyprof"

"AluminumActiveConcentration"

"PeakPos" 0.1 "PeakVal" 1e20

"ValueAtDepth" 1e17 "Depth" 2

"Erf" "Length" 0.1)

(sdedr:define-analytical-profile-placement "Impl.pbody"

"Impl.pbodyprof" "BaseLine.pbody" "Positive" "NoReplace" "Eval")

(sdedr:define-refinement-window "BaseLine.nplus" "Line"

(position 3.0 0.0 0.0)

(position 3.7 0.0 0.0) )

(sdedr:define-gaussian-profile "Impl.nplusprof"

"NitrogenActiveConcentration"

"PeakPos" 0.0 "PeakVal" 1e21

"ValueAtDepth" 1e17 "Depth" 0.5

"Erf" "Length" 0.1)

(sdedr:define-analytical-profile-placement "Impl.nplus"

"Impl.nplusprof" "BaseLine.nplus" "Positive" "NoReplace" "Eval")

(sdedr:define-refinement-window "BaseLine.fieldstop" "Line"

(position 0.0 70.0 0.0)

(position 5.0 70.0 0.0) )

(sdedr:define-gaussian-profile "Impl.fieldstopprof"

"NitrogenActiveConcentration"

"PeakPos" 0.0 "PeakVal" 1e19

"ValueAtDepth" 1e15 "Depth" 3.0

"Erf" "Length" 0.1)

57

(sdedr:define-analytical-profile-placement "Impl.fieldstop"

"Impl.fieldstopprof" "BaseLine.fieldstop" "Negative" "NoReplace" "Eval")

(sdedr:define-refinement-window "BaseLine.collector" "Line"

(position 0.0 70.0 0.0)

(position 5.0 70.0 0.0) )

(sdedr:define-gaussian-profile "Impl.collectorprof"

"AluminumActiveConcentration"

"PeakPos" 0.1 "PeakVal" 1e20

"ValueAtDepth" 1e17 "Depth" 0.5

"Erf" "Length" 0.1)

(sdedr:define-analytical-profile-placement "Impl.collector"

"Impl.collectorprof" "BaseLine.collector" "Negative" "NoReplace" "Eval")

;----------------------------------------------------------------------;

Meshing

;----------------------------------------------------------------------;

(sdedr:define-refinement-window "RW.SiTop" "Rectangle"

(position 0.0 0.0 0.0 )

(position 4.8 6.0 0.0 ))

(sdedr:define-refinement-size "Ref.SiTop"

0.301 0.3751

0.05 0.05 )

(sdedr:define-refinement-function "Ref.SiTop"

"DopingConcentration" "MaxTransDiff" 1)

(sdedr:define-refinement-placement "RefPlace.SiTop"

"Ref.SiTop" "RW.SiTop" )

(sdedr:define-refinement-window "RW.SiMid" "Rectangle"

(position 0.0 6.0 0.0 )

(position 4.8 10.0 0.0 ))

(sdedr:define-refinement-size "Ref.SiMid"

0.601 0.751

0.03 0.03 )

(sdedr:define-refinement-function "Ref.SiMid"

"DopingConcentration" "MaxTransDiff" 1)

(sdedr:define-refinement-placement "RefPlace.SiMid"

"Ref.SiMid" "RW.SiMid" )

58

(sdedr:define-refinement-window "RW.SiBot" "Rectangle"

(position 0.0 10.0 0.0 )

(position 4.8 70.0 0.0 ))

(sdedr:define-refinement-size "Ref.SiBot"

1.201 2.001

0.05 0.05 )

(sdedr:define-refinement-function "Ref.SiBot"

"DopingConcentration" "MaxTransDiff" 1)

(sdedr:define-refinement-placement "RefPlace.SiBot"

"Ref.SiBot" "RW.SiBot" )

(sdedr:define-refinement-window "RW.TrBot" "Rectangle"

(position 1.8 1.5 0.0 )

(position 3.3 4.0 0.0 ))

(sdedr:define-refinement-size "Ref.TrBot"

0.1 0.1 0.05 0.05)

(sdedr:define-refinement-function "Ref.TrBot"

"DopingConcentration" "MaxTransDiff" 1)

(sdedr:define-refinement-placement "RefPlace.TrBot"

"Ref.TrBot" "RW.TrBot" )

;----------------------------------------------------------------------;

Meshing Offseting

;----------------------------------------------------------------------;

(sdenoffset:create-global

"usebox" 2

"maxangle" 180

"maxconnect" 1000000

"background" ""

"options" ""

"triangulate" 0

"recoverholes" 1

"hglobal" 5

"hlocal" 0

"factor" 1.3

"subdivide" 0

"terminateline" 3

59

"maxedgelength" 5

"maxlevel" 10)

(sdenoffset:create-noffset-block "region" "R.Si"

"maxedgelength" 5

"maxlevel" 10)

(sdenoffset:create-noffset-block "region" "R.Gox"

"maxedgelength" 5

"maxlevel" 2)

(sdenoffset:create-noffset-block "region" "R.PolyGate"

"maxedgelength" 0.25

"maxlevel" 4)

(sdenoffset:create-noffset-interface "region" "R.Si" "R.Gox"

"hlocal" 0.0015

"factor" 1.5)

(sdenoffset:create-noffset-interface "region" "R.Gox" "R.Si"

"hlocal" 0.01

"factor" 1.5)

(sdenoffset:create-noffset-interface "region" "R.PolyGate" "R.Gox"

"hlocal" 0.003

"factor" 1.5)

;----------------------------------------------------------------------

; Saving BND file

(sdeio:save-tdr-bnd (get-body-list) "20nm-bnd.tdr")

; Save CMD file

(sdedr:write-cmd-file "20nm-msh.cmd")

(system:command "snmesh -offset 20nm-msh")

;----------------------------------------------------------------------;

20nm High-k dielectric+ 1nm SiO2 as Gate Dielectric

(.des command file)

;----------------------------------------------------------------------;

(sdegeo:set-default-boolean "BAB")

(sdegeo:create-polygon (list

(position 2.0 0.0 0)

(position 2.1 3.19 0)

(position 2.7 3.19 0)

60

(position 2.788 0.0 0)

(position 2.0 0.0 0))

"PolySi" "R.PolyGate")

(sdegeo:fillet-2d (find-vertex-id (position 2.1 3.19 0)) 0.2)

(sdegeo:fillet-2d (find-vertex-id (position 2.7 3.19 0)) 0.2)

;----------------------------------------------------------------------;

20nm High-K Dielectric layer

;----------------------------------------------------------------------;

(sdegeo:create-polygon (list

(position 1.98 0.00 0)

(position 2.08 3.22 0)

(position 2.72 3.22 0)

(position 2.808 0.00 0)

(position 1.98 0.00 0))

"HfO2" "R.Gox")

(sdegeo:fillet-2d (find-vertex-id (position 2.08 3.22 0)) 0.2)

(sdegeo:fillet-2d (find-vertex-id (position 2.72 3.22 0)) 0.2)

;----------------------------------------------------------------------;

1nm SiO2 layer

;----------------------------------------------------------------------;

(sdegeo:create-polygon (list

(position 1.979 0.00 0)

(position 2.079 3.222 0)

(position 2.721 3.222 0)

(position 2.809 0.00 0)

(position 1.979 0.00 0))

"Oxide" "New")

(sdegeo:fillet-2d (find-vertex-id (position 2.079 3.222 0)) 0.2)

(sdegeo:fillet-2d (find-vertex-id (position 2.721 3.222 0)) 0.2)

(sdegeo:create-polygon (list

(position 2.00 0.02 0)

(position 1.50 0.02 0)

(position 1.30 0.22 0)

(position 0.00 0.22 0)

(position 0.00 -0.18 0)

61

(position 1.30 -0.18 0)

(position 1.50 0.00 0)

(position 2.00 0.00 0)

(position 2.00 0.02 0))

"Oxide" "R.LOCOS")

(sdegeo:fillet-2d (find-vertex-id (position 1.3 0.22 0)) 0.15)

(sdegeo:fillet-2d (find-vertex-id (position 1.3 -0.18 0)) 0.15)

(sdegeo:create-rectangle

(position 2.8 -0.3 0.0 )

(position 3.1 0.0 0.0 )

"Oxide" "R.Spacer" )

(sdegeo:create-rectangle

(position 0.0 0.0 0.0 )

(position 2.8 -0.3 0.0 )

"PolySi" "R.PolyCont" )

(sdegeo:create-rectangle

(position 0.0 0.0 0.0 )

(position 4.8 70.0 0.0 )

"SiliconCarbide" "R.SiC" )

; Rest Device Script remains same as previous case;

Static Characteristics

;———————————————————————-;

Transfer Characteristics(Ic-Vg)

(.des command file)

;———————————————————————-;

File {

Grid= "20nm-msh.tdr"

*Parameters= "@parameter@"

Plot= "Plot"

Current= "outputcurrent"

Output= "output" }

Electrode {

{ Name="Gate" Voltage= 0 }

{ Name="Emitter" Voltage= 0 }

{ Name="Collector" Voltage= 0 }}

62

Physics(MaterialInterface= "SiliconCarbide/Oxide")

{ Traps (FixedCharge Conc= 2E12) }

Physics {

Temperature= 300

Recombination (

SRH(DopingDependence

TempDependence)

Mobility (

DopingDependence

HighFieldSaturation

Enormal)

Aniso (

eMobilityFactor(Total)= 0.83

hMobilityFactor(Total)= 1.0 )

IncompleteIonization

EffectiveIntrinsicDensity

(BandGapNarrowing (Slotboom))}

Math {

ExtendedPrecision(128)

Iterations= 15

Notdamped= 1000

eDrForceRefDens= 1

hDrForceRefDens= 1

Digits= 5

ErrRef(electron) = 1

ErrRef(hole) = 1

Extrapolate

TensorGridAniso

RHSmin= 1e-30

RHSmax= 1e30

RHSFactor= 1e30

CDensityMin= 1e-30

ExitOnFailure

}

Plot {

63

TotalCurrentDensity/vector

eDensity hDensity

eCurrent hCurrent

ElectricField/vector

}

Solve {

*- Initial Solution

Coupled(Iterations=1000 LineSearchDamping=1e-2){ Poisson }

Coupled(Iterations=1000 LineSearchDamping=1e-2){ Poisson Electron }

Coupled(Iterations=1000 LineSearchDamping=1e-2){ Poisson Electron Hole}

*- Vc sweep

Quasistationary(

InitialStep= 1e-4 MinStep= 1e-5 MaxStep= 1.0

Increment= 1.5 Decrement= 2.0

Goal { Name="Collector" Voltage= 5.0 }

){ Coupled { Poisson Electron Hole } }

NewCurrentFile="IcVg"

*- Vg sweep

Quasistationary(

InitialStep= 1e-4 MinStep= 1e-5 MaxStep= 0.1

Increment= 1.5 Decrement= 2.0

Goal { Name="Gate" Voltage= 10.0 }

){ Coupled { Poisson Electron Hole }

CurrentPlot( Time=(Range=(0 1) Intervals= 40 ) )

}}

;----------------------------------------------------------------------;

Output Characteristics(Ic-Vc)

(.des command file)

;----------------------------------------------------------------------;

*- Vg sweep

Quasistationary(

InitialStep= 1e-4 MinStep= 1e-5 MaxStep= 1.0

Increment= 1.5 Decrement= 2.0

Goal { Name="Gate" Voltage= 5.0 }

){ Coupled { Poisson Electron Hole } }

64

NewCurrentFile="IcVc"

*- Vc sweep

Quasistationary(

InitialStep= 1e-4 MinStep= 1e-5 MaxStep= 0.1

Increment= 1.5 Decrement= 2.0

Goal { Name="Collector" Voltage= 10.0 }

){ Coupled { Poisson Electron Hole }

CurrentPlot( Time=(Range=(0 1) Intervals= 40 ) )

}}

; Rest Device Script remains same as previous case;

;----------------------------------------------------------------------;

Gate Leakage Characteristics

(.des command file)

;----------------------------------------------------------------------;

File {

Grid= "20nm-msh.tdr"

*Parameters= "@parameter@"

Plot= "Plot"

Current= "outputcurrent"

Output= "output" }

Electrode {

{ Name="Gate" Voltage= 0 }

{ Name="Emitter" Voltage= 0 }

{ Name="Collector" Voltage= 0 }}

Physics(MaterialInterface= "SiliconCarbide/Oxide")

{ Traps (FixedCharge Conc= 2E12) }

Physics {

Temperature= 300

Recombination (

SRH(DopingDependence

TempDependence)

Mobility (

DopingDependence

HighFieldSaturation

Enormal)

65

Aniso (

eMobilityFactor(Total)= 0.83

hMobilityFactor(Total)= 1.0 )

IncompleteIonization

EffectiveIntrinsicDensity

(BandGapNarrowing (Slotboom))}

Physics {

eBarrierTunneling "NLM" hBarrierTunneling "NLM"

}

Physics(MaterialInterface= "SiliconCarbide/Oxide")

{ GateCurrent(Fowler(EVB)) }

Math {

NonLocal "NLM" (Barrier(Material="SiliconCarbide" Material="Oxide"))}

Math {

ExtendedPrecision(128)

Iterations= 15

Notdamped= 1000

eDrForceRefDens= 1

hDrForceRefDens= 1

Digits= 5

ErrRef(electron) = 1

ErrRef(hole) = 1

Extrapolate

TensorGridAniso

RHSmin= 1e-30

RHSmax= 1e30

RHSFactor= 1e30

CDensityMin= 1e-30

ExitOnFailure

}

Plot {

TotalCurrentDensity/vector

eDensity hDensity

eCurrent hCurrent

ElectricField/vector

66

}

Solve {

*- Initial Solution

Coupled(Iterations=1000 LineSearchDamping=1e-2){ Poisson }

Coupled(Iterations=1000 LineSearchDamping=1e-2){ Poisson Electron }

Coupled(Iterations=1000 LineSearchDamping=1e-2){ Poisson Electron Hole}

*- Vc sweep

Quasistationary(

InitialStep= 1e-4 MinStep= 1e-5 MaxStep= 1.0

Increment= 1.5 Decrement= 2.0

Goal { Name="Collector" Voltage= 5.0 }

){ Coupled { Poisson Electron Hole } }

NewCurrentFile="IcVg"

*- Vg sweep

Quasistationary(

InitialStep= 1e-4 MinStep= 1e-5 MaxStep= 0.1

Increment= 1.5 Decrement= 2.0

Goal { Name="Gate" Voltage= 10.0 }

){ Coupled { Poisson Electron Hole }

CurrentPlot( Time=(Range=(0 1) Intervals= 40 ) )

}}

;----------------------------------------------------------------------;

Dynamic Characteristics

(.des command file)

;---------------------------------------------------------------------;

Dessis IGBT {

File {

Grid= "20nm-msh.tdr"

* Parameters= "@parameter@"

Plot= "@tdrdat@"

Current= "@plot@"}

Electrode {

{ Name="Gate" Voltage= 0 }

{ Name="Emitter" Voltage= 0 }

{ Name="Collector" Voltage= 0 }}

67

Physics(MaterialInterface= "SiliconCarbide/Oxide")

{ Traps (FixedCharge Conc= 2E12) }

Physics {

AreaFactor= 1e5

Temperature= 300

Recombination (

SRH(DopingDependence

TempDependence)

Mobility (

DopingDependence

HighFieldSaturation

Enormal)

Aniso (

eMobilityFactor(Total)= 0.83

hMobilityFactor(Total)= 1.0 )

IncompleteIonization

EffectiveIntrinsicDensity

(BandGapNarrowing (Slotboom))}

Plot {

TotalCurrentDensity/vector

eDensity hDensity

eCurrent hCurrent

ElectricField/vector

}

Math {

ExtendedPrecision(128)

Iterations= 15

Notdamped= 1000

eDrForceRefDens= 1

hDrForceRefDens= 1

Digits= 5

ErrRef(electron) = 1

ErrRef(hole) = 1

Extrapolate

TensorGridAniso

68

RHSmin= 1e-30

RHSmax= 1e30

RHSFactor= 1e30

CDensityMin= 1e-30

ExitOnFailure

}

System {

IGBT IGBT1 (Emitter=0 Gate=2 Collector=3)

Vsource pset vc (4 0) { dc= 0 }

Vsource pset vg (1 0) { pwl= (0 0 2e-7 0 4e-7 15 1e-6 15 1.2e-6 0 3e-6 0)}

Diode pset circuit diode (3 4)

Inductor pset lc (4 3) { inductance=1e-4 }

Resistor pset rg (2 1) { resistance= 470 }

Plot "dynamic characteristics" (time() v(1) v(3) v(4) i(lc 3))}

Solve {

Coupled { Poisson Electron Hole }

Quasistationary (

InitialStep= 1e-5 Increment= 1.35

MinStep= 1e-7 MaxStep= 0.05

Goal { Parameter= vc.dc Value=400) }

{ Coupled { Poisson Electron Hole } }

NewCurrentPrefix="Transient@300K"

Transient (

InitialTime= 0 FinalTime= 3e-5

InitialStep= 1e-8 Increment= 1.35 Decrement= 4

MinStep= 1e-14 MaxStep= 1e-7)

{ Coupled { Poisson Electron Hole }}}

;----------------------------------------------------------------------;

69

Related Publications

1. Proceedings of European Conference on Silicon Carbide and Related Materials (ECSCRM) 2016,to be published by the Trans Tech Publication Co. in the Materials Science Forum journal.

70

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